368 lines
17 KiB
C++
368 lines
17 KiB
C++
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/********************************************************************
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* This file includes functions that are used for building bitstreams
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* for grids (CLBs, heterogenerous blocks, I/Os, etc.)
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*******************************************************************/
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#include <string>
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Headers from vpr library */
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#include "vpr_utils.h"
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#include "mux_utils.h"
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#include "circuit_library_utils.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "mux_bitstream_constants.h"
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#include "pb_type_utils.h"
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#include "build_mux_bitstream.h"
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//#include "build_lut_bitstream.h"
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#include "build_grid_bitstream.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Decode mode bits "01..." to a bitstream vector
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*******************************************************************/
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static
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std::vector<bool> generate_mode_select_bitstream(const std::vector<size_t>& mode_bits) {
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std::vector<bool> mode_select_bitstream;
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for (const size_t& mode_bit : mode_bits) {
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/* Error out for unexpected bits */
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VTR_ASSERT((0 == mode_bit) || (1 == mode_bit));
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mode_select_bitstream.push_back(1 == mode_bit);
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}
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return mode_select_bitstream;
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}
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/********************************************************************
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* Generate bitstream for a primitive node and add it to bitstream manager
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*******************************************************************/
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static
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void build_primitive_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& parent_configurable_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const VprDeviceAnnotation& device_annotation,
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const PhysicalPb& physical_pb,
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const PhysicalPbId& primitive_pb_id,
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t_pb_type* primitive_pb_type) {
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/* Ensure a valid physical pritimive pb */
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if (nullptr == primitive_pb_type) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid primitive_pb_type!\n");
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exit(1);
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}
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CircuitModelId primitive_model = device_annotation.pb_type_circuit_model(primitive_pb_type);
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VTR_ASSERT(CircuitModelId::INVALID() != primitive_model);
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VTR_ASSERT( (CIRCUIT_MODEL_IOPAD == circuit_lib.model_type(primitive_model))
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|| (CIRCUIT_MODEL_HARDLOGIC == circuit_lib.model_type(primitive_model))
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|| (CIRCUIT_MODEL_FF == circuit_lib.model_type(primitive_model)) );
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/* Find SRAM ports for mode-selection */
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std::vector<CircuitPortId> primitive_mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, primitive_model);
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/* We may have a port for mode select or not. */
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VTR_ASSERT( (0 == primitive_mode_select_ports.size())
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|| (1 == primitive_mode_select_ports.size()) );
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/* Generate bitstream for mode-select ports */
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if (0 == primitive_mode_select_ports.size()) {
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return; /* Nothing to do, return directly */
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}
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std::vector<bool> mode_select_bitstream;
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if (true == physical_pb.valid_pb_id(primitive_pb_id)) {
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mode_select_bitstream = generate_mode_select_bitstream(physical_pb.mode_bits(primitive_pb_id));
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} else { /* get default mode_bits */
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mode_select_bitstream = generate_mode_select_bitstream(device_annotation.pb_type_mode_bits(primitive_pb_type));
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}
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/* Ensure the length of bitstream matches the side of memory circuits */
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std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, primitive_model);
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VTR_ASSERT(1 == sram_models.size());
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std::string mem_block_name = generate_memory_module_name(circuit_lib, primitive_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
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ModuleId mem_module = module_manager.find_module(mem_block_name);
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VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
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ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name());
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VTR_ASSERT(mode_select_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width());
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/* Create a block for the bitstream which corresponds to the memory module associated to the LUT */
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ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name);
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bitstream_manager.add_child_block(parent_configurable_block, mem_block);
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/* Add the bitstream to the bitstream manager */
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for (const bool& bit : mode_select_bitstream) {
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ConfigBitId config_bit = bitstream_manager.add_bit(bit);
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/* Link the memory bits to the mux mem block */
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bitstream_manager.add_bit_to_block(mem_block, config_bit);
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}
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}
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/********************************************************************
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* This function generates bitstream for a physical block, which is
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* a child block of a grid
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* This function will follow a recursive way in generating bitstreams
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* It will follow the same sequence in visiting all the sub blocks
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* in a physical as we did during module generation
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*
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* Note: if you want to bind your bitstream with a FPGA fabric generated by FPGA-X2P
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* Please follow the same sequence in visiting pb_graph nodes!!!
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* For more details, you may refer to function rec_build_physical_block_modules()
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*******************************************************************/
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static
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void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& parent_configurable_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const VprDeviceAnnotation& device_annotation,
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const e_side& border_side,
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const PhysicalPb& physical_pb,
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const PhysicalPbId& pb_id,
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t_pb_graph_node* physical_pb_graph_node,
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const size_t& pb_graph_node_index) {
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/* Get the physical pb_type that is linked to the pb_graph node */
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t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
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/* Find the mode that define_idle_mode*/
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t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
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/* Create a block for the physical block under the grid block in bitstream manager */
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std::string pb_block_name = generate_physical_block_instance_name(physical_pb_type, pb_graph_node_index);
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ConfigBlockId pb_configurable_block = bitstream_manager.add_block(pb_block_name);
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bitstream_manager.add_child_block(parent_configurable_block, pb_configurable_block);
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/* Recursively finish all the child pb_types*/
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if (false == is_primitive_pb_type(physical_pb_type)) {
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for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
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for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
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PhysicalPbId child_pb = PhysicalPbId::INVALID();
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/* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */
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if (true == physical_pb.valid_pb_id(pb_id)) {
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child_pb = physical_pb.child(pb_id, &(physical_mode->pb_type_children[ipb]), jpb);
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VTR_ASSERT(true == physical_pb.valid_pb_id(child_pb));
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}
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/* Go recursively */
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rec_build_physical_block_bitstream(bitstream_manager, pb_configurable_block,
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module_manager, circuit_lib, mux_lib,
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device_annotation,
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border_side,
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physical_pb, child_pb,
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&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
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jpb);
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}
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}
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}
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/* Check if this has defined a circuit_model*/
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if (true == is_primitive_pb_type(physical_pb_type)) {
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switch (physical_pb_type->class_type) {
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case LUT_CLASS:
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/* Special case for LUT !!!
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* Mapped logical block information is stored in child_pbs of this pb!!!
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*/
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//build_lut_bitstream(bitstream_manager, pb_configurable_block,
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// module_manager, circuit_lib, mux_lib,
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// physical_pb, pb_id, physical_pb_type);
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break;
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case LATCH_CLASS:
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case UNKNOWN_CLASS:
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case MEMORY_CLASS:
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/* For other types of blocks, we can apply a generic therapy */
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build_primitive_bitstream(bitstream_manager, pb_configurable_block,
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module_manager, circuit_lib, device_annotation,
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physical_pb, pb_id, physical_pb_type);
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Unknown class type of pb_type '%s'!\n",
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physical_pb_type->name);
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exit(1);
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}
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/* Finish for primitive node, return */
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return;
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}
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/* Generate the bitstream for the interconnection in this physical block */
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//build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block,
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// module_manager, circuit_lib, mux_lib,
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// physical_pb_graph_node, physical_pb,
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// pb_id, physical_mode_index);
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}
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/********************************************************************
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* This function generates bitstream for a grid, which could be a
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* CLB, a heterogenerous block, an I/O, etc.
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* Note that each grid may contain a number of physical blocks,
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* this function will iterate over them
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*******************************************************************/
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static
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void build_physical_block_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& top_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const VprDeviceAnnotation& device_annotation,
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const VprClusteringAnnotation& cluster_annotation,
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const VprPlacementAnnotation& place_annotation,
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const DeviceGrid& grids,
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const vtr::Point<size_t>& grid_coord,
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const e_side& border_side) {
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/* Create a block for the grid in bitstream manager */
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t_physical_tile_type_ptr grid_type = grids[grid_coord.x()][grid_coord.y()].type;
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std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
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std::string grid_block_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name),
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is_io_type(grid_type), border_side, grid_coord);
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ConfigBlockId grid_configurable_block = bitstream_manager.add_block(grid_block_name);
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bitstream_manager.add_child_block(top_block, grid_configurable_block);
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/* Iterate over the capacity of the grid
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* Now each physical tile may have a number of logical blocks
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* OpenFPGA only considers the physical implementation of the tiles.
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* So, we do not allow multiple equivalent sites to be defined
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* under a physical tile type.
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* If you need different equivalent sites, you can always define
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* it as a mode under a <pb_type>
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*/
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for (size_t z = 0; z < place_annotation.grid_blocks(grid_coord).size(); ++z) {
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VTR_ASSERT(1 == grid_type->equivalent_sites.size());
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for (t_logical_block_type_ptr lb_type : grid_type->equivalent_sites) {
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/* Bypass empty pb_graph */
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if (nullptr == lb_type->pb_graph_head) {
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continue;
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}
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if (ClusterBlockId::INVALID() == place_annotation.grid_blocks(grid_coord)[z]) {
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/* Recursively traverse the pb_graph and generate bitstream */
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rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block,
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module_manager, circuit_lib, mux_lib,
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device_annotation, border_side,
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PhysicalPb(), PhysicalPbId::INVALID(),
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lb_type->pb_graph_head, z);
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} else {
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const PhysicalPb& phy_pb = cluster_annotation.physical_pb(place_annotation.grid_blocks(grid_coord)[z]);
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/* Get the top-level node of the pb_graph */
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t_pb_graph_node* pb_graph_head = lb_type->pb_graph_head;
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VTR_ASSERT(nullptr != pb_graph_head);
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const PhysicalPbId& top_pb_id = phy_pb.find_pb(pb_graph_head);
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/* Recursively traverse the pb_graph and generate bitstream */
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rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block,
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module_manager, circuit_lib, mux_lib,
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device_annotation, border_side,
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phy_pb, top_pb_id, pb_graph_head, z);
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}
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}
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}
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}
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/********************************************************************
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* Top-level function of this file:
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* Generate bitstreams for all the grids, including
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* 1. core grids that sit in the center of the fabric
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* 2. side grids (I/O grids) that sit in the borders for the fabric
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*******************************************************************/
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void build_grid_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& top_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const DeviceGrid& grids,
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const VprDeviceAnnotation& device_annotation,
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const VprClusteringAnnotation& cluster_annotation,
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const VprPlacementAnnotation& place_annotation,
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const bool& verbose) {
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VTR_LOGV(verbose, "Generating bitstream for core grids...");
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/* Generate bitstream for the core logic block one by one */
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for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
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for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
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/* Bypass EMPTY grid */
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if (true == is_empty_type(grids[ix][iy].type)) {
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continue;
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}
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/* Skip width > 1 or height > 1 tiles (mostly heterogeneous blocks) */
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if ( (0 < grids[ix][iy].width_offset)
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continue;
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}
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/* We should not meet any I/O grid */
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VTR_ASSERT(true != is_io_type(grids[ix][iy].type));
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/* Add a grid module to top_module*/
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vtr::Point<size_t> grid_coord(ix, iy);
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build_physical_block_bitstream(bitstream_manager, top_block, module_manager,
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circuit_lib, mux_lib,
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device_annotation, cluster_annotation,
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place_annotation,
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grids, grid_coord, NUM_SIDES);
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}
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}
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VTR_LOGV(verbose, "Done\n");
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VTR_LOGV(verbose, "Generating bitstream for I/O grids...");
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/* Create the coordinate range for each side of FPGA fabric */
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std::vector<e_side> io_sides{TOP, RIGHT, BOTTOM, LEFT};
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std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates;
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/* TOP side*/
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for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
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io_coordinates[TOP].push_back(vtr::Point<size_t>(ix, grids.height() - 1));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* RIGHT side */
|
||
|
|
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
|
||
|
|
io_coordinates[RIGHT].push_back(vtr::Point<size_t>(grids.width() - 1, iy));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* BOTTOM side*/
|
||
|
|
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
|
||
|
|
io_coordinates[BOTTOM].push_back(vtr::Point<size_t>(ix, 0));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* LEFT side */
|
||
|
|
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
|
||
|
|
io_coordinates[LEFT].push_back(vtr::Point<size_t>(0, iy));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Add instances of I/O grids to top_module */
|
||
|
|
for (const e_side& io_side : io_sides) {
|
||
|
|
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
|
||
|
|
/* Bypass EMPTY grid */
|
||
|
|
if (true == is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
/* Skip height > 1 tiles (mostly heterogeneous blocks) */
|
||
|
|
if ( (0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset)
|
||
|
|
|| (0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset) ) {
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
/* We should not meet any I/O grid */
|
||
|
|
VTR_ASSERT(true == is_io_type(grids[io_coordinate.x()][io_coordinate.y()].type));
|
||
|
|
build_physical_block_bitstream(bitstream_manager, top_block, module_manager,
|
||
|
|
circuit_lib, mux_lib,
|
||
|
|
device_annotation, cluster_annotation,
|
||
|
|
place_annotation,
|
||
|
|
grids, io_coordinate, io_side);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
VTR_LOGV(verbose, "Done\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
} /* end namespace openfpga */
|