2018-07-26 12:28:21 -05:00
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#ifndef SETUPVPR_H
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#define SETUPVPR_H
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2019-04-26 13:23:47 -05:00
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void VPRSetupArch(t_arch* arch,
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t_det_routing_arch* RoutingArch,
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t_segment_inf ** Segments,
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t_swseg_pattern_inf** swseg_patterns,
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t_model** user_models,
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t_model** library_models);
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void alloc_and_init_globals_clb_to_clb_directs(int num_directs,
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t_direct_inf* directs);
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2018-07-26 12:28:21 -05:00
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void SetupVPR(INP t_options *Options,
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INP boolean TimingEnabled,
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INP boolean readArchFile,
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OUTP struct s_file_name_opts *FileNameOpts,
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INOUTP t_arch * Arch,
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OUTP enum e_operation *Operation,
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OUTP t_model ** user_models,
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OUTP t_model ** library_models,
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OUTP struct s_packer_opts *PackerOpts,
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OUTP struct s_placer_opts *PlacerOpts,
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OUTP struct s_annealing_sched *AnnealSched,
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OUTP struct s_router_opts *RouterOpts,
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OUTP struct s_det_routing_arch *RoutingArch,
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OUTP t_segment_inf ** Segments,
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OUTP t_timing_inf * Timing,
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OUTP boolean * ShowGraphics,
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OUTP int *GraphPause,
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OUTP t_power_opts * power_opts,
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/*Xifan TANG: Switch Segment Pattern Support*/
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OUTP t_swseg_pattern_inf** swseg_patterns,
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/* Xifan TANG: FPGA-SPICE Support*/
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OUTP t_fpga_spice_opts* fpga_spice_opts);
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void CheckSetup(INP enum e_operation Operation,
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INP struct s_placer_opts PlacerOpts,
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INP struct s_annealing_sched AnnealSched,
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INP struct s_router_opts RouterOpts,
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INP struct s_det_routing_arch RoutingArch,
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INP t_segment_inf * Segments,
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INP t_timing_inf Timing,
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INP t_chan_width_dist Chans);
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void CheckArch(INP t_arch Arch,
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INP boolean TimingEnabled);
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void CheckOptions(INP t_options Options,
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INP boolean TimingEnabled);
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void ShowSetup(INP t_options options, INP t_vpr_setup vpr_setup);
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void printClusteredNetlistStats(void);
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#endif
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