23 lines
360 B
Plaintext
23 lines
360 B
Plaintext
|
# Yosys synthesis script for ${TOP_MODULE}
|
||
|
|
# Read verilog files
|
||
|
|
${READ_VERILOG_FILE}
|
||
|
|
|
||
|
|
# Technology mapping
|
||
|
|
hierarchy -top ${TOP_MODULE}
|
||
|
|
proc
|
||
|
|
techmap -D NO_LUT -map +/adff2dff.v
|
||
|
|
|
||
|
|
# Synthesis
|
||
|
|
synth -top ${TOP_MODULE} -flatten
|
||
|
|
clean
|
||
|
|
|
||
|
|
# LUT mapping
|
||
|
|
abc -lut ${LUT_SIZE}
|
||
|
|
|
||
|
|
# Check
|
||
|
|
synth -run check
|
||
|
|
|
||
|
|
# Clean and output blif
|
||
|
|
opt_clean -purge
|
||
|
|
write_blif ${OUTPUT_BLIF}
|