559 lines
9.5 KiB
Plaintext
559 lines
9.5 KiB
Plaintext
entity muxe is
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port (
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accu : in bit_vector(3 downto 0);
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d : in bit_vector(3 downto 0);
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i : in bit_vector(2 downto 0);
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r : out bit_vector(3 downto 0);
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ra : in bit_vector(3 downto 0);
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rb : in bit_vector(3 downto 0);
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s : out bit_vector(3 downto 0);
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vdd : in bit;
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vss : in bit
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);
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end muxe;
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architecture structural of muxe is
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Component o2_x2
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component on12_x1
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component inv_x2
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port (
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i : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component o3_x2
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component no4_x1
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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i3 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component na3_x1
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component na2_x1
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port (
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i0 : in bit;
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i1 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component a2_x2
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component nao22_x1
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component no2_x1
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port (
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i0 : in bit;
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i1 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component an12_x1
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component no3_x1
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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signal not_i : bit_vector( 2 downto 0);
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signal on12_x1_sig : bit;
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signal on12_x1_2_sig : bit;
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signal o3_x2_sig : bit;
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signal o3_x2_2_sig : bit;
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signal not_aux2 : bit;
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signal not_aux1 : bit;
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signal not_aux0 : bit;
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signal no2_x1_sig : bit;
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signal no2_x1_5_sig : bit;
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signal no2_x1_4_sig : bit;
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signal no2_x1_3_sig : bit;
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signal no2_x1_2_sig : bit;
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signal nao22_x1_sig : bit;
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signal na3_x1_sig : bit;
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signal na3_x1_6_sig : bit;
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signal na3_x1_5_sig : bit;
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signal na3_x1_4_sig : bit;
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signal na3_x1_3_sig : bit;
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signal na3_x1_2_sig : bit;
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signal na2_x1_sig : bit;
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signal na2_x1_3_sig : bit;
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signal na2_x1_2_sig : bit;
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signal inv_x2_sig : bit;
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signal inv_x2_2_sig : bit;
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signal aux4 : bit;
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signal aux3 : bit;
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signal an12_x1_sig : bit;
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signal an12_x1_2_sig : bit;
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signal a2_x2_sig : bit;
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signal a2_x2_2_sig : bit;
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begin
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not_aux2_ins : a2_x2
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port map (
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i0 => not_aux0,
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i1 => not_i(0),
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q => not_aux2,
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vdd => vdd,
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vss => vss
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);
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not_aux1_ins : o2_x2
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port map (
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i0 => i(0),
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i1 => not_aux0,
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q => not_aux1,
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vdd => vdd,
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vss => vss
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);
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not_aux0_ins : a2_x2
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port map (
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i0 => i(2),
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i1 => not_i(1),
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q => not_aux0,
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vdd => vdd,
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vss => vss
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);
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not_i_2_ins : inv_x2
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port map (
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i => i(2),
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nq => not_i(2),
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vdd => vdd,
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vss => vss
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);
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not_i_1_ins : inv_x2
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port map (
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i => i(1),
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nq => not_i(1),
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vdd => vdd,
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vss => vss
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);
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not_i_0_ins : inv_x2
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port map (
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i => i(0),
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nq => not_i(0),
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vdd => vdd,
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vss => vss
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);
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aux4_ins : an12_x1
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port map (
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i0 => i(1),
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i1 => ra(3),
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q => aux4,
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vdd => vdd,
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vss => vss
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);
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aux3_ins : an12_x1
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port map (
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i0 => i(1),
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i1 => ra(1),
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q => aux3,
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vdd => vdd,
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vss => vss
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);
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na3_x1_ins : na3_x1
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port map (
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i0 => rb(0),
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i1 => i(0),
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i2 => not_i(2),
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nq => na3_x1_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_2_ins : na3_x1
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port map (
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i0 => ra(0),
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i1 => i(2),
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i2 => not_i(1),
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nq => na3_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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on12_x1_ins : on12_x1
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port map (
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i0 => accu(0),
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i1 => not_aux1,
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q => on12_x1_sig,
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vdd => vdd,
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vss => vss
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);
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s_0_ins : na3_x1
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port map (
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i0 => on12_x1_sig,
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i1 => na3_x1_2_sig,
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i2 => na3_x1_sig,
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nq => s(0),
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vdd => vdd,
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vss => vss
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);
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na2_x1_ins : na2_x1
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port map (
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i0 => i(2),
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i1 => aux3,
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nq => na2_x1_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_3_ins : na3_x1
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port map (
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i0 => rb(1),
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i1 => i(0),
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i2 => not_i(2),
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nq => na3_x1_3_sig,
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vdd => vdd,
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vss => vss
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);
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on12_x1_2_ins : on12_x1
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port map (
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i0 => accu(1),
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i1 => not_aux1,
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q => on12_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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s_1_ins : na3_x1
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port map (
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i0 => on12_x1_2_sig,
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i1 => na3_x1_3_sig,
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i2 => na2_x1_sig,
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nq => s(1),
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vdd => vdd,
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vss => vss
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);
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inv_x2_ins : inv_x2
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port map (
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i => accu(2),
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nq => inv_x2_sig,
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vdd => vdd,
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vss => vss
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);
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o3_x2_ins : o3_x2
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port map (
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i0 => i(0),
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i1 => not_aux0,
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i2 => inv_x2_sig,
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q => o3_x2_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_4_ins : na3_x1
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port map (
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i0 => rb(2),
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i1 => i(0),
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i2 => not_i(2),
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nq => na3_x1_4_sig,
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vdd => vdd,
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vss => vss
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);
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na2_x1_2_ins : na2_x1
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port map (
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i0 => ra(2),
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i1 => not_aux0,
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nq => na2_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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s_2_ins : na3_x1
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port map (
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i0 => na2_x1_2_sig,
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i1 => na3_x1_4_sig,
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i2 => o3_x2_sig,
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nq => s(2),
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vdd => vdd,
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vss => vss
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);
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a2_x2_ins : a2_x2
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port map (
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i0 => rb(3),
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i1 => accu(3),
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q => a2_x2_sig,
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vdd => vdd,
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vss => vss
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);
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nao22_x1_ins : nao22_x1
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port map (
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i0 => i(2),
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i1 => a2_x2_sig,
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i2 => aux4,
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nq => nao22_x1_sig,
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vdd => vdd,
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vss => vss
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);
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inv_x2_2_ins : inv_x2
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port map (
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i => accu(3),
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nq => inv_x2_2_sig,
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vdd => vdd,
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vss => vss
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);
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o3_x2_2_ins : o3_x2
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port map (
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i0 => i(0),
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i1 => not_aux0,
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i2 => inv_x2_2_sig,
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q => o3_x2_2_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_5_ins : na3_x1
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port map (
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i0 => rb(3),
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i1 => i(0),
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i2 => not_i(2),
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nq => na3_x1_5_sig,
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vdd => vdd,
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vss => vss
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);
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s_3_ins : na3_x1
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port map (
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i0 => na3_x1_5_sig,
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i1 => o3_x2_2_sig,
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i2 => nao22_x1_sig,
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nq => s(3),
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vdd => vdd,
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vss => vss
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);
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no2_x1_ins : no2_x1
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port map (
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i0 => ra(0),
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i1 => i(2),
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nq => no2_x1_sig,
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vdd => vdd,
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vss => vss
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);
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no2_x1_2_ins : no2_x1
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port map (
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i0 => i(2),
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i1 => not_i(1),
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nq => no2_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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no2_x1_3_ins : no2_x1
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port map (
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i0 => d(0),
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i1 => not_i(2),
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nq => no2_x1_3_sig,
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vdd => vdd,
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vss => vss
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);
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r_0_ins : no4_x1
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port map (
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i0 => no2_x1_3_sig,
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i1 => not_aux2,
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i2 => no2_x1_2_sig,
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i3 => no2_x1_sig,
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nq => r(0),
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vdd => vdd,
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vss => vss
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);
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no2_x1_4_ins : no2_x1
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port map (
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i0 => d(1),
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i1 => not_i(2),
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nq => no2_x1_4_sig,
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vdd => vdd,
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vss => vss
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);
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an12_x1_ins : an12_x1
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port map (
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i0 => aux3,
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i1 => not_i(2),
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q => an12_x1_sig,
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vdd => vdd,
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vss => vss
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);
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r_1_ins : no3_x1
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port map (
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i0 => not_aux2,
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i1 => an12_x1_sig,
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i2 => no2_x1_4_sig,
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nq => r(1),
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vdd => vdd,
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vss => vss
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);
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na3_x1_6_ins : na3_x1
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port map (
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i0 => ra(2),
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i1 => not_i(1),
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i2 => not_i(2),
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nq => na3_x1_6_sig,
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vdd => vdd,
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vss => vss
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);
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na2_x1_3_ins : na2_x1
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port map (
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i0 => d(2),
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i1 => i(2),
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nq => na2_x1_3_sig,
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vdd => vdd,
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vss => vss
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);
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a2_x2_2_ins : a2_x2
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port map (
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i0 => not_i(1),
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i1 => not_i(0),
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q => a2_x2_2_sig,
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vdd => vdd,
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vss => vss
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);
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r_2_ins : nao22_x1
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port map (
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i0 => a2_x2_2_sig,
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i1 => na2_x1_3_sig,
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i2 => na3_x1_6_sig,
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nq => r(2),
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vdd => vdd,
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vss => vss
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);
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no2_x1_5_ins : no2_x1
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port map (
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i0 => d(3),
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i1 => not_i(2),
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nq => no2_x1_5_sig,
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vdd => vdd,
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vss => vss
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);
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an12_x1_2_ins : an12_x1
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port map (
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i0 => aux4,
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i1 => not_i(2),
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q => an12_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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r_3_ins : no3_x1
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port map (
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i0 => not_aux2,
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i1 => an12_x1_2_sig,
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i2 => no2_x1_5_sig,
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nq => r(3),
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vdd => vdd,
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vss => vss
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);
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end structural;
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