eab4a4aa7f
* Bug: In CRL/BlifParser::Model::mergeAlias(), when a signal is aliased
toward $true or $false in a Blif file (through a ".name" statement),
it was directly merged to "vdd" (resp. "vss"), and if it is an
external signal, this leads to its removal, potentially making "hole"
in its interface.
Now, create a gate zero or one for each tied up/low signal. This
way the interface is fully kept. At the cost of some supplemental
gates.
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| CMakeLists.txt | ||