1194 lines
44 KiB
Python
1194 lines
44 KiB
Python
#!/usr/bin/python
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# This file is part of the Coriolis Project.
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# Copyright (C) Laboratoire LIP6 - Departement ASIM
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# Universite Pierre et Marie Curie
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#
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# Main contributors :
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# Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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# Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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# Hugo Clement <Hugo.Clement@lip6.fr>
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# Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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# Damien Dupuis <Damien.Dupuis@lip6.fr>
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# Christian Masson <Christian.Masson@lip6.fr>
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# Marek Sroka <Marek.Sroka@lip6.fr>
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#
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# The Coriolis Project is free software; you can redistribute it
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# and/or modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# The Coriolis Project is distributed in the hope that it will be
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# useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with the Coriolis Project; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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#
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# License-Tag
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# Authors-Tag
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# ===================================================================
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#
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# x-----------------------------------------------------------------x
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# | |
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./st_net.py" |
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# | *************************************************************** |
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# | U p d a t e s |
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# | |
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# x-----------------------------------------------------------------x
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import CRL
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from Hurricane import *
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from st_model import Model
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from st_instance import Inst
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from st_generate import Generate
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import re, types, inspect
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## Class of nets ##
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PORT = ( "st_net.SignalIn", "st_net.SignalOut", "st_net.SignalInOut" \
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, "st_net.SignalUnknown", "st_net.TriState" \
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)
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#####################
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##### Class net #####
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#####################
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class net :
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# Creation of the instance : coded for each herited class
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def __init__ ( self, nbit ) : pass
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# Deletion of the instance : the same for each net
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def Delete ( self ) :
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# Erasement of the references to the net
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if str ( self.__class__ ) in PORT :
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for i in range ( len ( self._st_cell._st_ports ) ) :
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if self._st_cell._st_ports[i] == self :
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del self._st_cell._st_ports[i]
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break
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else :
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for i in range ( len ( self._st_cell._st_sigs ) ) :
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if self._st_cell._st_sigs[i] == self :
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del self._st_cell._st_sigs[i]
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break
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for net in self._st_cell._st_sigs :
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if "_to_merge" in net.__dict__ :
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if len ( net._to_merge ) :
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for i in range ( len ( net._to_merge ) ):
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if net._to_merge[i] != 0 :
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if net._to_merge[i][0] == self : net._to_merge[i] = 0 # Erasement of a reference of the net
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non = False
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# Erasement of the net which wes going to be merged to the net being deleted
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for i in range ( len ( net._to_merge ) ) :
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if net._to_merge[i] != 0 :
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non = True
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break
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if not non : net.Delete()
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# Erasement in the connections
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for inst in self._st_cell._st_insts :
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for pin in inst._map :
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if self == inst._map[pin] :
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del inst._map[pin]
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break
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# Erasement of the huricane nets associated
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for hurNet in self._hur_net :
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if hurNet : hurNet.Delete()
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##### For buses #####
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def __getitem__ ( self, indice ) :
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if indice == -1:
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return Sig ( self, self._ind + self._arity - 1 )
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if ( indice < self._ind ) or ( indice >= ( self._ind + self._arity ) ) :
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err = "\n[Stratus ERROR] [] : bad index " + str(indice) + " for net : " \
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+ self._name + " of arity " + str(self._arity)
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if self._ind != 0 : err += " and LSB " + str(self._ind)
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err += ".\n"
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raise Exception ( err )
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return Sig ( self, indice )
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def __getslice__ ( self, ind1, ind2 ) :
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if ind1 < ind2 :
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indmin = ind1
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indmax = ind2
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else :
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indmin = ind2
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indmax = ind1
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# Errors
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if ( (indmax-indmin) < 1 ) or ( (indmax-indmin) > self._arity ) :
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err = "\n[Stratus ERROR] [:] : bad indexes " + str(indmax) + ", and " + str(indmin) \
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+ " for net : " + self._name + " of arity " + str(self._arity)
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if self._ind != 0 : err += " and LSB " + str(self._ind)
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err += ".\n"
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raise Exception ( err )
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if ( indmax >= ( self._ind + self._arity ) ) or ( indmin < self._ind ) :
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err = "\n[Stratus ERROR] [:] : bad indexes " + str(indmax) + ", and " + str(indmin) \
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+ " for net : " + self._name + " of arity " + str(self._arity)
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if self._ind != 0 : err += " and LSB " + str(self._ind)
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err += ".\n"
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raise Exception ( err )
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return Sig ( self, ind1, ind2 )
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##### To affect a signal : <= #####
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def __le__ ( self, net ) :
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global CELLS
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from st_model import CELLS
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cell = CELLS[-1]
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### Initialisation of net representing a constant ###
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if type ( net ) == types.StringType :
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from st_const import Constant
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if not ( cell._st_vdds ) or not ( cell._st_vsss ) :
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err = "\n[Stratus ERROR] : there is no alim.\n"
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raise Exception ( err )
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constParam = { 'nb' : net }
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string = Constant.getString ( constParam )
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num_net = len ( cell._TAB_NETS_OUT )
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cell._TAB_NETS_OUT += [Signal ( "cst_o%d" % num_net, len ( string ) )]
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# 3 possible constant operator output name (nq,q,output) => 3 differents map
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if string == "0" :
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inst_name = "zero"
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map_cst = { 'nq' : cell._TAB_NETS_OUT[num_net]
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, 'vdd': cell._st_vdds[0]
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, 'vss': cell._st_vsss[0]
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}
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elif string == "1" :
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inst_name = "one"
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map_cst = { 'q' : cell._TAB_NETS_OUT[num_net]
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, 'vdd': cell._st_vdds[0]
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, 'vss': cell._st_vsss[0]
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}
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else :
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inst_name = Constant.getModelName ( constParam )
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map_cst = { 'o': cell._TAB_NETS_OUT[num_net]
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, 'vdd': cell._st_vdds[0]
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, 'vss': cell._st_vsss[0]
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}
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Generate ( "Constant", inst_name, param = constParam )
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Inst ( inst_name
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, map = map_cst
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)
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net = cell._TAB_NETS_OUT[num_net]
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### Merging of two nets ###
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# Resizement of the output net if needed thanks to the input net's lenght
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if not ( self._arity ) : self.create_net ( self._name, net._arity )
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# Error if the nets don t have the same size
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if self._arity - net._arity :
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err = "\n[Stratus ERROR] <= : the nets " + self._name + " " + str(self._arity) + " and " + net._name + " " + str(net._arity) \
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+ " must have the same lenght\n"
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raise Exception ( err )
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# If the nets are virtual, Let s work with the corresponding real nets
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if self._real_net : netInCell = self._real_net
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else : netInCell = self
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if net._real_net : netToMerge = net._real_net
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else : netToMerge = net
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# Error if self is an input net
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if ( netInCell._ext ) and ( netInCell._direct == "IN" ) :
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err = "\n[Stratus ERROR] <= : " + self._name + " One can not give a value to an input net.\n"
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raise Exception ( err )
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if netToMerge._ext :
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err = "\n[Stratus ERROR] <= : " + self._name
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# Error if net is an output net
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if netToMerge._direct == "OUT" : err += " One can not initialise a net with an output net.\n"
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# Error if net is an input net
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elif netToMerge._direct == "IN" : err += " One can not initialise a net with an input net. The method Buffer() should be used.\n"
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raise Exception ( err )
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# Construction of the tab if needed
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if not ( len ( netToMerge._to_merge ) ) :
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for i in range ( netToMerge._arity ) : netToMerge._to_merge.append ( 0 )
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# Initialisation of _to_merge
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for i in range ( net._arity ) : netToMerge._to_merge[i+net._ind] = [netInCell, i+self._ind]
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# Puts the net in the list of nets to merge in order to have them in the right order
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self._st_cell._st_merge.append ( net )
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if self._st_cell._hur_cell :
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net.hur_merge()
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#for i in range ( net._arity ) :
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# CRL.createPartRing ( self._st_cell._hur_cell, netInCell._hur_net[i+self._ind].getName() ) # FIXME plante avec le adder mixed dans un cas particulier indetermine ....
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##### Instanciation of a buffer #####
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def Buffer ( self ) :
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global CELLS
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from st_model import CELLS
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cell = CELLS[-1]
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if not ( cell._st_vdds ) or not ( cell._st_vsss ) :
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err = "\n[Stratus ERROR] : there is no alim.\n"
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raise Exception ( err )
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# Creation of the output net with the right size
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num_net = len ( cell._TAB_NETS_OUT )
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cell._TAB_NETS_OUT += [Signal ( "buf_o%d" % num_net, self._arity )]
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buffMap = { 'q' : cell._TAB_NETS_OUT[num_net]
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, 'vdd' : cell._st_vdds[0]
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, 'vss' : cell._st_vsss[0]
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}
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if self._st_cell._buff == 'DpgenBuff' : buffMap['i0'] = self
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else : buffMap['i'] = self
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# if ( self._st_cell._buff == "Buf" ) and ( self._arity == 1 ) :
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# inst_name = self._st_cell._buff.lower()
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# else :
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inst_name = self._st_cell._buff.lower()
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inst_name = re.sub ( "\.", "_", inst_name )
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inst_name += "_"
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inst_name += str(self._arity)
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Generate ( self._st_cell._buff, inst_name, param = { 'nbit' : self._arity } )
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Inst ( inst_name, map = buffMap )
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return cell._TAB_NETS_OUT[num_net]
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##### Boolean operators #####
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def __and__ ( self, other_net ) : return self.bool ( other_net, self._st_cell._and )
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def __or__ ( self, other_net ) : return self.bool ( other_net, self._st_cell._or )
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def __xor__ ( self, other_net ) : return self.bool ( other_net, self._st_cell._xor )
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def bool ( self, other_net, model ) :
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global CELLS
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from st_model import CELLS
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cell = CELLS[-1]
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if model == self._st_cell._and : f = "&"
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elif model == self._st_cell._or : f = "|"
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elif model == self._st_cell._xor : f = "^"
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if self._arity - other_net._arity :
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err = "\n[Stratus ERROR] " + f + " : the nets " + self._name + " and " + other_net._name + " must have the same lenght.\n"
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raise Exception ( err )
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# Creation of the output net with the right size
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num_net = len ( cell._TAB_NETS_OUT )
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cell._TAB_NETS_OUT += [Signal ( "bool_o%d" % num_net, self._arity )]
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if not ( cell._st_vdds ) or not ( cell._st_vsss ) :
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err = "\n[Stratus ERROR] : there is no alim.\n"
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raise Exception ( err )
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# if ( model in ( "A2", "O2", "Xr2" ) ) and ( self._arity == 1 ) and ( other_net._arity == 1 ) :
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# inst_name = model.lower()
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#
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# else :
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inst_name = model.lower()
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inst_name = re.sub ( "\.", "_", inst_name )
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inst_name += "_"
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inst_name += str(self._arity)
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Generate ( model, inst_name, param = { 'nbit' : self._arity } )
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Inst ( inst_name
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, map = { 'i0' : self
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, 'i1' : other_net
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, 'q' : cell._TAB_NETS_OUT[num_net]
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, 'vdd' : cell._st_vdds[0]
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, 'vss' : cell._st_vsss[0]
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}
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)
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return cell._TAB_NETS_OUT[num_net]
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def __invert__ ( self ) :
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global CELLS
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from st_model import CELLS
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cell = CELLS[-1]
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if not ( cell._st_vdds ) or not ( cell._st_vsss ) :
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err = "\n[Stratus ERROR] : there is no alim.\n"
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raise Exception ( err )
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# Creation of the output net with the right size
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num_net = len ( cell._TAB_NETS_OUT )
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cell._TAB_NETS_OUT += [Signal ( "inv_o%d" % num_net, self._arity )]
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invMap = { 'nq' : cell._TAB_NETS_OUT[num_net]
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, 'vdd' : cell._st_vdds[0]
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, 'vss' : cell._st_vsss[0]
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}
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if self._st_cell._not == 'DpgenInv' : invMap['i0'] = self
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else : invMap['i'] = self
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# if ( self._st_cell._not == "Inv" ) and ( self._arity == 1 ) :
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# inst_name = self._st_cell._not.lower()
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# else :
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inst_name = self._st_cell._not.lower()
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inst_name = re.sub ( "\.", "_", inst_name )
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inst_name += "_"
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inst_name += str(self._arity)
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Generate ( self._st_cell._not, inst_name, param = { 'nbit' : self._arity } )
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Inst ( inst_name, map = invMap )
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return cell._TAB_NETS_OUT[num_net]
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##### Arithmetic operators #####
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def __add__ ( self, other_net ) : return self.arithgen ( other_net, self._st_cell._add, {'signed' : self._st_cell._signed, 'extended' : self._st_cell._extended} )
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def __sub__ ( self, other_net ) : return self.arithgen ( other_net, self._st_cell._sub, {'signed' : self._st_cell._signed, 'extended' : self._st_cell._extended} )
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def __mul__ ( self, other_net ) : return self.arithgen ( other_net, self._st_cell._mult, {'signed' : self._st_cell._signed} )
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def __div__ ( self, other_net ) : return self.arithgen ( other_net, self._st_cell._div )
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def arithgen ( self, other_net, function, parameter = {} ) :
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global CELLS
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from st_model import CELLS
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cell = CELLS[-1]
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if not function :
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err = "\n[Stratus ERROR] / : to be done.\n"
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raise Exception ( err )
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if not ( cell._st_vdds ) or not ( cell._st_vsss ) :
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err = "\n[Stratus ERROR] there is no alim in cell %s.\n" % str(cell._name)
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raise Exception ( err )
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# Creation of the output net with the right size
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num_net = len ( cell._TAB_NETS_OUT )
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if function == self._st_cell._add :
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if self._st_cell._extended :
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cell._TAB_NETS_OUT += [Signal ( "add_o%d" % num_net, max ( self._arity, other_net._arity )+1 )]
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else:
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cell._TAB_NETS_OUT += [Signal ( "add_o%d" % num_net, max ( self._arity, other_net._arity ) )]
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elif function == self._st_cell._sub :
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if self._st_cell._extended :
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cell._TAB_NETS_OUT += [Signal ( "sub_o%d" % num_net, max ( self._arity, other_net._arity )+1 )]
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else:
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cell._TAB_NETS_OUT += [Signal ( "sub_o%d" % num_net, max ( self._arity, other_net._arity ) )]
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elif function == self._st_cell._mult : cell._TAB_NETS_OUT += [Signal ( "mul_o%d" % num_net, self._arity+other_net._arity )]
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arithParam = parameter
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if not self._st_cell._signed and function == self._st_cell._mult :
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name1 = re.sub(r"\[([0-9]+):([0-9]+)\]",r"\1\2", self._name) + "ext"
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name2 = re.sub(r"\[([0-9]+):([0-9]+)\]",r"\1\2", other_net._name) + "ext"
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i0ext = Signal(name1, self._arity+1)
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i1ext = Signal(name2, other_net._arity+1)
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i0ext <= self.Extend(self._arity+1, 'zero')
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i1ext <= other_net.Extend(other_net._arity+1, 'zero')
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arithParam['nbit0'] = self._arity+1
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arithParam['nbit1'] = other_net._arity+1
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arithMap = { 'i0' : i0ext
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, 'i1' : i1ext
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, 'o' : cell._TAB_NETS_OUT[num_net]
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, 'vdd' : cell._st_vdds[0]
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, 'vss' : cell._st_vsss[0]
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}
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else:
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arithParam['nbit0'] = self._arity
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arithParam['nbit1'] = other_net._arity
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arithMap = { 'i0' : self
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, 'i1' : other_net
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, 'o' : cell._TAB_NETS_OUT[num_net]
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, 'vdd' : cell._st_vdds[0]
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, 'vss' : cell._st_vsss[0]
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}
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inst_name = function.lower()
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inst_name = re.sub ( "\.", "_", inst_name )
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for p in arithParam : inst_name += "_%s_%s" % ( str(p).lower(), str(arithParam[p]).lower() )
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Generate ( function, inst_name, param = arithParam )
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Inst ( inst_name, map = arithMap )
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return cell._TAB_NETS_OUT[num_net]
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##### Shifter #####
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def Shift ( self, inputNet, direction, type ) :
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global CELLS
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from st_model import CELLS
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cell = CELLS[-1]
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if not inputNet._arity : raise Exception ( "\n[Stratus ERROR] Shift : The input net does not have a positive arity.\n" )
|
|
if not self._arity : raise Exception ( "\n[Stratus ERROR] Shift : The command net does not have a positive arity.\n" )
|
|
if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise Exception ( "\n[Stratus ERROR] there is no alim.\n" )
|
|
# Wrong parameters :
|
|
if direction not in ( "left", "right" ) : raise Exception ( "\n[Stratus ERROR] Shift : The direction parameter must be \"left\" or \"right\".\n" )
|
|
if type not in ( "logical", "arith", "circular" ) : raise Exception ( "\n[Stratus ERROR] Shift : The type parameter must be \"logical\" or \"arith\" or \"circular\".\n" )
|
|
|
|
# Creation of the output net with the right size
|
|
num_net = len ( cell._TAB_NETS_OUT )
|
|
cell._TAB_NETS_OUT += [Signal ( "sh_o%d" % num_net, inputNet._arity )]
|
|
|
|
# Initialisation of shiftType
|
|
if direction is "left" :
|
|
if type is "logical" : shiftType = 0x12
|
|
elif type is "arith" : shiftType = 0xa
|
|
else : shiftType = 0x6
|
|
else :
|
|
if type is "logical" : shiftType = 0x11
|
|
elif type is "arith" : shiftType = 0x9
|
|
else : shiftType = 0x5
|
|
|
|
inst_name = self._st_cell._shift.lower()
|
|
inst_name = re.sub ( "\.", "_", inst_name )
|
|
inst_name += "_"
|
|
inst_name += type
|
|
inst_name += "_"
|
|
inst_name += str(inputNet._arity)
|
|
|
|
Generate ( self._st_cell._shift, inst_name, param = { 'nbit' : inputNet._arity, 'type' : shiftType } )
|
|
Inst ( inst_name
|
|
, map = { 'cmd' : self
|
|
, 'i' : inputNet
|
|
, 's' : cell._TAB_NETS_OUT[num_net]
|
|
, 'vdd' : cell._st_vdds[0]
|
|
, 'vss' : cell._st_vsss[0]
|
|
}
|
|
)
|
|
|
|
return cell._TAB_NETS_OUT[num_net]
|
|
|
|
##### Register #####
|
|
def Reg ( self, inputNet ) :
|
|
global CELLS
|
|
from st_model import CELLS
|
|
|
|
cell = CELLS[-1]
|
|
|
|
if not inputNet._arity : raise Exception ( "\n[Stratus ERROR] Reg : The input net does not have a positive arity.\n" )
|
|
if not self._arity : raise Exception ( "\n[Stratus ERROR] Reg : The clock does not have a positive arity.\n" )
|
|
if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise Exception ( "\n[Stratus ERROR] there is no alim.\n" )
|
|
|
|
# Creation of the output net with the right size
|
|
num_net = len ( cell._TAB_NETS_OUT )
|
|
cell._TAB_NETS_OUT += [Signal ( "reg_o%d" % num_net, inputNet._arity )]
|
|
|
|
# if ( self._st_cell._reg == "Sff1" ) and ( inputNet._arity == 1 ) :
|
|
# inst_name = "sff1"
|
|
# else :
|
|
# inst_name = self._st_cell._reg.lower()
|
|
# inst_name = re.sub ( "\.", "_", inst_name )
|
|
# inst_name += "_"
|
|
# inst_name += str(inputNet._arity)
|
|
#
|
|
# Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } )
|
|
|
|
inst_name = self._st_cell._reg.lower()
|
|
inst_name = re.sub ( "\.", "_", inst_name )
|
|
inst_name += "_"
|
|
inst_name += str(inputNet._arity)
|
|
|
|
Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } )
|
|
|
|
Inst ( inst_name
|
|
, map = { 'i' : inputNet
|
|
, 'ck' : self
|
|
, 'q' : cell._TAB_NETS_OUT[num_net]
|
|
, 'vdd' : cell._st_vdds[0]
|
|
, 'vss' : cell._st_vsss[0]
|
|
}
|
|
)
|
|
|
|
return cell._TAB_NETS_OUT[num_net]
|
|
|
|
##### Multiplexor #####
|
|
def Mux ( self, nets ) :
|
|
|
|
maxPossibility = pow ( 2, self._arity ) - 1
|
|
|
|
### List ###
|
|
if type ( nets ) == types.ListType :
|
|
if len ( nets ) != ( maxPossibility + 1 ) :
|
|
raise Exception ( "\n[Stratus ERROR] Mux : when using a list, all the nets must be precised. Maybe one should use a dictionnary.\n" )
|
|
|
|
return self.muxList ( nets )
|
|
|
|
### Dictionnary : Creation of the corresponding list ###
|
|
elif type ( nets ) == types.DictType :
|
|
|
|
# Initialisation of the by default to 0 net if no default net given
|
|
if "default" not in nets : nets["default"] = 0
|
|
|
|
# Traitement of lists, intervals and numbers
|
|
for net in nets.keys () :
|
|
if re.search ( "-", net ) or re.search ( ",", net ) or re.search ( "#", net ) :
|
|
chaine = net
|
|
while chaine :
|
|
interval = re.search ( "^([0-9]+)-([0-9]+)", chaine )
|
|
chiffre = re.search ( "^([0-9]+)", chaine )
|
|
diese = re.search ( "^#([0-9\?]+)", chaine )
|
|
|
|
#############
|
|
if interval :
|
|
nb1 = int ( interval.group(1) )
|
|
nb2 = int ( interval.group(2) )
|
|
|
|
# Error : wrong interval
|
|
if nb1 >= nb2 :
|
|
raise Exception ( "\n[Stratus ERROR] Mux : when an interval is specified, the second number of the interval must be the greater one.\n" )
|
|
# Error : if the interval does not correspond to the lenght of the command
|
|
if ( nb1 > maxPossibility ) or ( nb2 > maxPossibility ) :
|
|
raise Exception ( "\n[Stratus ERROR] Mux : One key does not match with the arity of the input nets.\n" )
|
|
|
|
for i in range ( nb1, nb2+1 ) : nets[i] = nets[net]
|
|
|
|
# Next element
|
|
temp = re.search ( "^[0-9]+-[0-9]+,(.+)$", chaine )
|
|
if temp : chaine = str ( temp.group(1) )
|
|
else : chaine = None
|
|
|
|
##############
|
|
elif chiffre :
|
|
if int ( chiffre.group(0) ) > maxPossibility :
|
|
raise Exception ( "\n[Stratus ERROR] Mux : One key does not match with the arity of the input nets.\n" )
|
|
|
|
nets[int(chiffre.group(0))] = nets[net]
|
|
|
|
# Next element
|
|
temp = re.search ( "^[0-9]+,(.+)$", chaine )
|
|
if temp : chaine = str ( temp.group(1) )
|
|
else : chaine = None
|
|
|
|
############
|
|
elif diese :
|
|
binaire = diese.group ( 1 )
|
|
|
|
# Error : if the binary number does not correspond to the lenght of the command
|
|
if len ( binaire ) != self._arity :
|
|
err = "\n[Stratus ERROR] Mux : the binary number " + str(binaire) \
|
|
+ " does not match with the lenght of the command. It has to be a " + str(self._arity) + "bits number.\n"
|
|
raise Exception ( err )
|
|
|
|
# Error : if the number is not binary
|
|
for n in binaire :
|
|
if n not in ( "0", "1", "?", "#" ) :
|
|
err = "\n[Stratus ERROR] Mux : after #, the number has to be binary.\n"
|
|
raise Exception ( err )
|
|
|
|
nombrebit = self._arity
|
|
|
|
nb = 0
|
|
for i in range ( -1, -nombrebit - 1, -1 ) :
|
|
if binaire[i] == "1" : nb += pow ( 2, -i - 1 )
|
|
|
|
nombres = []
|
|
premierpassage = 1
|
|
for i in range ( -1, -nombrebit - 1, -1 ) :
|
|
if binaire[i] == "?" :
|
|
if premierpassage :
|
|
nombres += [nb]
|
|
nombres += [nb + pow ( 2, -i - 1 )]
|
|
premierpassage = 0
|
|
else :
|
|
enplus = []
|
|
for chaquenombre in nombres : enplus += [chaquenombre + pow ( 2, -i - 1 )]
|
|
nombres += enplus
|
|
|
|
for chaquenombre in nombres : nets[chaquenombre] = nets[net]
|
|
|
|
# Next element
|
|
temp = re.search ( "^#.*,(.+)$", chaine )
|
|
if temp : chaine = str ( temp.group (1) )
|
|
else : chaine = None
|
|
|
|
else :
|
|
err = "\n[Stratus ERROR] Mux : wrong key.\n"
|
|
raise Exception ( err )
|
|
|
|
del nets[net]
|
|
|
|
# Otherwise it must be a number :
|
|
elif re.search ( "^[0-9]+$", net ) :
|
|
chaine = re.search ( "^([0-9]+)$", net )
|
|
chiffre = str ( chaine.group ( 1 ) )
|
|
|
|
if int ( chiffre ) > maxPossibility :
|
|
err = "\n[Stratus ERROR] Mux : One key does not match with the arity of the input nets.\n"
|
|
raise Exception ( err )
|
|
|
|
nets[int(chiffre)] = nets[chiffre]
|
|
del nets[chiffre]
|
|
|
|
else :
|
|
if net != "default" :
|
|
err = "\n[Stratus ERROR] Mux : wrong key.\n"
|
|
raise Exception ( err )
|
|
|
|
clefs = nets.keys ()
|
|
clefs.sort ()
|
|
|
|
# Covering of the keys wich are not default
|
|
lenClefs = 0
|
|
for c in clefs :
|
|
if c != "default" : lenClefs += 1
|
|
|
|
liste = []
|
|
decalage = 0
|
|
for i in range ( lenClefs ) :
|
|
nb = clefs[i]
|
|
nb2 = i + decalage
|
|
if nb2 < nb :
|
|
while nb2 < nb :
|
|
liste.append ( nets["default"] )
|
|
nb2 += 1
|
|
decalage += 1
|
|
liste.append ( nets[clefs[i]] ) # it is the right one
|
|
else :
|
|
liste.append ( nets[clefs[i]] )
|
|
|
|
# Number of wanted nets :
|
|
lenList = pow ( 2, self._arity )
|
|
|
|
# If nets are missing theu are default nets
|
|
while len ( liste ) < lenList : liste.append ( nets["default"] )
|
|
|
|
# Creation of the list corresponding to the dictionnary
|
|
return self.muxList ( liste )
|
|
|
|
# Error : wrong argument
|
|
else :
|
|
err = "\n[Stratus ERROR] Mux : wrong argument type.\n"
|
|
raise Exception ( err )
|
|
|
|
|
|
### List ###
|
|
def muxList ( self, nets ) :
|
|
global CELLS
|
|
from st_model import CELLS
|
|
|
|
cell = CELLS[-1]
|
|
|
|
if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise Exception ( "\n[Stratus ERROR] : there is no alim.\n" )
|
|
|
|
long = 0
|
|
for i in range ( len ( nets ) ) :
|
|
if nets[i] : long = nets[i]._arity
|
|
|
|
# Error : if no input net
|
|
if not ( long ) : raise Exception ( "\n[Stratus ERROR] Mux : there are no input nets.\n" )
|
|
|
|
# Instanciation of a zero cell if needed
|
|
for net in nets :
|
|
if net == 0 :
|
|
from st_const import Zero
|
|
num_net = len ( cell._TAB_NETS_OUT )
|
|
cell._TAB_NETS_OUT += [Signal ( "sig0_%d" % num_net, long )]
|
|
cell._TAB_NETS_OUT[num_net] <= Zero ( long )
|
|
break
|
|
|
|
# Creation of the map
|
|
map_mux = { 'cmd' : self
|
|
, 'vdd' : cell._st_vdds[0]
|
|
, 'vss' : cell._st_vsss[0]
|
|
}
|
|
|
|
i = 0
|
|
for net in nets :
|
|
if net : map_mux['i%d' % i] = net
|
|
else : map_mux['i%d' % i] = cell._TAB_NETS_OUT[num_net]
|
|
|
|
i += 1
|
|
|
|
# Initialisation of the output net
|
|
num_net = len ( cell._TAB_NETS_OUT )
|
|
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, long )]
|
|
|
|
map_mux ['q'] = cell._TAB_NETS_OUT[num_net]
|
|
|
|
inst_name = self._st_cell._mux.lower()
|
|
inst_name = re.sub ( "\.", "_", inst_name )
|
|
inst_name += "_"
|
|
inst_name += str(long)
|
|
inst_name += "_"
|
|
inst_name += str(self._arity)
|
|
|
|
Generate ( self._st_cell._mux, inst_name, param = { 'nbit' : long, 'nbit_cmd' : self._arity } )
|
|
Inst ( inst_name, map = map_mux )
|
|
|
|
return cell._TAB_NETS_OUT[num_net]
|
|
|
|
|
|
##### Comparison functions #####
|
|
def Eq ( self, nb ) : return self.comparaison ( nb, True )
|
|
def Ne ( self, nb ) : return self.comparaison ( nb, False )
|
|
|
|
# TODO : it could work with un string representing binary, decimal, or hexadecimal
|
|
def comparaison ( self, nb, egal ) :
|
|
global CELLS
|
|
from st_model import CELLS
|
|
|
|
cell = CELLS[-1]
|
|
|
|
if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise Exception ( "\n[Stratus ERROR] : threre is no alim.\n" )
|
|
|
|
# Initialisation of the output net
|
|
num_net = len ( cell._TAB_NETS_OUT )
|
|
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, 1 )]
|
|
|
|
inst_name = self._st_cell._comp.lower()
|
|
inst_name = re.sub ( "\.", "_", inst_name )
|
|
inst_name += "_"
|
|
inst_name += str(self._arity)
|
|
inst_name += "_"
|
|
inst_name += str(nb)
|
|
if egal : inst_name += "eq"
|
|
|
|
Generate ( self._st_cell._comp, inst_name, param = { 'nbit' : self._arity, 'nb' : nb, 'egal' : egal } )
|
|
Inst ( inst_name
|
|
, map = { "netin" : self
|
|
, "netout" : cell._TAB_NETS_OUT[num_net]
|
|
, 'vdd' : cell._st_vdds[0]
|
|
, 'vss' : cell._st_vsss[0]
|
|
}
|
|
)
|
|
|
|
return cell._TAB_NETS_OUT[num_net]
|
|
|
|
|
|
##### Method Alias #####
|
|
def Alias ( self, net ) :
|
|
|
|
# Error : if the net already has an alias
|
|
if net._alias :
|
|
err = "\n[Stratus ERROR] Alias : the net " + net._name + " is already an alias.\n"
|
|
raise Exception ( err )
|
|
|
|
# Resizement of the net if needed
|
|
if not ( net._arity ) : net.create_net ( net._name, self._arity )
|
|
|
|
# Error : if the nets don't have the same lenght
|
|
if self._arity != net._arity :
|
|
err = "\n[Stratus ERROR] Alias : the nets " + self._name + " and " + net._name + " must have the same lenght\n"
|
|
raise Exception ( err )
|
|
|
|
# If nets are virtual, let's work with the corresponding real nets
|
|
if net._real_net : realNet = net._real_net
|
|
else : realNet = net
|
|
|
|
if self._real_net : realSelf = self._real_net
|
|
else : realSelf = self
|
|
|
|
# Construction of the tab if needed
|
|
if not ( len ( realNet._alias ) ) :
|
|
for i in range ( realNet._arity ) : realNet._alias.append ( 0 )
|
|
|
|
# Initialisation of _alias
|
|
for i in range ( net._ind, net._ind + net._arity ) :
|
|
|
|
if not realSelf._alias :
|
|
realNet._alias[i] = {realSelf : i + self._ind - net._ind}
|
|
# Alias of an alias
|
|
else :
|
|
err = "\n[Stratus ERROR] Alias : 2 Alias in a row are not supported.\n"
|
|
raise Exception ( err )
|
|
# FIXME bug : for now, Alias of Alias are not permitted
|
|
# if realSelf._alias[i + self._ind - net._ind] :
|
|
# netAlias = realSelf._alias[i + self._ind - net._ind].keys()[0]
|
|
# bitAlias = realSelf._alias[i + self._ind - net._ind][netAlias]
|
|
# if netAlias._real_net : netAlias = netAlias._real_net
|
|
# realNet._alias[i] = {netAlias : bitAlias}
|
|
# # Error : more than 2 Alias in a row not supported
|
|
# if netAlias._alias :
|
|
# err = "\n[Stratus ERROR] Alias : more than 2 Alias in a row are not supported.\n"
|
|
# raise err
|
|
# else :
|
|
# realNet._alias[i] = {realSelf : i + self._ind - net._ind}
|
|
|
|
##### Method Extend #####
|
|
def Extend ( self, width, type ) :
|
|
global CELLS
|
|
|
|
from st_model import CELLS
|
|
from st_const import Zero, One
|
|
|
|
cell = CELLS[-1]
|
|
|
|
if self._arity >= width :
|
|
err = "\n[Stratus ERROR] Extend : the net " + self._name + \
|
|
" can not be extended to " + str(width) + " bits, it's arity is already " + str(self._arity) + ".\n"
|
|
raise Exception ( err )
|
|
|
|
num_net = len ( cell._TAB_NETS_OUT )
|
|
cell._TAB_NETS_OUT += [Signal ( "%s_ext_%d_%d" % ( self._name, width, num_net ), width )]
|
|
|
|
name = "extend_%d_%d_%s" % ( self._arity, width, type )
|
|
|
|
Generate ( "Extend", name, param = { 'nbit0' : self._arity, 'nbit1' : width, 'type' : type } )
|
|
|
|
Inst ( name
|
|
, map = { 'i' : self
|
|
, 'o' : cell._TAB_NETS_OUT[num_net]
|
|
, 'vdd' : cell._st_vdds[0]
|
|
, 'vss' : cell._st_vsss[0]
|
|
}
|
|
)
|
|
|
|
return cell._TAB_NETS_OUT[num_net]
|
|
|
|
##################################################################################################################################
|
|
##### Initialisation of nets #####
|
|
def create_net ( self, nom, nbit, indice = 0, extern = False, direction = None, hType = None ) :
|
|
global CELLS
|
|
from st_model import CELLS
|
|
|
|
cell = CELLS[-1]
|
|
|
|
# Error :
|
|
if re.search ( "[A-Z]", nom ) :
|
|
print "[Stratus Warning] : Upper case letters are not supported, the name", nom, "is lowered."
|
|
nom = nom.lower ()
|
|
if re.search ( " ", nom ) :
|
|
chaine = re.search ( "st_net\.(.*)", str ( self.__class__ ) )
|
|
classe = chaine.group(1)
|
|
err = "\n[Stratus ERROR] " + classe + " : \"" + nom + "\" the name of the net can not contain a space.\n"
|
|
raise Exception ( err )
|
|
|
|
self._st_cell = cell
|
|
self._name = nom
|
|
self._arity = nbit
|
|
self._ind = indice
|
|
self._hur_net = []
|
|
self._alias = []
|
|
self._to_merge = []
|
|
self._to_cat = []
|
|
self._real_net = None
|
|
self._ext = extern
|
|
self._h_type = hType
|
|
if extern : self._direct = direction
|
|
|
|
# Error :
|
|
if ( nbit == 1 ) and indice :
|
|
err = "\n[Stratus ERROR] " + str ( self.__class__ ) + " : " + self._name + " : one can not put an indice for a 1 bit net.\n"
|
|
raise Exception ( err )
|
|
|
|
if hType :
|
|
if hType == "POWER" : self._st_cell._st_vdds.append ( self )
|
|
elif hType == "GROUND" : self._st_cell._st_vsss.append ( self )
|
|
elif hType == "CLOCK" : self._st_cell._st_cks.append ( self )
|
|
|
|
# The net is put in the nets list of the cell
|
|
else :
|
|
if nbit :
|
|
if extern : self._st_cell._st_ports.append ( self )
|
|
else : self._st_cell._st_sigs.append ( self )
|
|
|
|
# Creation of the hurricane net if in hurricane mode
|
|
if self._st_cell._hur_cell : self.create_hur_net()
|
|
|
|
##### Initialisation of the hurricane nets for part nets #####
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def create_part_hur_net ( self ) :
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if self._ind2 < self._ind : pas = -1
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else : pas = 1
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if self._real_net._hur_net : # FIXME a priori pb du a l outil d optimisation
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for i in range ( self._ind, self._ind2 + pas, pas ) : self._hur_net.append ( self._real_net._hur_net[i] )
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##### Initialisation of the hurricane nets #####
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def create_hur_net ( self ) :
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if self._arity == 1 :
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self.hur_net ( self._name, 0 )
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else :
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#for i in range ( self._ind+self._arity, self._ind, -1 ):
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for i in range ( self._ind, self._ind+self._arity, 1 ):
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#print 'create %s(%d)' % (self._name,i)
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self.hur_net ( '%s(%d)' % (self._name,i), i )
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##### hur_net one by one #####
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def hur_net ( self, name, ind ) :
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if ( self._alias ) and ( self._alias[ind] ) :
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self._hur_net += [self._alias[ind].keys()[0]] # put the right hur_net
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return
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elif ( self._to_cat ) and ( self._to_cat[ind] ) :
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cat = self._to_cat[ind]
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self._hur_net += [cat[0]._hur_net[cat[1]]]
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return
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net = Net.create ( self._st_cell._hur_cell, name )
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net.setType ( Net.Type.LOGICAL )
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if self._ext : net.setExternal ( True )
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else : net.setExternal ( False )
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if self._ext :
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if self._direct == "IN" : net.setDirection ( Net.Direction.IN )
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elif self._direct == "OUT" : net.setDirection ( Net.Direction.OUT )
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elif self._direct == "INOUT" : net.setDirection ( Net.Direction.INOUT )
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elif self._direct == "TRISTATE" : net.setDirection ( Net.Direction.TRISTATE )
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elif self._direct == "UNKNOWN" : net.setDirection ( Net.Direction.UNDEFINED )
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if '_h_type' in self.__dict__ :
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if self._h_type == "POWER" : net.setType ( Net.Type.POWER ); net.setGlobal( True )
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elif self._h_type == "GROUND" : net.setType ( Net.Type.GROUND ); net.setGlobal( True )
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elif self._h_type == "CLOCK" : net.setType ( Net.Type.CLOCK ); net.setGlobal( True )
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self._hur_net += [net]
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##### Hurricane merge #####
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def hur_merge ( self ) :
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if self._real_net : realNet = self._real_net
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else : realNet = self
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if self._to_cat :
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err = "\n[Stratus ERROR] HurricanePlug <= : net " + self._name + " is a Cat net. Forbidden utilisation of <= and Cat.\n"
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raise Exception ( err )
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for i in range ( self._ind, self._arity + self._ind ) :
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if realNet._to_merge[i] :
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selfToMerge = realNet._to_merge[i][0]
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bitToMerge = realNet._to_merge[i][1]
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if selfToMerge._hur_net == [] :
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print "[Stratus Warning] HurricanePlug <= : net", selfToMerge._name, "has no hurricane net."
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return
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if realNet._hur_net == [] :
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err = "\n[Stratus ERROR] HurricanePlug <= : net " + realNet._name + " has no hurricane net.\n"
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raise Exception ( err )
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if bitToMerge > ( len ( selfToMerge._hur_net ) - 1 ) :
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err = "\n[Stratus ERROR] HurricanePlug <= : net " + selfToMerge._name + " with hur_net : " + str(selfToMerge._hur_net) \
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+ " with asked bit : " + str(bitToMerge) + ".\n"
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raise Exception ( err )
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if i > ( len ( realNet._hur_net ) - 1 ) :
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err = "\n[Stratus ERROR] HurricanePlug <= : net " + realNet._name + " with hur_net : " + str(realNet._hur_net) \
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+ " with asked bit : " + str(i) + ".\n"
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raise Exception ( err )
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selfToMerge._hur_net[bitToMerge].merge ( realNet._hur_net[i] )
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# realNet._hur_net[i] = 0
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# realNet.Delete()
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# del realNet
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##### Initialisation from a net hurricane #####
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def create_from_hur ( self, hur_net ) :
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global CELLS
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from st_model import CELLS
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cell = CELLS[-1]
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self._st_cell = cell
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self._alias = []
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self._to_merge = []
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self._to_cat = []
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self._real_net = None
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self._arity = 1
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self._ind = 0
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self._name = str ( hur_net.getName() )
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if hur_net.isExternal() : self._ext = True
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else : self._ext = False
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if hur_net.isExternal() :
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if hur_net.getDirection() == Net.Direction.IN : self._direct = "IN"
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elif hur_net.getDirection() == Net.Direction.OUT : self._direct = "OUT"
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elif hur_net.getDirection() == Net.Direction.INOUT : self._direct = "INOUT"
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elif hur_net.getDirection() == Net.Direction.TRISTATE : self._direct = "TRISTATE"
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elif hur_net.getDirection() == Net.Direction.UNDEFINED : self._direct = "UNDEFINED"
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if hur_net.getType() == Net.Type.POWER : self._h_type = "POWER"
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elif hur_net.getType() == Net.Type.GROUND : self._h_type = "GROUND"
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elif hur_net.getType() == Net.Type.CLOCK : self._h_type = "CLOCK"
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self._hur_net = [hur_net]
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if ( self._ext ) and ( '_h_type' in self.__dict__ ) :
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if self._h_type == "CLOCK" : cell._st_ports.append ( self ) # not alimentations
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else :
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cell._st_sigs.append ( self )
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###########
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# SignalIn #
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###########
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class SignalIn ( net ) :
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def __init__ ( self, nom, nbit, indice = 0 ) :
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if nbit < 1 : raise Exception ( "\n[Stratus ERROR] SignalIn : the lenght of the net must be a positive value\n" )
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self.create_net ( nom, nbit, indice, True, "IN" )
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class SignalInFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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############
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# SignalOut #
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############
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class SignalOut ( net ) :
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def __init__ ( self, nom, nbit, indice = 0 ) :
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if nbit < 1 : raise Exception ( "\n[Stratus ERROR] SignalOut : the lenght of the net must be a positive value\n" )
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self.create_net ( nom, nbit, indice, True, "OUT" )
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class SignalOutFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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##############
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# SignalInOut #
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##############
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class SignalInOut ( net ) :
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def __init__ ( self, nom, nbit, indice = 0 ) :
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if nbit < 1 : raise Exception ( "\n[Stratus ERROR] SignalInOut : the lenght of the net must be a positive value\n" )
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self.create_net ( nom, nbit, indice, True, "INOUT" )
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class SignalInOutFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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################
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# SignalUnknown #
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################
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class SignalUnknown ( net ) :
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def __init__ ( self, nom, nbit, indice = 0 ) :
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if nbit < 1 : raise Exception ( "\n[Stratus ERROR] SignalUnknown : the lenght of the net must be a positive value\n" )
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self.create_net ( nom, nbit, indice, True, "UNKNOWN" )
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class SignalUnknownFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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############
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# TriState #
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############
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class TriState ( net ) :
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def __init__ ( self, nom, nbit, indice = 0 ) :
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if nbit < 1 : raise Exception ( "\n[Stratus ERROR] TriState : the lenght of the net must be a positive value\n" )
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self.create_net ( nom, nbit, indice, True, "TRISTATE" )
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class SignalTriStateFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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#########
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# Clock #
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#########
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class CkIn ( net ) :
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def __init__ ( self, nom ) :
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self.create_net ( nom, 1, extern = True, direction = "IN", hType = "CLOCK" )
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class CkInFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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#########################
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# Internal Clock Signal #
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#########################
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class SignalCk ( net ) :
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def __init__ ( self, nom ) :
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self.create_net ( nom, 1, direction = "IN", hType = "CLOCK" )
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class SignalCkFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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###################
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# Internal Signal #
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###################
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class Signal ( net ) :
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def __init__ ( self, nom, nbit = 0, indice = 0 ) :
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if nbit < 0 : raise Exception ( "\n[Stratus ERROR] Signal : the lenght of the net must be a positive value\n" )
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self.create_net ( nom, nbit, indice )
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class SignalFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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################
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# Alimentation #
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################
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class VddIn ( net ) :
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def __init__ ( self, nom ) : self.create_net ( nom, 1, extern = True, direction = "IN", hType = "POWER" )
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class VssIn ( net ) :
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def __init__ ( self, nom ) : self.create_net ( nom, 1, extern = True, direction = "IN", hType = "GROUND" )
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class VddInFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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class VssInFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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class SignalVdd ( net ) :
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def __init__ ( self, nom ) : self.create_net ( nom, 1, direction = "IN", hType = "POWER" )
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class SignalVss ( net ) :
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def __init__ ( self, nom ) : self.create_net ( nom, 1, direction = "IN", hType = "GROUND" )
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class SignalVddFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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class SignalVssFromHur ( net ) :
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def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
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##################
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# Virtual signal #
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##################
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class Sig ( net ) :
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def __init__ ( self, net, indiceFort, indiceFaible = -1 ) :
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global CELLS
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from st_model import CELLS
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if indiceFaible == -1 : indiceFaible = indiceFort
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self._st_cell = CELLS[-1]
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self._ind = indiceFaible
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self._ind2 = indiceFort
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self._alias = []
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self._to_merge = []
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self._to_cat = []
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self._real_net = net
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self._ext = net._ext
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self._arity = abs ( indiceFort - indiceFaible ) + 1
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if indiceFort < indiceFaible : self._reverse = True
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else : self._reverse = False
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self._hur_net = []
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self._st_cell._st_partsigs.append ( self )
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# Initialisation of _hur_net if in hurricanePlug mode
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# if CELLS[0]._hur_plug : self.create_part_hur_net()
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if self._ext : self._direct = net._direct
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if '_h_type' in net.__dict__ : self._h_type = net._h_type
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if indiceFort == indiceFaible : self._name = net._name + "[" + str(indiceFaible) + "]"
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else : self._name = net._name + "[" + str(indiceFort) + ":" + str(indiceFaible) + "]"
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