1351 lines
44 KiB
Python
1351 lines
44 KiB
Python
#!/usr/bin/python
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#
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# This file is part of the Coriolis Software.
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# Copyright (c) UPMC/LIP6 2008-2012, All Rights Reserved
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#
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# +-----------------------------------------------------------------+
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./st_model.py" |
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# +-----------------------------------------------------------------+
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import re
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import types
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import string
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import Cfg
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import CRL
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import Viewer
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from Hurricane import *
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FRAMEWORK = None
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EDITOR = None
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MODELMAP = {}
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CELLS = []
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STRATUS = 100
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LOGICAL = CRL.Catalog.State.Logical
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PHYSICAL = CRL.Catalog.State.Physical
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VIEWS = CRL.Catalog.State.Views
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def setEditor ( editor ):
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global EDITOR
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EDITOR = editor
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return
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#######################
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##### Class Model #####
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#######################
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class Model() :
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##########################
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##### Initialisation #####
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##########################
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def __init__ ( self, nom, param = {}, hurCell = None, hurricane_plug = True ) :
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global FRAMEWORK, CELLS
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# Look up the editor
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if globals().has_key ( "__editor" ) : setEditor ( __editor )
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self._name = nom
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self._param = param
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self.pat = None
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self._hur_cell = hurCell
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self._st_insts = [] # Tab : list of the instances
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self._st_ports = [] # Tab : list of the nets
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self._st_sigs = [] # Tab : list of the nets
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self._st_partsigs = [] # Tab : list of the partial nets
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self._st_merge = [] # Tab : list of the nets to merge, in order to have them in the right order
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self._hierarchy = 0 # Modified in ModelCreation
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self._TAB_NETS_OUT = []
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self._TAB_NETS_CAT = []
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self._NB_INST = 0
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# List of the generators used for overload
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self._and = 'A2'
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self._or = 'O2'
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self._xor = 'Xr2'
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self._not = 'Inv'
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self._buff = 'Buf'
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self._reg = 'Sff1'
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# Stratus generators
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self._mux = 'Smux'
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self._shift = 'Shifter'
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self._comp = 'Comp'
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# Arithmetic generators
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self._add = 'Slansky'
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self._sub = 'Sub'
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self._mult = 'Multiplier'
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self._div = None
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self._signed = True
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self._extended = False
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self._model_map = {}
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# List of the under-cells of a cell
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self._underCells = {}
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# self._tabPlacement = []
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# Instance reference for placement
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self._insref = None
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# Place and Route
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self._nb_alims_verticales = 0
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self._nb_pins = 0 # to number the pins of the core
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self._nb_vdd_pins = 0 # to number the pins vdd of the core
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self._nb_vss_pins = 0 # to number the pins vss of the core
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self.standard_instances_list = []
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self.pad_north = [] # list to save the pads names
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self.pad_south = []
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self.pad_east = []
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self.pad_west = []
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# Creation of the database
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if not FRAMEWORK :
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#Initialize()
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FRAMEWORK = CRL.AllianceFramework.get()
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self._st_vdds = []
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self._st_vsss = []
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if hurCell :
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from st_net import VddInFromHur
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from st_net import VssInFromHur
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try:
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netVdd = iter(hurCell.getPowerNets()).next()
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self._st_vdds.append ( VddInFromHur ( netVdd ) )
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except StopIteration:
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print "[Stratus Warning] : Cell", self._name, "does not have a vdd port."
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pass
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try:
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netVss = iter(hurCell.getGroundNets()).next()
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self._st_vsss.append ( VssInFromHur ( netVss ) )
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except StopIteration:
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print "[Stratus Warning] : Cell", self._name, "does not have a vss port."
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pass
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self._st_cks = []
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if not hurCell :
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# List of the cells
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CELLS.append ( self )
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# List of the undercells
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if CELLS[0] != self :
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CELLS[0]._underCells[self] = 0
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# CELLS[0]._tabPlacement.append ( self )
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self._hur_plug = hurricane_plug
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# HurricanePLug if : no hurCell, in mode hurricane plug (i.e. hurricane_plug and hurricane_plug of the masterCell)
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if ( not hurCell ) and ( hurricane_plug ) :
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if CELLS[0] == self :
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self.HurricanePlug()
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else :
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if CELLS[0]._hur_plug :
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self.HurricanePlug()
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##### Delete #####
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def Delete ( self ) :
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UpdateSession.open()
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under_cells = self._underCells
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self._hur_cell.Delete()
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for cell in under_cells : cell._hur_cell.Delete()
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UpdateSession.close()
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#####################################################
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##### Initialisation of attributes for the cell #####
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#####################################################
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def InitGraph ( self ) :
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self._graph = True
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# External nets
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for net in self._st_ports :
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net._st_inst_in = None
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net._st_insts_out = []
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net._covered = False
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# Internal nets
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for net in self._st_sigs :
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net._st_inst_in = None
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net._st_insts_out = []
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net._covered = False
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# Part nets
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for pnet in self._st_partsigs :
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pnet._st_inst_in = None
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pnet._st_insts_out = []
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pnet._covered = False
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# Instances
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for inst in self._st_insts :
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inst._st_nets_in = []
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inst._st_nets_out = []
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# Initialisation of instances and nets
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self.initNet ( inst )
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self.initInst ( inst )
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########################################################
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##### Initialisation of the attributes of the nets #####
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########################################################
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def initNet ( self, instance ) :
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# For each pin
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for pin in instance._map :
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# Check if the pin is an output or an input
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direct = ""
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direct = self.getDirect ( instance._model, pin )
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# Get the net connected to this pin
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if instance._map[pin]._to_merge : mapNet = instance._map[pin]._to_merge[0][0]
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else : mapNet = instance._map[pin]
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if len ( instance._map[pin]._to_merge ) > mapNet._arity :
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mapNet._real_arity = len ( instance._map[pin]._to_merge )
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mapNet._inverse_merge = instance._map[pin]
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# Initialisation
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if direct == 'input' :
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if mapNet._real_net :
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mapNet = mapNet._real_net
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if '_st_insts_out' not in mapNet.__dict__ : mapNet._st_insts_out = []
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if instance not in mapNet._st_insts_out : mapNet._st_insts_out += [instance]
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elif direct == 'output' : # FIXME _real_net not taken care of
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mapNet._st_inst_in = instance
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#############################################################
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##### Initialisation of the attributes of the instances #####
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#############################################################
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def initInst ( self, instance ) :
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# For each pin
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for pin in instance._map :
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# Check if the pin is an output or an input
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direct = ""
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direct = self.getDirect ( instance._model, pin )
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# Get the net connected to this pin
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if instance._map[pin]._to_merge : mapNet = instance._map[pin]._to_merge[0][0]
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else : mapNet = instance._map[pin]
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# Initialisation
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if direct == 'input' : instance._st_nets_in += [mapNet]
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elif direct == 'output' : instance._st_nets_out += [mapNet]
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###########################################
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##### Returns the direction of a port #####
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###########################################
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def getDirect ( self, model, pin ) :
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global FRAMEWORK
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hurCell = FRAMEWORK.getCell ( model, CRL.Catalog.State.Views )
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stCell = None
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if not hurCell :
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for c in self._underCells :
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if c._name == model :
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stCell = c
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break
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if not hurCell and not stCell :
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err = "\nError : no cell found with model %s.\n" % model
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raise Exception ( err )
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# Hurricane cell found:
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if hurCell :
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found = False
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for net in hurCell.getExternalNets():
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direction = net.getDirection()
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name = str(net.getName())
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if net.getType() in ( Net.Type.POWER, Net.Type.GROUND, Net.Type.CLOCK ) :
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found = True
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continue
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chaine = re.search ( "(.*)\([0-9]+\)", name )
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if chaine : name = chaine.group(1)
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if name == pin :
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found = True
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if direction == DirectionOUT : return "output"
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elif direction == DirectionIN : return "input"
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else :
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err = "\nError : unable to find direction of port %s in model %s. Direction is %d\n" % ( pin, model, direction )
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raise Exception ( err )
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if not found :
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err = "\nError : unable to find port %s in model %s.\n" % ( pin, model )
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raise Exception ( err )
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# Stratus cell found:
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elif stCell :
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found = False
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for net in stCell._st_vdds :
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if net._name == pin :
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found = True
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break
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for net in stCell._st_vsss :
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if net._name == pin :
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found = True
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break
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for net in stCell._st_cks :
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if net._name == pin :
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found = True
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break
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# _st_ports i.e. not alimentations and not clock
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for net in stCell._st_ports :
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if net._name == pin :
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found = True
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if net._direct == "OUT" : return "output"
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elif net._direct == "IN" : return "input"
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else :
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err = "\nError : unable to find direction of port %s in model %s.\n" % ( pin, model )
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raise Exception ( err )
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if not found :
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ports = ""
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for net in stCell._st_ports : ports += net._name + ","
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err = "\nError : unable to find port %s in model %s.\nPorts are : %s\n" % ( pin, model, ports )
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raise Exception ( err )
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else :
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err = "\n[ERROR] InitGraph : no model named " + model + " in the database.\n"
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raise Exception ( err )
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#############################
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##### Print of the cell #####
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#############################
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def Print ( self ) :
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print "################## The Cell ##################"
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for inst in self._st_insts :
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print " * inst name :", inst._name
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print " inst model :", inst._model
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for pin in inst._map :
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if pin != 'vdd' and pin != 'vss' :
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net = inst._map[pin]
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print " pin :", pin, "net :", net._name, "with arity :", net._arity
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if net._to_merge :
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net = inst._map[pin]._to_merge[0][0]
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print " net merged with :", net._name, "with arity :", net._arity
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#############################
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##### Find An Instance #####
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#############################
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def getInstance ( self, name ):
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for instance in self._st_insts:
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if instance._name == name:
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return instance
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return None
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#########################
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def PrintGraph ( self ) :
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if "_graph" not in self.__dict__ :
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err = "\n[Stratus ERROR] PrintGraph : The graph does not exist. Use initGraph before.\n"
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raise Exception ( err )
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else :
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if self._graph == False :
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err = "\n[Stratus ERROR] PrintGraph : The graph does not exist. Use initGraph before.\n"
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raise Exception ( err )
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print "################## Cell's Graph features ##################"
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for inst in self._st_insts :
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print " => inst name :", inst._name, "( model :", inst._model, ")"
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print " inst st_nets_in :"
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for net in inst._st_nets_in : print " ", net._name
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print " inst st_nets_out :"
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for net in inst._st_nets_out : print " ", net._name
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for port in self._st_ports :
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print " => port name :", port._name
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if port._st_inst_in : print " port _st_inst_in :", port._st_inst_in._name
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print " port _st_insts_out :"
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for p in port._st_insts_out : print " ", p._name
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for sig in self._st_sigs :
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print " => sig name :", sig._name
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if sig._st_inst_in : print " sig _st_inst_in :", sig._st_inst_in._name
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print " sig _st_insts_out :"
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for s in sig._st_insts_out : print " ", s._name
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for psig in self._st_partsigs :
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print " => part sig name :", psig._name
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if '_st_inst_in' in psig.__dict__ and psig._st_inst_in: print " part sig _st_inst_in :", psig._st_inst_in._name
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if '_st_insts_out' in psig.__dict__ :
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print " part sig _st_insts_out :"
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for s in psig._st_insts_out : print " ", s._name
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#####################
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##### overloard #####
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#####################
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##### __getattr #####
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# def __getattr__ ( self, attr ) :
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##### __str #####
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def __str__ ( self ) :
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s = "Model" + str ( self._hur_cell )
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return s
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########################
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##### VLSI Methods #####
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########################
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##### Interface #####
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def Interface ( self ) :
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print "[Stratus Warning] : Execution of empty Interface method for", self._name, "."
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##### Netlist #####
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def Netlist ( self ) :
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print "[Stratus Warning] : Execution of empty Netlist method for", self._name, "."
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pass
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##### Layout #####
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def Layout ( self ) :
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print "[Stratus Warning] : Execution of empty Layout method for", self._name, "."
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pass
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##### Vbe #####
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def Vbe ( self ) :
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self._vbe = True
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##### View : in order to see the in the editor #####
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def View ( self, stopLevel=1, message="Status stop point" ) :
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global EDITOR
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if not self._hur_cell :
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err = "\n[Stratus ERROR] View : Hurricane Cell does not exist.\nCheck CRL_IN_LO/CRL_IN_PH variables.\n"
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raise Exception ( err )
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if EDITOR:
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EDITOR.setCell ( self._hur_cell )
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EDITOR.fit ()
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if stopLevel > 0:
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Breakpoint.stop ( stopLevel, message )
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##### Save : in order to create the output files #####
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def Save ( self, views = 0, fileName = None ) :
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global FRAMEWORK
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global CELLS
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netlistFormat = Cfg.getParamString('stratus1.format').asString()
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if views == STRATUS :
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self.exportStratus ( fileName )
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elif netlistFormat == 'vst' :
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UpdateSession.open()
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hurCell = self._hur_cell
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if str ( hurCell.getName() ) != "__Scratch__" :
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FRAMEWORK.saveCell ( hurCell, views|CRL.Catalog.State.Logical|CRL.Catalog.State.VstUseConcat )
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if len ( CELLS ) == 0 :
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err = "\n[Stratus ERROR] Save : CELLS stack is empty.\n"
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raise Exception ( err )
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CELLS.pop()
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UpdateSession.close()
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elif netlistFormat == 'stratus' :
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self.exportStratus ( fileName )
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elif netlistFormat in ['vhd','vlog','json'] :
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self.export(netlistFormat)
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else :
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raise Exception('Unrecognized format %s' % netlistFormat)
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##### Simul : in order to use simulation tool #####
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def Simul ( self, name = None, tool = 'asimut' ) :
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from utils import runpat
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if not name : name = self._name
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simulator = Cfg.getParamString('stratus1.simulator').asString()
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if simulator == 'asimut' :
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runpat ( self._name, name, '-l 1 -p 100 -zerodelay -bdd' )
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elif simulator == 'ghdl' :
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import os
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cmd_str = ('ghdl -c -g -Psxlib --ieee=synopsys *.vhd -r %s_run --vcd=%s.vcd' %(name,name))
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os.system(cmd_str)
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elif tool == 'asimut' : runpat ( self._name, name, '-l 1 -p 100 -zerodelay -bdd' )
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else : raise Exception ( 'not implemented yet' )
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##### TestBench : in order to create testbench #####
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def Testbench ( self ) :
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netlistFormat = Cfg.getParamString('stratus1.format').asString()
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import stimuli
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stim = stimuli.Stimuli(self)
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if netlistFormat == 'vhd' :
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# Create stimuli input file
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stim.create_stimuli_text_file()
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# Create testbench
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stim.create_testbench(delay = 20, unit = 'ns', debug = False, downto = True, logic = False)
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# Create testbench and block instance
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stim.create_run(debug = False, downto = True)
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elif netlistFormat == 'vst' :
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stim.create_pat_file()
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else :
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raise Exception('Testbench not yet implemented for format %s' % netlistFormat)
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##### Create a stratus file given the database #####
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def exportStratus ( self, fileName ) :
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## Cat formating ##
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def catName ( net, tableau ) :
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name = "Cat ( "
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paire = tableau[-1]
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if paire :
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net1 = paire[0]
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bit1 = str(paire[1])
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else :
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net1 = net
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bit1 = str(len(tableau)-1)
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for i in range ( len(tableau)-2, -1, -1 ) :
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change = False
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if tableau[i] and not tableau[i+1] :
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change = True
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elif not tableau[i] and tableau[i+1] :
|
|
change = True
|
|
elif tableau[i] and tableau[i+1] :
|
|
if tableau[i][0] != tableau[i+1][0] :
|
|
change = True
|
|
|
|
if change :
|
|
if tableau[i+1] : bit2 = str(tableau[i+1][1])
|
|
else : bit2 = str(i+1)
|
|
|
|
name += "self."
|
|
if int(bit2) == int(net1._ind) and int(bit1) == (net1._arity-1) :
|
|
name += net1._name
|
|
else :
|
|
name += net1._name
|
|
name += "["
|
|
name += bit1
|
|
name += ":"
|
|
name += bit2
|
|
name += "]"
|
|
|
|
name += ", "
|
|
|
|
if tableau[i] : net1 = tableau[i][0]
|
|
else : net1 = net
|
|
|
|
if tableau[i] : bit1 = str(tableau[i][1])
|
|
else : bit1 = str(i)
|
|
|
|
if tableau[0] :
|
|
bit2 = str(tableau[0][1])
|
|
else :
|
|
bit2 = "0"
|
|
|
|
name += "self."
|
|
if int(bit2) == int(net1._ind) and int(bit1) == (net1._arity-1) :
|
|
name += net1._name
|
|
else :
|
|
name += net1._name
|
|
name += "["
|
|
name += bit1
|
|
name += ":"
|
|
name += bit2
|
|
name += "]"
|
|
|
|
name += " )"
|
|
|
|
return name
|
|
|
|
#########################
|
|
nom = str(self.__class__)
|
|
chaine = re.search ( "[^\.]*\.(.*)", nom )
|
|
nom = chaine.group(1)
|
|
|
|
if not fileName : fileName = nom + "_created"
|
|
fileName += ".py"
|
|
|
|
file = open ( fileName, "w+" )
|
|
|
|
file.write ( "#!/usr/bin/python\n\n" )
|
|
file.write ( "from stratus import *\n\n" )
|
|
|
|
file.write ( "class %s ( Model ) :\n\n" % nom )
|
|
|
|
##### Interface #####
|
|
file.write ( " def Interface ( self ) :\n\n" )
|
|
|
|
for net in self._st_ports :
|
|
if net._direct == "IN" : classe = "SignalIn"
|
|
elif net._direct == "OUT" : classe = "SignalOut"
|
|
elif net._direct == "INOUT" : classe = "SignalInOut"
|
|
|
|
file.write ( " self.%s = %s ( \"%s\", %d )\n" % ( net._name, classe, net._name, net._arity ) )
|
|
file.write ( "\n" )
|
|
|
|
for ck in self._st_cks :
|
|
if ck._ext:
|
|
file.write ( " self.%s = CkIn ( \"%s\" )\n" % (ck._name, ck._name) )
|
|
|
|
file.write ( " self.vdd = VddIn ( \"vdd\" )\n" )
|
|
file.write ( " self.vss = VssIn ( \"vss\" )\n" )
|
|
file.write ( "\n" )
|
|
|
|
##### Netlist #####
|
|
file.write ( " def Netlist ( self ) :\n\n" )
|
|
|
|
# Signals
|
|
for net in self._st_sigs :
|
|
if net._to_merge :
|
|
towrite = False
|
|
for paire in net._to_merge :
|
|
if paire == 0 : towrite = True
|
|
if not towrite : continue
|
|
file.write ( " self.%s = Signal ( \"%s\", %d )\n" % ( net._name, net._name, net._arity ) )
|
|
file.write ( "\n" )
|
|
|
|
# Generate
|
|
for cell in CELLS[0]._underCells :
|
|
if CELLS[0]._underCells[cell] == 1 :
|
|
classe = str(cell.__class__)
|
|
nom = cell._name
|
|
param = cell._param
|
|
|
|
# Gestion of libraries with specific treatment
|
|
chaine = re.search ( "(.*)\.([^\.]*)", classe )
|
|
if chaine :
|
|
fichier = chaine.group(1)
|
|
if re.search ( "dpgen_", fichier ) or re.search ( "st_", fichier ) :
|
|
classe = chaine.group(2)
|
|
# Special treatment for virtual library
|
|
if classe == "Bool" :
|
|
nom = cell._name
|
|
classe = cell._param['model']
|
|
param = cell._param
|
|
del param['model']
|
|
del param['realModel']
|
|
|
|
classe = string.upper(classe[0]) + classe[1:] #FIXME !!!
|
|
if re.search ( "(.*)\.([^\.]*)", classe ) : # ArithLib generator
|
|
classe = string.lower(classe[0]) + classe[1:]
|
|
|
|
file.write ( " Generate ( \"%s\", \"%s\", param = %s )\n" % ( classe, nom, param ) )
|
|
file.write ( "\n" )
|
|
|
|
# Instances
|
|
for inst in self._st_insts :
|
|
#chaine = re.search ( "([^_]*)_(.*)", inst._name ) #XTOF FIXME !!!
|
|
#instName = chaine.group(1) #XTOF FIXME !!
|
|
file.write ( " self.%s = Inst ( \"%s\"\n" % ( inst._name, inst._model ) )
|
|
file.write ( " , \"%s\"\n" % inst._name )
|
|
file.write ( " , map = { " )
|
|
|
|
# Map
|
|
for pin in inst._map :
|
|
toto = False
|
|
tata = False
|
|
|
|
netInMap = inst._map[pin]
|
|
nom = "self." + netInMap._name
|
|
|
|
# <=
|
|
if netInMap._to_merge :
|
|
oneperone = True
|
|
for i in range ( len ( netInMap._to_merge ) ) :
|
|
paire = netInMap._to_merge[i]
|
|
|
|
if paire :
|
|
net = paire[0]
|
|
if i > 0 :
|
|
if netInMap._to_merge[i-1] != 0 :
|
|
netbefore = netInMap._to_merge[i-1][0]
|
|
else :
|
|
oneperone = False
|
|
break
|
|
if net != netbefore :
|
|
oneperone = False
|
|
break
|
|
if paire[1] != i :
|
|
oneperone = False
|
|
break
|
|
|
|
else :
|
|
toto = True
|
|
oneperone = False
|
|
break
|
|
|
|
# "easy" case : 1 per 1 corresponding
|
|
if oneperone :
|
|
netInMap = netInMap._to_merge[0][0]
|
|
nom = "self." + netInMap._name
|
|
|
|
# else : Cat of the different signals
|
|
else :
|
|
nom = catName ( netInMap, netInMap._to_merge )
|
|
|
|
# Cat
|
|
if netInMap._to_cat :
|
|
tata = True
|
|
nom = catName ( netInMap, netInMap._to_cat )
|
|
|
|
if toto and tata : print "Attention est ce un cas bien gere ???"
|
|
|
|
if pin == inst._map.keys()[0] : file.write ( "\"%s\" : %s\n" % ( pin, nom ) )
|
|
else : file.write ( " , \"%s\" : %s\n" % ( pin, nom ) )
|
|
|
|
file.write ( " }\n" )
|
|
file.write ( " )\n\n" )
|
|
|
|
##### End #####
|
|
file.close ()
|
|
|
|
##### Export the given database in the given format
|
|
def export ( self, format):
|
|
from st_export import write
|
|
|
|
if format not in ['vhd','vlog','json']:
|
|
raise "Unrecognized format %s" %(format)
|
|
write(self,format)
|
|
|
|
##### Create a IEEE VHDL file given the database #####
|
|
def exportVHD ( self ) :
|
|
|
|
file = open ( self._name + '.vhd', "w+" )
|
|
|
|
file.write ( "--\n" )
|
|
file.write ( "-- Generated by VHDL export\n" )
|
|
file.write ( "--\n" )
|
|
file.write ( "library ieee;\n" )
|
|
file.write ( "use ieee.std_logic_1164.all;\n\n" )
|
|
|
|
if 'realModel' in self._param :
|
|
file.write ( "library sxlib;\n" )
|
|
file.write ( "use sxlib.all;\n\n" )
|
|
|
|
|
|
##### Entity #####
|
|
file.write ( "entity %s is\n" % self._name )
|
|
file.write ( " port(\n" )
|
|
|
|
strPorts = ""
|
|
for net in self._st_ports :
|
|
if net._arity == 1 :
|
|
strPorts += " %s : %s std_logic;\n" % ( net._name, net._direct )
|
|
else :
|
|
strPorts += " %s : %s std_logic_vector(%d downto %d);\n" % ( net._name, net._direct, net._arity-1+net._ind, net._ind )
|
|
|
|
for ck in self._st_cks :
|
|
if ck._ext:
|
|
strPorts += " %s : IN std_logic;\n" % ( ck._name )
|
|
|
|
file.write(strPorts[:-2])
|
|
file.write ( "\n );\n" )
|
|
file.write ( "end %s ;\n\n" % self._name )
|
|
|
|
##### Architecture #####
|
|
file.write ( "architecture structural of %s is\n" % self._name )
|
|
|
|
|
|
# Components
|
|
if 'realModel' in self._param :
|
|
cellList = [self]
|
|
else :
|
|
cellList = self._underCells
|
|
for cell in cellList :
|
|
if 'realModel' in self._param :
|
|
nom = cell._param['realModel']
|
|
else :
|
|
nom = cell._name
|
|
#classe = str(cell.__class__)
|
|
#nom = cell._name
|
|
#param = cell._param
|
|
#print "nom " + nom
|
|
#print "classe " + classe
|
|
|
|
## Gestion of libraries with specific treatment
|
|
#chaine = re.search ( "(.*)\.([^\.]*)", classe )
|
|
#if chaine :
|
|
# fichier = chaine.group(1)
|
|
# if re.search ( "dpgen_", fichier ) or re.search ( "st_", fichier ) :
|
|
# classe = chaine.group(2)
|
|
# # Special treatment for virtual library
|
|
# if classe == "Bool" :
|
|
# #nom = cell._name
|
|
# nom = cell._param['realModel']
|
|
# classe = cell._param['model']
|
|
# param = cell._param
|
|
# #del param['model']
|
|
# #del param['realModel']
|
|
|
|
#classe = string.upper(classe[0]) + classe[1:] #FIXME !!!
|
|
#if re.search ( "(.*)\.([^\.]*)", classe ) : # ArithLib generator
|
|
# classe = string.lower(classe[0]) + classe[1:]
|
|
|
|
file.write ( " component %s\n" % nom )
|
|
file.write ( " port(\n" )
|
|
|
|
# Ports
|
|
strPorts = ""
|
|
for net in cell._st_ports :
|
|
if net._arity == 1 :
|
|
strPorts += " %s : %s std_logic;\n" % ( net._name, net._direct )
|
|
else :
|
|
strPorts += " %s : %s std_logic_vector(%d downto %d);\n" % ( net._name, net._direct, net._arity-1+net._ind, net._ind )
|
|
|
|
for ck in cell._st_cks :
|
|
if ck._ext:
|
|
strPorts += " %s : IN std_logic;\n" % ( ck._name )
|
|
|
|
file.write(strPorts[:-2])
|
|
|
|
file.write ( "\n );\n" )
|
|
file.write ( " end component;\n\n")
|
|
|
|
# Signals
|
|
for net in self._st_sigs :
|
|
if net._to_merge :
|
|
towrite = False
|
|
for paire in net._to_merge :
|
|
if paire == 0 : towrite = True
|
|
if not towrite : continue
|
|
if net._arity == 1 :
|
|
file.write ( " signal %s : std_logic;\n" % net._name )
|
|
else :
|
|
file.write ( " signal %s : std_logic_vector(%d downto %d);\n" % ( net._name, net._arity-1+net._ind, net._ind ) )
|
|
|
|
# Instances
|
|
file.write ( "\nbegin\n" )
|
|
for inst in self._st_insts :
|
|
#chaine = re.search ( "([^_]*)_(.*)", inst._name ) #XTOF FIXME !!!
|
|
#instName = chaine.group(1) #XTOF FIXME !!
|
|
file.write ( " %s : %s\n" % ( inst._name, inst._model ) )
|
|
file.write ( " port map(\n" )
|
|
|
|
# Map
|
|
strMap = ""
|
|
for pin in inst._map :
|
|
toto = False
|
|
tata = False
|
|
|
|
netInMap = inst._map[pin]
|
|
if netInMap._real_net :
|
|
nom = netInMap._real_net._name
|
|
else :
|
|
nom = netInMap._name
|
|
|
|
# <=
|
|
if netInMap._to_merge :
|
|
oneperone = True
|
|
for i in range ( len ( netInMap._to_merge ) ) :
|
|
paire = netInMap._to_merge[i]
|
|
|
|
if paire :
|
|
net = paire[0]
|
|
if i > 0 :
|
|
if netInMap._to_merge[i-1] != 0 :
|
|
netbefore = netInMap._to_merge[i-1][0]
|
|
else :
|
|
oneperone = False
|
|
break
|
|
if net != netbefore :
|
|
oneperone = False
|
|
break
|
|
if paire[1] != i :
|
|
oneperone = False
|
|
break
|
|
|
|
else :
|
|
toto = True
|
|
oneperone = False
|
|
break
|
|
|
|
# "easy" case : 1 per 1 corresponding
|
|
if oneperone :
|
|
netInMap = netInMap._to_merge[0][0]
|
|
nom = netInMap._name
|
|
|
|
# else : Cat of the different signals
|
|
else :
|
|
nom = catName ( netInMap, netInMap._to_merge )
|
|
|
|
# Cat
|
|
if netInMap._to_cat :
|
|
tata = True
|
|
nom = catName ( netInMap, netInMap._to_cat )
|
|
|
|
if toto and tata : print "Attention est ce un cas bien gere ???"
|
|
|
|
if netInMap not in self._st_vdds + self._st_vsss :
|
|
if pin == inst._map.keys()[0] : strMap += " %s => %s,\n" % ( pin, nom )
|
|
else : strMap += " %s => %s,\n" % ( pin, nom )
|
|
|
|
file.write(strMap[:-2] + '\n')
|
|
file.write ( " );\n\n" )
|
|
|
|
##### End #####
|
|
file.write('end structural;')
|
|
file.close ()
|
|
|
|
|
|
#### Quit : to quit the current cell without saving #####
|
|
def Quit ( self ) :
|
|
global CELLS
|
|
|
|
CELLS.pop ()
|
|
|
|
#########################################
|
|
##### GetModelName : Class's method #####
|
|
#########################################
|
|
def GetModelName ( param ) :
|
|
return None
|
|
GetModelName = staticmethod ( GetModelName )
|
|
|
|
#########################################
|
|
##### GetParam : Class's method #####
|
|
#########################################
|
|
def GetParam () :
|
|
return None
|
|
GetParam = staticmethod ( GetParam )
|
|
|
|
###############
|
|
##### Set #####
|
|
###############
|
|
def SetAnd ( self, model ) : self._and = model
|
|
def SetOr ( self, model ) : self._or = model
|
|
def SetXor ( self, model ) : self._xor = model
|
|
def SetNot ( self, model ) : self._not = model
|
|
|
|
def SetBuff ( self, model ) : self._buff = model
|
|
def SetReg ( self, model ) : self._reg = model
|
|
def SetMux ( self, model ) : self._mux = model
|
|
def SetShift ( self, model ) : self._shift = model
|
|
def SetComp ( self, model ) : self._comp = model
|
|
|
|
def SetAdd ( self, model ) : self._add = model
|
|
def SetMult ( self, model ) : self._mult = model
|
|
def SetDiv ( self, model ) : self._div = model
|
|
|
|
def SetSigned ( self, model ) : self._signed = model
|
|
def SetExtended ( self, model ) : self._extended = model
|
|
|
|
#############################
|
|
##### Creation of model #####
|
|
#############################
|
|
def ModelCreation ( self, modele, modele2, dict, hierarchy, realModele = None, inOut = None ) :
|
|
global CELLS
|
|
|
|
from st_parser import BVg
|
|
|
|
## Virtual library ##
|
|
from st_bool import Bool
|
|
|
|
## Stratus generators ##
|
|
from st_mux import Smux
|
|
from st_shifter import Shifter
|
|
from st_comp import Comp
|
|
from st_const import Constant
|
|
from st_extend import Extend
|
|
|
|
from st_slansky import Slansky
|
|
from st_slansky import Sub
|
|
from st_mult import Multiplier
|
|
|
|
## Genlib ##
|
|
from dpgen_Shifter import DpgenShifter
|
|
from dpgen_Shrot import DpgenShrot
|
|
from dpgen_Nul import DpgenNul
|
|
from dpgen_RAM import DpgenRam
|
|
from dpgen_ROM2 import DpgenRom2
|
|
from dpgen_ROM4 import DpgenRom4
|
|
from dpgen_ADSB2F import DpgenAdsb2f
|
|
from dpgen_RF1 import DpgenRf1, DpgenRf1d, DpgenRf1r0, DpgenRf1dr0, DpgenFifo
|
|
from dpgen_RF2 import DpgenRf2, DpgenRf2d, DpgenRf2r0, DpgenRf2dr0
|
|
from dpgen_Regular import DpgenAnd2, DpgenAnd3, DpgenAnd4, DpgenBuff, DpgenBuse, DpgenConst, DpgenDff, DpgenDfft, DpgenInv, DpgenMux2, DpgenNand2, DpgenNand2mask, DpgenNand3, DpgenNand4, DpgenNbuse, DpgenNmux2, DpgenNor2, DpgenNor2mask, DpgenNor3, DpgenNor4, DpgenOr2, DpgenOr3, DpgenOr4, DpgenSff, DpgenSfft, DpgenXnor2, DpgenXnor2mask, DpgenXor2
|
|
|
|
from util_Gen import F_MSB_FIRST
|
|
|
|
if type ( dict ) != types.DictType :
|
|
err = "\n[Stratus ERROR] Inst : instanciation of a user's defined generator. The methods' arguments must be dictionnaries.\n"
|
|
raise Exception ( err )
|
|
|
|
##### Creation of the instance #####
|
|
# dict['flags'] = F_MSB_FIRST # When vst driver permits to do F_LSB_FIRST or F_LSB_FIRST TODO
|
|
# dict['flags'] = 0
|
|
|
|
## Virtual library ##
|
|
if modele in BVg :
|
|
dict['model'] = modele.lower()
|
|
dict['realModel'] = realModele
|
|
|
|
instCell = Bool ( modele2, dict, inOut )
|
|
|
|
## Generator ##
|
|
elif re.search ( "\.", modele ) :
|
|
chaine = re.search ( "(.*)\.([^\.]*)$", modele )
|
|
|
|
ficName = chaine.group(1)
|
|
className = chaine.group(2)
|
|
|
|
# Roselyne : pour prendre en compte les modeles recursifs
|
|
#import sys
|
|
moduleClass = __import__ ( ficName, globals(), locals(), [className] )
|
|
modeleClass = getattr ( moduleClass, className )
|
|
#try :
|
|
# modeleClass = getattr ( sys.modules['__main__'], className )
|
|
#except AttributeError :
|
|
# moduleClass = __import__ ( ficName, globals(), locals(), [className] )
|
|
# modeleClass = getattr ( moduleClass, className )
|
|
# fin Roselyne
|
|
|
|
instCell = modeleClass ( modele2, dict )
|
|
|
|
else :
|
|
instCell = eval ( "%s ( \"%s\", %s )" % ( modele, modele2, str(dict) ) )
|
|
|
|
## MAJ of the hierarchy ##
|
|
instCell._hierarchy = hierarchy
|
|
|
|
##### Methods #####
|
|
if ( self._hur_cell ) and ( not instCell._hur_cell ) : instCell.HurricanePlug()
|
|
|
|
instCell.Interface()
|
|
instCell.Netlist()
|
|
|
|
if ( 'clean' in dict ) and ( dict['clean'] != False ) :
|
|
if 'interactive' not in dict : dict['interactive'] = False
|
|
instCell.Clean ( dict['interactive'], dict['clean'] )
|
|
|
|
if ( 'behavioral' in dict ) and ( dict['behavioral'] == True ) :
|
|
instCell.Vbe()
|
|
|
|
if instCell._hur_cell :
|
|
v = 0
|
|
if ( 'physical' in dict ) and ( dict['physical'] == True ) :
|
|
instCell.Layout()
|
|
v = CRL.Catalog.State.Physical
|
|
instCell.Save( v|CRL.Catalog.State.Logical )
|
|
|
|
else :
|
|
instCell.Quit()
|
|
|
|
if CELLS[0] != instCell : CELLS[0]._underCells[instCell] = hierarchy
|
|
|
|
return instCell
|
|
|
|
#################################################################
|
|
##### HurricanePlug : in order to create the hurricane cell #####
|
|
#################################################################
|
|
def HurricanePlug ( self ) :
|
|
global FRAMEWORK, CELLS
|
|
|
|
if self._hur_cell :
|
|
print "[Stratus Warning] : The stratus cell already exists."
|
|
return
|
|
|
|
self._hur_plug = True
|
|
|
|
##### Creation of all the under cells #####
|
|
# Initialisation of the max depth
|
|
max_depth = 0
|
|
for keyCell in self._underCells :
|
|
if self._underCells[keyCell] > max_depth : max_depth = self._underCells[keyCell]
|
|
# Creation from the leaf to the top cell
|
|
while max_depth :
|
|
for keyCell in self._underCells :
|
|
if self._underCells[keyCell] == max_depth :
|
|
if not FRAMEWORK.getCell ( keyCell._name, CRL.Catalog.State.Views ) :
|
|
CELLS.append ( keyCell )
|
|
keyCell.CellHurCreation()
|
|
max_depth -= 1
|
|
|
|
# Creation of the top cell
|
|
CELLS.append ( self )
|
|
self.CellHurCreation()
|
|
|
|
##### CellHurCreation #####
|
|
def CellHurCreation ( self ) :
|
|
global FRAMEWORK, CELLS
|
|
|
|
# The cell
|
|
hurCell = FRAMEWORK.createCell ( self._name )
|
|
hurCell.setTerminal ( 0 )
|
|
|
|
self._hur_cell = hurCell
|
|
|
|
MODELMAP [ str ( self._hur_cell ) ] = self
|
|
|
|
# The nets
|
|
for net in self._st_ports : net.create_hur_net()
|
|
for net in self._st_sigs : net.create_hur_net()
|
|
|
|
|
|
for net in self._st_cks : net.create_hur_net()
|
|
|
|
for net in self._st_vdds : net.create_hur_net()
|
|
for net in self._st_vsss : net.create_hur_net()
|
|
|
|
# The instances and the connection
|
|
for inst in self._st_insts : inst.create_hur_inst ( inst._model )
|
|
|
|
# Merge
|
|
for net in self._st_merge : net.hur_merge()
|
|
|
|
if ( self != CELLS[0] ) and ( self._st_insts ) : # Layout done if HurricanePlug after Netlist method
|
|
#self.Layout() # FIXME trouver une raison de le faire ou pas : instances placees ou pas ... HurricanePlug ne doit plus marcher avec placement A VERIFIER 14/01/08
|
|
if self._st_insts[0]._hur_instance.getPlacementStatus() : self.Save ( CRL.Catalog.State.Physical )
|
|
else : self.Save ( CRL.Catalog.State.Logical )
|
|
else :
|
|
self.Quit()
|
|
|
|
####################
|
|
##### Clean Up #####
|
|
####################
|
|
def Clean ( self, interactive = False, tab_name_net = [] ) :
|
|
|
|
# Hurricane cell
|
|
hurricane_cell = self._hur_cell
|
|
|
|
# Useful for print
|
|
TAB_NETS = []
|
|
TAB_INSTS = []
|
|
cpt_inst_del = 0
|
|
cpt_net_del = 0
|
|
|
|
##### Tabs initialisation #####
|
|
net_entree = []
|
|
net_sortie = []
|
|
net_interne = []
|
|
|
|
for net in hurricane_cell.getNets():
|
|
if net.getDirection() == DirectionUNDEFINED : net_interne.append ( net )
|
|
elif net.getDirection() == DirectionIN : net_entree.append ( net )
|
|
elif net.getDirection() == DirectionOUT : net_sortie.append ( net )
|
|
|
|
##### File initialisation #####
|
|
file = []
|
|
|
|
# Output nets put in the file if there are given as arguments
|
|
if tab_name_net != True :
|
|
for net_name in tab_name_net :
|
|
for net in net_sortie :
|
|
if net_name == str ( net.getName() ) :
|
|
file.insert ( 0, net )
|
|
if interactive : print "Output Net", net, "has to be erased, it is put in the fifo."
|
|
|
|
## Internal nets ##
|
|
# Number of plugs of each net :
|
|
# if equal to 0 : del net
|
|
# if equal to 1 : put net in the file
|
|
for net in net_interne :
|
|
nb_plugs = self.count_plugs ( net )
|
|
|
|
if nb_plugs == 0 :
|
|
if interactive : print "* One net suppressed (a) :", net
|
|
TAB_NETS.append ( net.getName () )
|
|
cpt_net_del += 1
|
|
|
|
net.Delete()
|
|
|
|
elif nb_plugs == 1 :
|
|
if net.getPlugs().next().getMasterNet().getDirection() == DirectionOUT: # output of an instance
|
|
if interactive : print "* One net put in the fifo :", net
|
|
file.insert ( 0, net )
|
|
|
|
## Ouput nets ##
|
|
# Number of plugs of each net :
|
|
# if equal to 0 : del net
|
|
for net in net_sortie + net_entree :
|
|
cpt_plugs_sor = self.count_plugs ( net )
|
|
if cpt_plugs_sor == 0 :
|
|
print "[Stratus Warning] Clean : Interface of", self._name, "changed, net :", net, "is suppressed"
|
|
TAB_NETS.append ( net.getName() )
|
|
cpt_net_del += 1
|
|
|
|
net.Delete()
|
|
|
|
##### Algorithm #####
|
|
while len ( file ) > 0 :
|
|
net_file = file.pop()
|
|
plug = net_file.getPlugs().next()
|
|
inst = plug.getInstance()
|
|
|
|
# input nets of the instance
|
|
plugs_inst = inst.getPlugs()
|
|
net_entree_inst = []
|
|
net_sortie_inst = []
|
|
cpt_sortie = 0
|
|
|
|
for plug_de_inst in plugs_inst:
|
|
# compute the number of outputs of the instance
|
|
if plug_de_inst.getMasterNet().getDirection() == DirectionOUT :
|
|
cpt_sortie += 1
|
|
# output nets of the instance put in tab, except for the net being worked on
|
|
if net_file != plug_de_inst.getNet() : net_sortie_inst.append ( plug_de_inst.getNet() )
|
|
|
|
if plug_de_inst.getMasterNet().getDirection() == DirectionIN :
|
|
# ignore vdd and vss
|
|
type = plug_de_inst.getNet().getType()
|
|
if type not in ( Net.Type.POWER, Net.Type.GROUND ) : net_entree_inst.append ( plug_de_inst.getNet() )
|
|
|
|
### Deletion of te instance ###
|
|
# If the instance has only one output
|
|
if cpt_sortie == 1 :
|
|
if interactive : print "* One net suppressed (b) :", net_file
|
|
TAB_NETS.append ( net_file.getName() )
|
|
cpt_net_del += 1
|
|
|
|
net_file.Delete()
|
|
|
|
if interactive : print "* One instance suppressed (a) :", inst, inst
|
|
TAB_INSTS.append(inst.getName())
|
|
cpt_inst_del += 1
|
|
|
|
UpdateSession.open()
|
|
inst.Delete()
|
|
UpdateSession.close()
|
|
|
|
for net_ent in net_entree_inst :
|
|
cpt_plugs_in = self.count_plugs ( net_ent )
|
|
if cpt_plugs_in == 0 :
|
|
if net_ent in net_entree :
|
|
print "[Stratus Warning] Clean : Interface of", self._name, "changed, net :", net_ent, "is suppressed"
|
|
|
|
TAB_NETS.append ( net_ent.getName() )
|
|
cpt_net_del += 1
|
|
|
|
net_ent.Delete()
|
|
else :
|
|
if interactive : print "* One net suppressed (c) : ", net_ent
|
|
|
|
TAB_NETS.append ( net_ent.getName() )
|
|
cpt_net_del += 1
|
|
|
|
net_ent.Delete()
|
|
|
|
elif cpt_plugs_in == 1 :
|
|
if net_ent.getPlugs().next().getMasterNet().getDirection() == DirectionOUT : # is an output net of another instance
|
|
if interactive : print "* One net put in the fifo :", net_ent
|
|
file.insert ( 0, net_ent )
|
|
|
|
# If the instance has more than one output
|
|
elif cpt_sortie >= 2 :
|
|
connect = False
|
|
for net_sor in net_sortie_inst:
|
|
cpt_sor = self.count_plugs ( net_sor )
|
|
if cpt_sor >= 2 :
|
|
connect = True # at least one output connected
|
|
break
|
|
elif cpt_sor == 1 :
|
|
if net_sor in net_sortie :
|
|
connect = True # at least one output connected
|
|
break
|
|
|
|
if not ( connect ) :
|
|
if interactive : print "* One net suppressed (d) :", net_file
|
|
|
|
TAB_NETS.append ( net_file.getName() )
|
|
cpt_net_del += 1
|
|
|
|
net_file.Delete()
|
|
|
|
for net_sor in net_sortie_inst :
|
|
if net_sor in file : file.remove ( net_sor )
|
|
|
|
if interactive : print "* One net suppressed (e) :", net_sor
|
|
TAB_NETS.append ( net_sor.getName() )
|
|
cpt_net_del += 1
|
|
|
|
net_sor.Delete()
|
|
|
|
if interactive : print "* One instance suppressed (b) :", inst
|
|
TAB_INSTS.append ( inst.getName() )
|
|
cpt_inst_del += 1
|
|
|
|
UpdateSession.open()
|
|
inst.Delete()
|
|
UpdateSession.close()
|
|
|
|
for net_ent in net_entree_inst :
|
|
cpt_plugs_in = self.count_plugs ( net_ent )
|
|
|
|
if cpt_plugs_in == 0 :
|
|
if net_ent in net_entree :
|
|
print "[Stratus Warning] Clean : Interface of", self._name, "changed, net :", net_ent, "is suppressed"
|
|
|
|
TAB_NETS.append ( net_ent.getName() )
|
|
cpt_net_del += 1
|
|
|
|
net_ent.Delete()
|
|
|
|
else :
|
|
if interactive : print "* One net suppressed (f) :", net_ent
|
|
|
|
TAB_NETS.append ( net_ent.getName() )
|
|
cpt_net_del += 1
|
|
|
|
net_ent.Delete()
|
|
|
|
elif cpt_plugs_in == 1 :
|
|
if net_ent.getPlugs().next().getMasterNet().getDirection() == DirectionOUT: # in an output net of another instance
|
|
if interactive : print "* One net net put in the fifo :", net_ent
|
|
file.insert ( 0, net_ent )
|
|
|
|
else :
|
|
if interactive : print "The net", net_file, "can not be delayed, it may be delayed later"
|
|
|
|
else :
|
|
print "[Warning] Pb in Clean."
|
|
|
|
if interactive :
|
|
print ""
|
|
print "* Number of net suppressed :", cpt_net_del
|
|
print "* List of these nets :", TAB_NETS
|
|
print ""
|
|
print "* Number of instances suppressed :", cpt_inst_del
|
|
print "* List of these instance :", TAB_INSTS
|
|
print ""
|
|
|
|
###############################
|
|
def count_plugs ( self, net ) :
|
|
return len(net.getPlugs())
|
|
|
|
|
|
#############################################################################
|
|
############################## Place and route ##############################
|
|
#############################################################################
|
|
#def getCore ( self ) :
|
|
# '''This function returns the instance "core" : the only one which is not a pad'''
|
|
|
|
# from placeandroute import isPad
|
|
|
|
# cores = []
|
|
# for instance in self._hur_cell.getInstances():
|
|
# if not isPad ( instance ):
|
|
# cores.append ( instance )
|
|
|
|
# if len(cores) == 0 : err = "\n[Stratus ERROR] getCore : No core found.\n"
|
|
# elif len(cores) > 1 : err = "\n[Stratus ERROR] getCore : More than one core found.\n"
|
|
# if len(cores) != 1 : raise Exception ( err )
|
|
|
|
# return cores[0]
|