coriolis/crlcore
Jean-Paul Chaput ae4d938553 Buffer cell configuration in ClockTree. More config parameters in Chip.
* New: In ClockTree plugin, select the name of the buffer cell through
    configuration (parameter: "clockTree.buffer"), and guess the I/O
    name of this buffer automatically.
      Put configuration parameters in plugin.conf and not mauka.conf.
      Bug: strangely triggers a coredump in components collection
    when used with <vsxlib>. Some debug printing still active until
    that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
    configuration parameters (in plugin.conf).
2014-09-02 11:17:47 +02:00
..
cmake_modules * ./crlcore: 2013-03-13 13:38:38 +00:00
doc Correction of SoC.css, adjust the look of the class index big letters. 2014-06-10 00:04:48 +02:00
etc Buffer cell configuration in ClockTree. More config parameters in Chip. 2014-09-02 11:17:47 +02:00
src Add management of fixed wires to Kite (for chip ClockTree) 2014-08-15 19:26:49 +02:00
CMakeLists.txt Starting to implement support for Windows/Cygwin. 2014-07-13 13:14:49 +02:00