439 lines
22 KiB
Python
439 lines
22 KiB
Python
#!/usr/bin/python
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import sys
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from Hurricane import *
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from CRL import *
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import helpers
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from helpers.io import ErrorMessage as Error
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from helpers import trace
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import oroshi
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from CapacitorUnit import CapacitorUnit
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from CapacitorMatrix import CapacitorStack
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from collections import OrderedDict
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import numpy
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## Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix. Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routeing tracks that represent top plates and bottom plates nets of C1 and C2 . Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routeing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool routeer, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions \f$ R*C \f$, the total number of vertical tracks is \f$ 2C+2 \f$ equivalent to \f$ C+1 \f$ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.
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# \image html Layout.png "Layout" width=.1\linewidth
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# An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.
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class VerticalRoutingTracks( CapacitorUnit, CapacitorStack ):
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rules = oroshi.getRules()
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def __init__( self, capacitorInstance, capacitor, minimizeVRT = False ) :
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self.device = capacitorInstance.device
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self.capacitorInstance = capacitorInstance
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self.capacitor = capacitor
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self.matchingScheme = capacitorInstance.matchingScheme
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self.capacitorType = capacitorInstance.capacitorType
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self.abutmentBox = capacitorInstance.abutmentBox
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self.matrixDim = self.capacitorInstance.matrixDim
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self.nets = capacitorInstance.nets
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self.capacitorsNumber = capacitorInstance.capacitorsNumber
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self.dummyRing = capacitorInstance.dummyRing
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self.dummyElement = capacitorInstance.dummyElement
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print('capacitorInstance.capacitance',capacitorInstance.capacitance)
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self.capacitorIds = range(0,self.capacitorsNumber)
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self.abutmentBox_spacing = capacitorInstance.abutmentBox_spacing
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self.vRoutingTrack_width = self.capacitorInstance.vRoutingTrack_width
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self.vRoutingTrackXCenter = []
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self.vRoutingTrackDict = {}
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self.minimizeVRT = minimizeVRT
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self.vRTsToEliminate = []
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self.vRTsDistribution = []
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self.platesDistribution = []
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return
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## Sets vertical stretching value considering spacing between elementary capacitors in the matrix.
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# \return stratching value.
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def __setStretching__( self ): return self.minSpacing_botPlate + self.abutmentBox_spacing/2
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## Defines technology rules used to draw the layout. Some of the rules, namely those describing routeing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different. \remark All \c CapacitorStack class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported.
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# \return a dictionary with rules labels as keys and rules content as values.
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def setRules ( self ):
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CapacitorStack.setRules ( self )
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CapacitorUnit.__setattr__ ( self, "minWidth_hRoutingTrackCut" , VerticalRoutingTracks.rules.minWidth_cut2 )
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CapacitorUnit.__setattr__ ( self, "minWidth_hRoutingLayer_vRoutingTrack_cut" , VerticalRoutingTracks.rules.minWidth_cut2 )
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CapacitorUnit.__setattr__ ( self, "minWidth_hRoutingTrack" , VerticalRoutingTracks.rules.minWidth_metal2 )
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CapacitorUnit.__setattr__ ( self, "minEnclosure_hRoutingLayer_vRoutingTrack_cut" , VerticalRoutingTracks.rules.minEnclosure_metal2_cut2 )
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CapacitorUnit.__setattr__ ( self, "minEnclosure_hRoutingTrackCut" , VerticalRoutingTracks.rules.minEnclosure_metal2_cut2 )
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CapacitorUnit.__setattr__ ( self, "minWidth_hRoutingLayer" , VerticalRoutingTracks.rules.minWidth_metal2 )
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CapacitorUnit.__setattr__ ( self, "minSpacing_hRoutingTrack" , VerticalRoutingTracks.rules.minSpacing_metbot )
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return
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def create( self ):
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UpdateSession.open ()
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self.setRules ()
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vRoutingTracksLayer = DataBase.getDB().getTechnology().getLayer("metal3" )
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if self.capacitorInstance.doMatrix == True and self.capacitorsNumber > 1 :
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self.minimizeVRTs()
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self.computeVRTDimensions()
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self.drawVRoutingTracks( vRoutingTracksLayer )
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else : raise Error(1, 'create() : Impossible to route. This class only routes a matrix of two or more capacitors. Please use <routeCapacitorMatrix> class instead.')
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UpdateSession.close ()
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return
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## Iteratively draws vertical routing tracks given the physical layer \c vRoutingTracksLayer. Every elementary capacitor is consequently positioned between four routing tracks, two from each side. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in [1,2]. As given in Figure 2, capacitor \f$ C_{ij} \f$ with an even j value situated in even columns have and inversily for odd columns numbers.
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def drawVRoutingTracks ( self, vRoutingTracksLayer ) :
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netsDistribution = self.__setNetsDistribution__()
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k = 0
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print('netsDistribution',netsDistribution)
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for j in range( 0, self.matrixDim["columns"] + 1 ):
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for key in self.vRoutingTrackXCenter[j]:
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if self.vRoutingTrackXCenter[j][key] != None:
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Vertical.create( netsDistribution[j][k] , vRoutingTracksLayer , self.vRoutingTrackXCenter[j][key] , self.vRoutingTrack_width , self.vRoutingTrackDict["YMin"] , self.vRoutingTrackDict["YMax"] )
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k = k + 1 if k < len(key)-1 else 0
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return
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def computeVRTDimensions( self ) :
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self.hRoutingTrack_width = max( self.minWidth_hRoutingTrack, self.minWidth_hRoutingTrackCut + 2*self.minEnclosure_hRoutingTrackCut )
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abutmentBoxXMin = self.capacitorInstance.computeAbutmentBoxDimensions( self.abutmentBox_spacing) ["XMin"]
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abutmentBoxYMin = self.capacitorInstance.computeAbutmentBoxDimensions( self.abutmentBox_spacing )["YMin"]
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abutmentBoxYMax = abutmentBoxYMin + self.capacitorInstance.computeAbutmentBoxDimensions( self.abutmentBox_spacing )["height"]
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self.minimumPosition = abutmentBoxYMin - self.__setStretching__()
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self.maximumPosition = abutmentBoxYMax + self.__setStretching__()
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vRTsNumber = self.__computeVRTsNumber__()
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print("vRTsNumber",vRTsNumber)
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self.vRoutingTrackDict["YMin"] = self.minimumPosition - vRTsNumber*(self.hRoutingTrack_width + self.minSpacing_hRoutingTrack)
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self.vRoutingTrackDict["YMax"] = self.maximumPosition + vRTsNumber*(self.hRoutingTrack_width + self.minSpacing_hRoutingTrack)
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self.__setPlatesDistribution__()
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self.computeXCenters()
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return
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def __computeVRTsNumber__ ( self ):
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if self.dummyElement == True :
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vRTsNumber = 2*self.capacitorsNumber - 1
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else :
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vRTsNumber = 2*self.capacitorsNumber + 1 if self.dummyRing == True else 2*self.capacitorsNumber
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return vRTsNumber
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def computeXCenters( self ):
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unitCapDim = self.capacitorInstance.getCapDim()
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abutmentBoxUnitCap_width = CapacitorUnit.computeAbutmentBoxDimensions( self, unitCapDim )["width"]
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unitCapXMin = self.abutmentBox.getXMin() if self.dummyRing == False else self.abutmentBox.getXMin() + abutmentBoxUnitCap_width + self.capacitorInstance.abutmentBox_spacing
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vRoutingTrack_spacing = self.capacitorInstance.minSpacing_vRoutingTrack
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[ factor1 , factor2 ] = [ self.capacitorsNumber , self.capacitorsNumber-1 ] if ( self.capacitorsNumber % 2 == 0 ) else [ self.capacitorsNumber + 1 , self.capacitorsNumber ]
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if self.vRTsToEliminate[0][0] == 1 :
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self.vRoutingTrackXCenter.append( OrderedDict() )
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self.vRoutingTrackXCenter[0][ self.platesDistribution[0][0] ] = unitCapXMin - factor1*vRoutingTrack_spacing - (factor2)*self.vRoutingTrack_width - self.vRoutingTrack_width/2
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else :
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self.vRoutingTrackXCenter.append( OrderedDict() )
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self.vRoutingTrackXCenter[0][ self.platesDistribution[0][0] ] = None
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leftVRTNumber = self.capacitorsNumber if ( self.capacitorsNumber % 2 == 0 ) else self.capacitorsNumber + 1
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for k in range( 1, leftVRTNumber ):
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self.vRoutingTrackXCenter[0][self.platesDistribution[0][k]] = unitCapXMin - (factor1-k)*vRoutingTrack_spacing -(factor2-k)*self.vRoutingTrack_width - self.vRoutingTrack_width/2 if self.vRTsToEliminate[0][k] == 1 else None
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print('self.vRoutingTrackXCenter',self.vRoutingTrackXCenter)
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for j in range( 1, self.matrixDim["columns"] + 1 ):
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factor3 = j - 1 if self.dummyRing == False else j
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unitCapXMin = self.abutmentBox.getXMin() + factor3*( abutmentBoxUnitCap_width + self.capacitorInstance.abutmentBox_spacing )
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unitCapXMax = unitCapXMin + abutmentBoxUnitCap_width
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if self.vRTsToEliminate[j][0] == 1:
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self.vRoutingTrackXCenter.append( OrderedDict() )
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self.vRoutingTrackXCenter[j][ self.platesDistribution[j][0] ] = unitCapXMax + vRoutingTrack_spacing + self.vRoutingTrack_width/2
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else :
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self.vRoutingTrackXCenter.append( OrderedDict() )
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self.vRoutingTrackXCenter[j][ self.platesDistribution[j][0] ] = None
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if self.capacitorsNumber % 2 == 0:
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rightVRTNumber = self.capacitorsNumber
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else :
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if (j % 2 == 0) :
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rightVRTNumber = self.capacitorsNumber + 1
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else : rightVRTNumber = self.capacitorsNumber - 1 if self.dummyElement == False else self.capacitorsNumber - 2
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for k in range( 1, rightVRTNumber ):
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self.vRoutingTrackXCenter[j][ self.platesDistribution[j][k] ] = unitCapXMax + (k+1)*vRoutingTrack_spacing + (k)*self.vRoutingTrack_width + self.vRoutingTrack_width/2 if self.vRTsToEliminate[j][k] == 1 else None
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print('self.vRoutingTrackXCenter',self.vRoutingTrackXCenter)
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return
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def __findUsedCapIdsPerColumn__( self ):
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usedCapIdsPerColumn = []
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for j in range(0, self.matrixDim["columns"] ):
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usedCapIdsPerColumn.append( [self.matchingScheme[0][j]] )
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for i in range(1, self.matrixDim["rows"] ):
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usedCapIdsPerColumn[j].append( self.matchingScheme[i][j] )
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usedCapIdsPerColumn[j] = numpy.unique(usedCapIdsPerColumn[j])
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return usedCapIdsPerColumn
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def __findCapIdsToEliminatePerColumn__( self, usedCapIdsPerColumn ):
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capIdsToEliminatePerColumn = []
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for j in range(0, len(usedCapIdsPerColumn) ):
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if len(usedCapIdsPerColumn[j]) == self.capacitorsNumber:
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capIdsToEliminatePerColumn.append( [None] )
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else :
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capIdsToEliminatePerColumn.append( list (set(usedCapIdsPerColumn[j])^set(self.capacitorIds) ) )
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return capIdsToEliminatePerColumn
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def __findCapIdsToEliminate__( self, capIdsToEliminatePerColumn ):
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capIdsToEliminate = []
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capIdsj = capIdsToEliminatePerColumn[0]
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print('capIdsj',capIdsj)
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sharedVRTIds = self.capacitorIds[0:self.capacitorsNumber/2] if self.capacitorsNumber % 2 == 0 else self.capacitorIds[0: int(self.capacitorsNumber/2+1)]
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print('sharedVRTIds',sharedVRTIds)
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intersection2 = list( set(capIdsj).intersection(set(sharedVRTIds)) )
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capIdsToEliminate.append( [None] ) if intersection2 == [] else capIdsToEliminate.append( intersection2 )
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for j in range(0, len(capIdsToEliminatePerColumn) ):
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capIdsj = capIdsToEliminatePerColumn[j]
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if (j % 2 == 0):
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sharedVRTIds = self.capacitorIds[self.capacitorsNumber/2 : self.capacitorsNumber] if (self.capacitorsNumber % 2 == 0) else self.capacitorIds[int(self.capacitorsNumber/2+1) : self.capacitorsNumber]
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else:
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sharedVRTIds = self.capacitorIds[0:self.capacitorsNumber/2] if (self.capacitorsNumber % 2 == 0) else self.capacitorIds[0: int(self.capacitorsNumber/2+1)]
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print('sharedVRTIds',sharedVRTIds)
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if j == len(capIdsToEliminatePerColumn)-1:
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intersection1 = list( set(capIdsj) )
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else :
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capIdsjp1 = capIdsToEliminatePerColumn[j+1]
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intersection1 = list( set(capIdsj).intersection(set(capIdsjp1)) )
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intersection2 = list( set(intersection1).intersection(set(sharedVRTIds)) )
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capIdsToEliminate.append( [None] ) if intersection2 == [] else capIdsToEliminate.append( intersection2 )
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return capIdsToEliminate
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def __findVRTsToEliminate__( self, capIdsToEliminate ):
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print('capIdsToEliminate',capIdsToEliminate)
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for j in range( 0,len(self.vRTsDistribution) ) :
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for k in range( 0,len(self.vRTsDistribution[j]) ) :
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if k == 0 :
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if self.vRTsDistribution[j][0] in capIdsToEliminate[j] :
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self.vRTsToEliminate.append( [0] )
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self.vRTsToEliminate[j].append( 0 )
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else :
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self.vRTsToEliminate.append( [1] )
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self.vRTsToEliminate[j].append( 1 )
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print('vRTsToEliminate',self.vRTsToEliminate)
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else :
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if self.vRTsDistribution[j][k] in capIdsToEliminate[j]:
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[self.vRTsToEliminate[j].append( 0 ) for u in range(0,2)]
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else :
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[self.vRTsToEliminate[j].append( 1 ) for u in range(0,2)]
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return
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def minimizeVRTs( self ) :
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self.__setVRTsDistribution__()
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if self.minimizeVRT == False :
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for j in range( 0, self.matrixDim["columns"]+1 ) :
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self.vRTsToEliminate.append( [1] )
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self.vRTsToEliminate[j].append( 1 )
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for k in range( 0,len(self.vRTsDistribution[j]) ) :
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[self.vRTsToEliminate[j].append( 1 ) for u in range(0,2)]
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elif self.minimizeVRT == True :
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usedCapIdsPerColumn = self.__findUsedCapIdsPerColumn__ ()
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capIdsToEliminatePerColumn = self.__findCapIdsToEliminatePerColumn__(usedCapIdsPerColumn )
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capIdsToEliminate = self.__findCapIdsToEliminate__ (capIdsToEliminatePerColumn)
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self.__findVRTsToEliminate__ (capIdsToEliminate )
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print("self.matchingScheme" ,self.matchingScheme)
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print("usedCapIdsPerColumn" ,usedCapIdsPerColumn)
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print("capIdsToEliminatePerColumn",capIdsToEliminatePerColumn)
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print("capIdsToEliminate" ,capIdsToEliminate)
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print('self.vRTsToEliminate' ,self.vRTsToEliminate)
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else : raise Error(1,'minimizeVRTs() : ')
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return
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def __setVRTsDistribution__( self ):
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element = [ self.capacitorIds[0:self.capacitorsNumber/2], self.capacitorIds[self.capacitorsNumber/2:self.capacitorsNumber] ] if self.capacitorsNumber % 2 == 0 else [ self.capacitorIds[0:int( self.capacitorsNumber/2 + 1 )], self.capacitorIds[int( self.capacitorsNumber/2 + 1 ):self.capacitorsNumber] ]
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u = 0
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for j in range(0,self.matrixDim["columns"]+1) :
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self.vRTsDistribution.append( element[u] )
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u = u+1 if u < 1 else 0
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print('self.vRTsDistribution',self.vRTsDistribution)
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return
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def __setNetsDistribution__( self ):
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netsList = self.nets[0:len(self.nets)-1] if self.dummyRing == True and self.dummyElement == False else self.nets
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element = [ netsList[0:len(netsList)/2], netsList[len(netsList)/2:len(netsList)] ] if len(netsList) % 2 == 0 else [ netsList[0:int( len(netsList)/2 + 1 )], netsList[int( len(netsList)/2 + 1 ):len(netsList)] ]
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u = 0
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netsDistribution = []
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for j in range(0,self.matrixDim["columns"]+1) :
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netsDistribution.append( [element[u][0][0]] )
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netsDistribution[j].append( element[u][0][1] )
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for k in range(1,len(element[u])):
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netsDistribution[j].append( element[u][k][0] )
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netsDistribution[j].append( element[u][k][1] )
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u = u+1 if u < 1 else 0
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print('netsDistribution',netsDistribution)
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return netsDistribution
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def __setPlatesDistribution__( self ):
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element = [ self.capacitorIds[0:self.capacitorsNumber/2], self.capacitorIds[self.capacitorsNumber/2:self.capacitorsNumber] ] if self.capacitorsNumber % 2 == 0 else [ self.capacitorIds[0:int( self.capacitorsNumber/2 + 1 )], self.capacitorIds[int( self.capacitorsNumber/2 + 1 ):self.capacitorsNumber] ]
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u = 0
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for j in range(0,self.matrixDim["columns"]+1) :
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print("j",j)
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self.platesDistribution.append( ['t' + str(element[u][0])] )
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print('self.platesDistribution',self.platesDistribution)
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if self.dummyElement == False or self.dummyElement == True and j % 2 == 0 and len(element[u]) > 1 :
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print("jif",j)
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self.platesDistribution[j].append( 'b' + str(element[u][0]) )
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for k in element[u][1:len(element[u])]:
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print('k',k)
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self.platesDistribution[j].append( 't' + str(k) )
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print("jj",j)
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if self.dummyElement == False or self.dummyElement == True and j % 2 == 0 or self.dummyElement == True and j % 2 != 0 and k != element[u][len(element[u])-1] :
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self.platesDistribution[j].append( 'b' + str(k) )
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u = u+1 if u < 1 else 0
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print('self.platesDistribution',self.platesDistribution)
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return
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def gethRoutingTrack_width ( self ) : return self.hRoutingTrack_width
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def getvRoutingTrackXCenter ( self ) : return self.vRoutingTrackXCenter
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def ScriptMain( **kw ):
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editor = None
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if kw.has_key('editor') and kw['editor']:
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editor = kw['editor']
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UpdateSession.open()
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Device = AllianceFramework.get().createCell( 'capacitor' )
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Device.setTerminal( True )
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bottomPlate_net0 = Net.create( Device, 'b0' )
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bottomPlate_net1 = Net.create( Device, 'b1' )
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bottomPlate_net2 = Net.create( Device, 'b2' )
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bottomPlate_net3 = Net.create( Device, 'b3' )
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bottomPlate_net0.setExternal( True )
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bottomPlate_net1.setExternal( True )
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bottomPlate_net2.setExternal( True )
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bottomPlate_net3.setExternal( True )
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b0 = Device.getNet("b0")
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b1 = Device.getNet("b1")
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b2 = Device.getNet("b2")
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b3 = Device.getNet("b3")
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topPlate_net0 = Net.create( Device, 't0' )
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topPlate_net1 = Net.create( Device, 't1' )
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topPlate_net2 = Net.create( Device, 't2' )
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topPlate_net3 = Net.create( Device, 't3' )
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topPlate_net0.setExternal( True )
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topPlate_net1.setExternal( True )
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topPlate_net2.setExternal( True )
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topPlate_net3.setExternal( True )
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t0 = Device.getNet("t0")
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t1 = Device.getNet("t1")
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t2 = Device.getNet("t2")
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t3 = Device.getNet("t3")
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if editor:
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UpdateSession.close()
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editor.setCell( Device )
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editor.fit()
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UpdateSession.open()
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nets = [[t0, b0] , [t1, b1] , [t2, b2] ] # [t3, b3] ]
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#capacitorInstance = CapacitorStack( Device, capacitance, 'MIMCap', [0,0], nets, unitCap = 93, matchingMode = True, matchingScheme = [ ['C2','C2','C2','C2'] , ['C1','C2','C2','C2'] , ['C1','C2','C2','C2'] , ['C1','C2','C2','C1'] ] )
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capacitorInstance = CapacitorStack( Device, [372,1116], 'MIMCap', [0,0], nets,unitCap = 93, matrixDim = [4,4], matchingMode = True, matchingScheme = [ [1,1,1,0] , [0,1,1,1] , [1,1,1,0] , [0,1,1,1]], dummyRing = True)
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# capacitorInstance = CapacitorStack( Device, [372,1116], 'MIMCap', [0,0], nets,unitCap = 93, matrixDim = [4,4], matchingMode = True, matchingScheme = [ [1,1,1,0] , [0,1,1,1] , [1,1,1,0] , [0,1,1,1] ], dummyRing = True)
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# capacitorInstance = CapacitorStack( Device, [279], 'MIMCap', [0,0], nets, unitCap = 279 ) #, matrixDim = [4,4], matchingMode = True, matchingScheme = [ [1,1,1,0] , [0,1,2,1] , [1,1,1,0] , [2,1,1,1] ], dummyElement = True )#dummyRing = True)
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# capacitorInstance = CapacitorStack( Device, [279,1023, 186], 'MIMCap', [0,0], nets, unitCap = 93, matrixDim = [4,4], matchingMode = True, matchingScheme = [ [1,1,1,0] , [0,1,2,1] , [1,1,1,0] , [2,1,1,1] ], dummyElement = True )#dummyRing = True)
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# capacitorInstance = CapacitorStack( Device, capacitance, 'MIMCap', [0,0], nets, unitCap = 93, matchingMode = True, matchingScheme = [ ['C2','C2','C1','C2'] , ['C1','C2','C2','C1'] , ['C1','C1','C2','C3'] , ['C1','C1','C2','C3'] ] )
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# capacitorInstance = CapacitorStack( Device, capacitance, 'MIMCap', [0,0], nets, unitCap = 93, matchingMode = True, matchingScheme = [ ['C1','C4','C1','C2'] , ['C1','C2','C4','C1'] , ['C3','C1','C4','C3'] , ['C3','C1','C2','C3'] ] )
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capacitor = capacitorInstance.create( )
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capWithVRT = VerticalRoutingTracks( capacitorInstance, capacitor, True ) # )
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capWithVRT.create()
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AllianceFramework.get().saveCell( Device, Catalog.State.Views )
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return True
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