121 lines
2.3 KiB
Plaintext
121 lines
2.3 KiB
Plaintext
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-- =======================================================================
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-- Coriolis Structural VHDL Driver
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-- Generated on Jul 11, 2018, 11:23
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--
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-- To be interoperable with Alliance, it uses it's special VHDL subset.
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-- ("man vhdl" under Alliance for more informations)
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-- =======================================================================
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entity fulladder is
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port ( a : linkage bit
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; b : linkage bit
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; cin : linkage bit
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; cout : linkage bit
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; sout : linkage bit
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; vdd : linkage bit
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; vss : linkage bit
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);
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end fulladder;
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architecture structural of fulladder is
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component xr2_x1
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port ( i0 : in bit
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; i1 : in bit
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; q : out bit
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; vdd : in bit
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; vss : in bit
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);
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end component;
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component a2_x2
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port ( i0 : in bit
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; i1 : in bit
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; q : out bit
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; vdd : in bit
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; vss : in bit
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);
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end component;
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component o2_x2
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port ( i0 : in bit
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; i1 : in bit
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; q : out bit
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; vdd : in bit
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; vss : in bit
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);
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end component;
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component tie_x0
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port ( vdd : in bit
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; vss : in bit
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);
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end component;
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component rowend_x0
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port ( vdd : in bit
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; vss : in bit
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);
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end component;
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signal carry_1 : bit;
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signal carry_2 : bit;
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signal sout_1 : bit;
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begin
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filler_2 : rowend_x0
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port map ( vdd => vdd
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, vss => vss
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);
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filler_1 : tie_x0
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port map ( vdd => vdd
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, vss => vss
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);
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o2_1 : o2_x2
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port map ( i0 => carry_2
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, i1 => carry_1
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, q => cout
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, vdd => vdd
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, vss => vss
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);
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xr2_2 : xr2_x1
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port map ( i0 => cin
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, i1 => sout_1
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, q => sout
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, vdd => vdd
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, vss => vss
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);
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xr2_1 : xr2_x1
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port map ( i0 => a
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, i1 => b
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, q => sout_1
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, vdd => vdd
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, vss => vss
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);
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a2_2 : a2_x2
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port map ( i0 => cin
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, i1 => sout_1
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, q => carry_2
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, vdd => vdd
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, vss => vss
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);
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a2_1 : a2_x2
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port map ( i0 => a
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, i1 => b
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, q => carry_1
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, vdd => vdd
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, vss => vss
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);
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end structural;
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