coriolis/crlcore
Jean-Paul Chaput bbcf14eb5a First step in supporting ISPD18 detailed routing benchmarks.
* Change: In CRL::DefImport, added callback to read the DEF UNITS statement
    and perform a correct length conversion. Previously set to read pseudo
    lambdas in hundredth of microns.
      Added DefParser::getLefCell() to lookup master cells in the LEF
    libraries before looking in the Alliance ones (rooted under "LEF"
    library).
* Change: In CRL::LefParser::_pinPostProcess(), when no segment suitable
    for terminal connexion is found, add all of them. This is a quick hack
    and an a correct policy that match all techno must be implemeneted.
* New: In CRL::pyCRL, add a Python wrapper for DefImport.
* New: In CRL/etc/45/ispd18/ added configuration files for the "real"
    technology used by the ISPD18 45nm design benchmarks.
2019-03-29 11:07:55 +01:00
..
cmake_modules New Library Manager Widget. Access with Tools menu or CTRL+M. 2015-05-09 17:03:17 +02:00
doc Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
etc First step in supporting ISPD18 detailed routing benchmarks. 2019-03-29 11:07:55 +01:00
python Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
src First step in supporting ISPD18 detailed routing benchmarks. 2019-03-29 11:07:55 +01:00
CMakeLists.txt Add a fully generated documentation in the git repository. 2018-06-06 18:42:26 +02:00