227 lines
3.8 KiB
Plaintext
227 lines
3.8 KiB
Plaintext
entity muxs is
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port (
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alu_out : in bit_vector(3 downto 0);
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i : in bit_vector(2 downto 0);
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noe : in bit;
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oe : out bit;
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ra : in bit_vector(3 downto 0);
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shift_l : out bit;
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shift_r : out bit;
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vdd : in bit;
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vss : in bit;
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y : out mux_vector(3 downto 0) bus
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);
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end muxs;
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architecture structural of muxs is
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Component o3_x2
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component inv_x2
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port (
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i : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component an12_x1
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component a2_x2
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component buf_x2
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port (
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i : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component nmx2_x1
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port (
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cmd : in bit;
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i0 : in bit;
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i1 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component nts_x1
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port (
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cmd : in bit;
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i : in bit;
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nq : out mux_bit bus;
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vdd : in bit;
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vss : in bit
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);
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end component;
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signal not_noe : bit;
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signal not_aux1 : bit;
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signal nmx2_x1_sig : bit;
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signal nmx2_x1_4_sig : bit;
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signal nmx2_x1_3_sig : bit;
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signal nmx2_x1_2_sig : bit;
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signal inv_x2_sig : bit;
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begin
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inv_x2_ins : inv_x2
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port map (
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i => i(1),
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nq => inv_x2_sig,
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vdd => vdd,
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vss => vss
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);
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not_aux1_ins : o3_x2
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port map (
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i0 => i(0),
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i1 => i(2),
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i2 => inv_x2_sig,
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q => not_aux1,
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vdd => vdd,
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vss => vss
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);
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not_noe_ins : inv_x2
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port map (
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i => noe,
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nq => not_noe,
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vdd => vdd,
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vss => vss
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);
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shift_r_ins : an12_x1
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port map (
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i0 => i(1),
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i1 => i(2),
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q => shift_r,
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vdd => vdd,
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vss => vss
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);
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shift_l_ins : a2_x2
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port map (
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i0 => i(2),
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i1 => i(1),
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q => shift_l,
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vdd => vdd,
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vss => vss
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);
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oe_ins : buf_x2
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port map (
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i => not_noe,
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q => oe,
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vdd => vdd,
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vss => vss
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);
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nmx2_x1_ins : nmx2_x1
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port map (
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cmd => not_aux1,
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i0 => ra(0),
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i1 => alu_out(0),
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nq => nmx2_x1_sig,
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vdd => vdd,
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vss => vss
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);
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y_0_ins : nts_x1
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port map (
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cmd => not_noe,
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i => nmx2_x1_sig,
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nq => y(0),
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vdd => vdd,
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vss => vss
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);
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nmx2_x1_2_ins : nmx2_x1
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port map (
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cmd => not_aux1,
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i0 => ra(1),
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i1 => alu_out(1),
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nq => nmx2_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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y_1_ins : nts_x1
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port map (
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cmd => not_noe,
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i => nmx2_x1_2_sig,
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nq => y(1),
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vdd => vdd,
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vss => vss
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);
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nmx2_x1_3_ins : nmx2_x1
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port map (
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cmd => not_aux1,
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i0 => ra(2),
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i1 => alu_out(2),
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nq => nmx2_x1_3_sig,
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vdd => vdd,
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vss => vss
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);
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y_2_ins : nts_x1
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port map (
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cmd => not_noe,
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i => nmx2_x1_3_sig,
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nq => y(2),
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vdd => vdd,
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vss => vss
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);
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nmx2_x1_4_ins : nmx2_x1
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port map (
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cmd => not_aux1,
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i0 => ra(3),
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i1 => alu_out(3),
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nq => nmx2_x1_4_sig,
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vdd => vdd,
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vss => vss
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);
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y_3_ins : nts_x1
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port map (
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cmd => not_noe,
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i => nmx2_x1_4_sig,
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nq => y(3),
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vdd => vdd,
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vss => vss
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);
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end structural;
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