coriolis/cumulus
Jean-Paul Chaput f5020120bf Correct clock-tree building when used on a standalone block.
* Change: In Cumulus, in Configuration.py, in the horizontal & vertical
    wire creation adds new flags ExpandWidth to draw wires one lambda
    bigger than the minimal width (see ClockTree.py patch).
* Change: In Cumulus, In ClockTree.py, use non default width to draw
    wires of the H branch of the clock tree. This is to prevent them
    to be recognized as "manual global routing", which they are not
    and not event topologically compatible.
* Bug: In Kite, in BuildPowerRails, change the way clocks are detected
    when working on a single block (not a whole chip). Now look only
    in clock which are external and do not filter out already routed
    ones.
* Change: In KiteEngine, in createGlobalGraph(), systematically call
    flattenNets() so nets that are added after the first flattening
    in the placer are also flattened. The flattenNets() Cell method
    takes care of not flattening twice a net.
2015-03-03 11:11:22 +01:00
..
src Correct clock-tree building when used on a standalone block. 2015-03-03 11:11:22 +01:00
CMakeLists.txt Starting to implement support for Windows/Cygwin. 2014-07-13 13:14:49 +02:00