123 lines
3.7 KiB
Python
123 lines
3.7 KiB
Python
#!/usr/bin/python
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# This file is part of the Coriolis Project.
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# Copyright (C) Laboratoire LIP6 - Departement ASIM
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# Universite Pierre et Marie Curie
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#
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# Main contributors :
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# Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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# Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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# Hugo Clement <Hugo.Clement@lip6.fr>
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# Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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# Damien Dupuis <Damien.Dupuis@lip6.fr>
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# Christian Masson <Christian.Masson@lip6.fr>
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# Marek Sroka <Marek.Sroka@lip6.fr>
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#
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# The Coriolis Project is free software; you can redistribute it
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# and/or modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# The Coriolis Project is distributed in the hope that it will be
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# useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with the Coriolis Project; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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#
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# License-Tag
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# Authors-Tag
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# ===================================================================
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#
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# x-----------------------------------------------------------------x
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# | |
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./util_Defs.py" |
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# | *************************************************************** |
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# | U p d a t e s |
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# | |
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# x-----------------------------------------------------------------x
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from st_placement import Place, NOSYM, SYM_Y, FIXED
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from st_ref import XY
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from util_Gen import F_MSB_FIRST
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Y_SLICE = 50
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# for DpgenAdder
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F_ADDER_CIN = 0x00000001
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F_ADDER_SIGN = 0x00000002
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F_ADDER_OVER = 0x00000004
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################
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## slice_to_y ##
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################
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def slice_to_y ( s ) :
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return s * Y_SLICE
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##################
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## slice_to_sym ##
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##################
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def slice_to_sym ( s ) :
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if s % 2 : return SYM_Y
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else : return NOSYM
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##################
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## slice_to_bit ##
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##################
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def slice_to_bit ( s, N, m ) :
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if m : m = N - 1 - s
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else : m = s
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return m
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####################
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## dpgen_port_bit ##
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####################
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def dpgen_port_bit ( n, flags, s ) :
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return slice_to_bit ( s
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, n
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, flags & F_MSB_FIRST
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)
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#################
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## dpgen_place ##
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#################
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def dpgen_place ( Ins, x, y, plac = FIXED ) :
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sym = NOSYM
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if ( y / 50 ) % 2 : sym = SYM_Y
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Place ( Ins, sym, XY ( x, y ), plac )
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###################
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## VHDL_BUS_WIDE ##
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###################
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def VHDL_BUS_WIDE ( msb, lsb, n, flags ) :
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if flags & F_MSB_FIRST : temp = "to"
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else : temp = "downto"
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bus = "(%ld %s %ld)" % ( dpgen_port_bit ( n, flags, msb )
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, temp
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, dpgen_port_bit ( n, flags, lsb )
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)
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return bus
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