coriolis/crlcore/etc/symbolic
Jean-Paul Chaput 82dc58bf8e Redesign of I/O pads and Corona support to mix real and symbolic.
* Bug: In CRL/etc/symbolic/cmos/plugins.conf, rails dimensions are no
    longer expressed directly in lambda. Must be created using helper.l().
* Change: In CRL::ApParser, slightly more smart management of Pin width.
    Must normalize Pin behavior between Alliance & Hurricane as in
    Alliance they have only one dimension.
* Change: In CRL::LefImport, if a net name end with "!", assume it's a
    global one. Have to check this naming convention.
* Change: In Anabatic::NetBuilderHV::_do_1G_1PinM3() & _do_1G_1PinM2()
    now implemented. Needed for the corona routing support.
* Change: In AnabaticEngine::setupPreRouted(), exclude segments outside
    the abutment box.
* Change: In KatanaEngine::PowerRails, remove the I/O pad support as now
    we route only inside the Corona. So only one vdd/vss/ck are supported.
* New: In cumulus/plugins/ChipPlugin.py, complete rewrite of the chip
    support:
    * Uncouple pad I/O ring whith real cells (foundry) from a symbolic
      core. A new intermediate level "corona" is introduced to handle
      the real/symbolic transition.
    * Ability to explicitly setup position of the pads on the chip side
      in case of uneven distribution.
    * Enable clock tree to be build with 3 metal only (M2 to M4) instead
      of (M2 to M5).
2019-05-10 11:58:05 +02:00
..
cmos Redesign of I/O pads and Corona support to mix real and symbolic. 2019-05-10 11:58:05 +02:00
cmos45 Reorganisation of menus in a more clear way. 2019-03-05 23:23:14 +01:00
ispd05 ISPD05 loading speed issues. IO PAD support for LEF importation. 2019-04-22 12:16:16 +02:00
vsc200 Corrections in the Dijkstra global routing (ripup) mechanism. 2018-04-16 12:10:48 +02:00