97 lines
3.3 KiB
Python
97 lines
3.3 KiB
Python
from OPENCHAMS import *
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circuit = Circuit(Name("design"), Name("myTech"))
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# value parameters
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circuit.addParameter(Name("temp"), 27.0 )
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circuit.addParameter(Name("Vdd") , 1.2 )
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circuit.addParameter(Name("Vss") , 0.0 )
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circuit.addParameter(Name("L") , 0.1e-6)
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circuit.addParameter(Name("Ids") , 30e-6 )
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circuit.addParameter(Name("Veg") , 0.12 )
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# equation parameters
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circuit.addParameter(Name("complex"), "myEq")
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# netlist :
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netlist = circuit.createNetlist()
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# instances
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# nmos1
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inst_nmos1 = netlist.addDevice("nmos1", "Transistor", 1, "NMOS", True)
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inst_nmos1.addConnector("G")
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inst_nmos1.addConnector("S")
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inst_nmos1.addConnector("D")
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tr_nmos1 = inst_nmos1.addTransistor("m1")
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tr_nmos1.gate = "G" # the name of the connector of inst_nmos1
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tr_nmos1.source = "S"
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tr_nmos1.drain = "D"
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tr_nmos1.bulk = "S"
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# pmos1
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inst_pmos1 = netlist.addDevice("pmos1", "Transistor", 2, "PMOS", True)
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inst_pmos1.addConnector("G")
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inst_pmos1.addConnector("S")
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inst_pmos1.addConnector("D")
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tr_pmos1 = inst_pmos1.addTransistor("m1")
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tr_pmos1.gate = "G" # the name of the connector of inst_pmos1
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tr_pmos1.source = "S"
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tr_pmos1.drain = "D"
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tr_pmos1.bulk = "S"
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# nets
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_vdd = netlist.addNet("vdd", "power" , True)
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_vss = netlist.addNet("vss", "ground" , True)
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_in = netlist.addNet("in" , "logical", True)
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_out = netlist.addNet("out", "logical", True)
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_vdd.connectTo("pmos1", "S")
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_vss.connectTo("nmos1", "S")
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_in.connectTo ("nmos1", "G")
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_in.connectTo ("pmos1", "G")
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_out.connectTo("nmos1", "D")
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_out.connectTo("pmos1", "D")
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# schematic
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schematic = circuit.createSchematic()
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schematic.addInstance("nmos1", 2490, 2600, "ID")
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schematic.addInstance("pmos1", 2490, 2300, "ID")
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_vdd.addPort("inV" , 0, 2490, 2100, "ID")
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_vss.addPort("inV" , 0, 2490, 2800, "MY")
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_in.addPort ("inH" , 0, 2190, 2500, "ID")
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_out.addPort("outH", 0, 2600, 2500, "ID")
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wireVdd = _vdd.addWire()
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wireVdd.setStartPoint("pmos1", "S")
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wireVdd.setEndPoint(0)
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wireVss = _vss.addWire()
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wireVss.setStartPoint("nmos1", "S")
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wireVss.setEndPoint(0)
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wireIn0 = _in.addWire()
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wireIn1 = _in.addWire()
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wireIn0.setStartPoint("pmos1", "G")
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wireIn0.setEndPoint ("nmos1", "G")
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wireIn1.setStartPoint(0)
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wireIn1.setEndPoint ("pmos1", "G")
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wireOut0 = _out.addWire()
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wireOut1 = _out.addWire()
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wireOut0.setStartPoint("pmos1", "D")
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wireOut0.setEndPoint ("nmos1", "D")
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wireOut1.setStartPoint("nmos1", "D")
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wireOut1.setEndPoint (0)
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# sizing
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sizing = circuit.createSizing()
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op_pmos1 = sizing.addOperator("pmos1", "OPVG(Veg)" , "BSIM3V3")
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op_pmos1.addConstraint("Temp", "design", "temp")
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op_pmos1.addConstraint("Ids" , "design", "Ids" )
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op_pmos1.addConstraint("L" , "design", "L" )
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op_pmos1.addConstraint("Veg" , "design", "Veg" )
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op_pmos1.addConstraint("Vd" , "design", "Vdd", 0.5)
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op_pmos1.addConstraint("Vs" , "design", "Vdd" )
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op_nmos1 = sizing.addOperator("nmos1", "OPW(Vg,Vs)", "BSIM3V3")
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op_nmos1.addConstraint("Temp", "design", "temp")
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op_nmos1.addConstraint("Ids" , "design", "Ids" )
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op_nmos1.addConstraint("L" , "design", "L" )
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op_nmos1.addConstraint("Vs" , "design", "Vdd" )
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op_nmos1.addConstraint("Vg" , "pmos1" , "Vg" )
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op_nmos1.addConstraint("Vd" , "pmos1" , "Vd" )
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op_nmos1.addConstraint("another", "myEq", -2.5 )
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# layout
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layout = circuit.createLayout()
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layout.addInstance("pmos1", "Common transistor")
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layout.addInstance("nmos1", "Rotate transistor")
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circuit.writeToFile("./myInverter.xml")
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