coriolis/crlcore/etc/alliance.conf

57 lines
2.4 KiB
Python

# -*- Mode:Python -*-
cellsTop = '/soc/alliance/cells/'
allianceConfig = \
( ( 'SYMBOLIC_TECHNOLOGY', helpers.sysConfDir+'/technology.symbolic.xml' )
, ( 'REAL_TECHNOLOGY' , helpers.sysConfDir+'/technology.cmos130.s2r.xml')
, ( 'DISPLAY' , helpers.sysConfDir+'/display.xml' )
, ( 'CATALOG' , 'CATAL')
, ( 'WORKING_LIBRARY' , '.')
, ( 'SYSTEM_LIBRARY' , ( (cellsTop+'sxlib' , Environment.Append)
, (cellsTop+'dp_sxlib', Environment.Append)
, (cellsTop+'ramlib' , Environment.Append)
, (cellsTop+'romlib' , Environment.Append)
, (cellsTop+'rflib' , Environment.Append)
, (cellsTop+'rf2lib' , Environment.Append)
, (cellsTop+'pxlib' , Environment.Append) ) )
, ( 'SCALE_X' , 100)
, ( 'IN_LO' , 'vst')
, ( 'IN_PH' , 'ap')
, ( 'OUT_LO' , 'vst')
, ( 'OUT_PH' , 'ap')
, ( 'POWER' , 'vdd')
, ( 'GROUND' , 'vss')
, ( 'CLOCK' , '^ck.*')
, ( 'BLOCKAGE' , '^blockageNet*')
)
# Format of routingGaugesTable (dictionary):
# A list of entry of the form:
# ( METAL_NAME, (Direction, Type, depth, density, offset, pitch, wire_width, via_width) )
routingGaugesTable = {}
routingGaugesTable['sxlib'] = \
( ( 'METAL1', ( RoutingLayerGauge.Vertical , RoutingLayerGauge.PinOnly, 0, 0.0, 0, 5, 2, 3 ) )
, ( 'METAL2', ( RoutingLayerGauge.Horizontal, RoutingLayerGauge.Default, 1, 7.0, 0, 5, 2, 3 ) )
, ( 'METAL3', ( RoutingLayerGauge.Vertical , RoutingLayerGauge.Default, 2, 0.0, 0, 5, 2, 3 ) )
, ( 'METAL4', ( RoutingLayerGauge.Horizontal, RoutingLayerGauge.Default, 3, 0.0, 0, 5, 2, 3 ) )
, ( 'METAL5', ( RoutingLayerGauge.Vertical , RoutingLayerGauge.Default, 4, 0.0, 0, 5, 2, 3 ) )
#, ( 'METAL6', ( RoutingLayerGauge.Horizontal, RoutingLayerGauge.Default, 5, 0.0, 0, 5, 2, 3 ) )
#, ( 'METAL7', ( RoutingLayerGauge.Vertical , RoutingLayerGauge.Default, 6, 0.0, 0, 5, 2, 3 ) )
)
# Format of cellGaugesTable (dictionary):
# A list of entry of the form:
# ( METAL_PIN, xy_common_pitch, slice_height, slice_step )
cellGaugesTable = {}
cellGaugesTable['sxlib'] = ('metal2', 5.0, 50.0, 5.0)