55 lines
1.9 KiB
TeX
55 lines
1.9 KiB
TeX
\begin{itemize}
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\item Name : DpgenShift -- Shifter Macro-Generator
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\item Description : Generates a \verb-n- bits shifter named \verb-modelname-.
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\item How it works :
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\begin{itemize}
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\item if the \verb-op[0]- signal is set to \verb-one-, performs a right shift, performs a left shift otherwise.
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\item if the \verb-op[1]- signal is set to \verb-one-, performs an arithmetic shift (only meaningful in case of a right shift).
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\item \verb-shamt- specifies the shift amount. The width of this signal (\verb-Y-) is computed from the operator's width : \verb-Y = ceil(log2(n)) -- 1
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\end{itemize}
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\item Terminal Names :
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\begin{itemize}
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\item op : select the kind of shift (input, 2 bits)
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\item shamt : the shift amount (input, \verb-Y- bits)
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\item i : value to shift (input, \verb-n- bits)
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\item o : output (\verb-n- bits)
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\item vdd : power
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\item vss : ground
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\end{itemize}
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\item Parameters : Parameters are given with a map called \verb-param-.
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\begin{itemize}
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\item nbit : Defines the size of the generator
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\end{itemize}
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% \item Behavior :
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%\begin{verbatim}
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%\end{verbatim}
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\item Example :
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\begin{verbatim}
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class myClass ( Model ) :
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def Interface ( self ) :
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self._instop = LogicIn ( "instop", 2 )
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self._instshamt = LogicIn ( "instshamt", 2 )
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self._insti = LogicIn ( "insti", 4 )
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self._insto = LogicOut ( "insto", 4 )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Inst ( 'DpgenShifter'
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, param = { 'nbit' : 4 }
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, map = { 'op' : self._instop
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, 'shamt' : self._instshamt
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, 'i' : self._insti
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, 'o' : self._insto
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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\end{verbatim}
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\end{itemize}
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