59 lines
2.2 KiB
TeX
59 lines
2.2 KiB
TeX
\begin{itemize}
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\item Name : DpgenSfft -- Static Flip-Flop with Scan-Path Macro-Generator
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\item Description : Generates a n bits static flip-flop with scan-path named \verb-modelname-. The two latches of this flip-flop are static i.e. each one is made of two interters looped togethers.
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\item How it works :
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\begin{itemize}
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\item scan : when set to \verb-one- enables the scan-path mode. Note that in scan-path mode, the wen signal is not effective
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\item scin : the input of the scan-path. This terminal is different from \verb-i0[0]-. The scout is verb-q[N-i1] (in the following example this is \verb-q[31]-)
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\item when wen is set to \verb-one- enables the writing of the flip-flop
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\end{itemize}
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\item Terminal Names :
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\begin{itemize}
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\item scan : scan-path mode (input, 1 bit)
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\item scin : scan path in (input, 1 bit)
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\item wen : write enable (1 bit)
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\item ck : clock signal (1 bit)
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\item i0 : data input (\verb-n- bits)
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\item q : output (\verb-n- bits)
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\item vdd : power
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\item vss : ground
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\end{itemize}
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\item Parameters : Parameters are given with a map called \verb-param-.
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\begin{itemize}
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\item nbit : Defines the size of the generator
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\end{itemize}
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% \item Behavior :
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% \begin{verbatim}
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% \end{verbatim}
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\item Example :
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\begin{verbatim}
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class myClass ( Model ) :
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def Interface ( self ) :
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self._scan = LogicIn ( "scin", 1 )
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self._scin = LogicIn ( "scan", 1 )
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self._ck = LogicIn ( "ck", 1 )
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self._wen = LogicIn ( "wen", 1 )
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self._in = LogicIn ( "in", 4 )
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self._out = LogicOut ( "out", 4 )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Inst ( 'DpgenSfft'
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, param = { 'nbit' : 4 }
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, map = { "wen" : self._wen
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, "ck" : self._ck
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, "scan" : self._scan
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, "scin" : self._scin
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, "i0" : self._in
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, "q" : self._out
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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\end{verbatim}
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\end{itemize}
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