938 lines
32 KiB
Python
938 lines
32 KiB
Python
#!/usr/bin/python
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# This file is part of the Coriolis Project.
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# Copyright (C) Laboratoire LIP6 - Departement ASIM
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# Universite Pierre et Marie Curie
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#
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# Main contributors :
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# Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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# Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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# Hugo Clement <Hugo.Clement@lip6.fr>
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# Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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# Damien Dupuis <Damien.Dupuis@lip6.fr>
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# Christian Masson <Christian.Masson@lip6.fr>
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# Marek Sroka <Marek.Sroka@lip6.fr>
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#
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# The Coriolis Project is free software; you can redistribute it
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# and/or modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# The Coriolis Project is distributed in the hope that it will be
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# useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with the Coriolis Project; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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#
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# License-Tag
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# Authors-Tag
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# ===================================================================
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#
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# x-----------------------------------------------------------------x
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# | |
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./dpgen_ROM.py" |
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# | *************************************************************** |
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# | U p d a t e s |
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# | |
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# x-----------------------------------------------------------------x
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from stratus import *
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# Le nombre de mots peut prendre cinq valeurs : 64, 128, 256, 512, 1024
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# Le nombre de bits est un multiple de 4 et doit etre inferieur ou egal a 64
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# On peut avoir une sortie tri-state en option (pour construire des ROMs
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# de capacite superieure a 1024 mots.
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# La largeur est egale a ( nmot / 64 * 50) + 150 (+ 20 si option tristate)
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# La hauteur est egale a ( nbit + 8) * 50 pour 64 ou 128 mots
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# ( nbit + 9) * 50 pour 256, 512 ou 1024 mots
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#
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# Les valeurs a encoder dans la ROM sont recuperees dans le tableau data[2048]
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# qui contient des "mots" de 32 bits : une valeur est stockee dans deux cases
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# consecutives de ce tableau, ce qui permet d'avoir des mots de 64 bits.
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# Les poids faibles de la valeur i sont a l'adresse data[2*i]
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# Les poids forts de la valeur i sont a l'adresse data[2*i+1]
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#
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# Les lignes de bit horizontales en ALU2 sont hors grilles et pre-routees
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# la ROM respecte le gabarit SXLIB pour ce qui concerne les caissons et les
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# alimentations en ALU1 sur les faces est et ouest, mais il n'y a pas
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# de continuite des alimentations en ALU1 dans la zone data.
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# Pour la partie "donnees", on utilise les cellules suivantes :
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# - rom_data_invss
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# - rom_data_insel
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# - rom_data_midvss
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# - rom_data_midsel
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# - rom_data_outvss
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# - rom_data_outsel
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# - rom_data_outvss_ts
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# - rom_data_outsel_ts
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#
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# Pour le decodeur, on utilise les cellules suivantes :
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# - rom_dec_adbuf
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# - rom_dec_nop
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# - rom_dec_prech
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# - rom_dec_col2
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# - rom_dec_col3
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# - rom_dec_col4
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# - rom_dec_colbuf
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# - rom_dec_line01
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# - rom_dec_line23
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# - rom_dec_line45
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# - rom_dec_line67
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# - rom_dec_selmux01
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# - rom_dec_selmux23
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# - rom_dec_selmux45
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# - rom_dec_selmux67
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# - rom_dec_selmux67_128
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# - rom_dec_selmux01_ts
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# - rom_dec_selmux23_ts
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# - rom_dec_selmux45_ts
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# - rom_dec_selmux67_ts
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# - rom_dec_selmux67_128_ts
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class TopRom ( Model ) :
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def Interface ( self ) :
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self.nbit = self._param['nbit']
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self.nword = self._param['nword']
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if self.nword == 64 : adrange = 6
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elif self.nword == 128 : adrange = 7
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elif self.nword == 256 : adrange = 8
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elif self.nword == 512 : adrange = 9
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elif self.nword == 1024 : adrange = 10
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else :
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print "Error : DPGEN_ROM"
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print "The word number (nword := %d) ", nword, "can only takes values : 64, 128, 256, 512 or 1024.\n"
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sys.exit ( 3 )
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if self.nbit % 4 != 0 or self.nbit > 64 or self.nbit < 4 :
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raise "\n[Stratus ERROR] DPGEN_ROM : The bus width (nbit := %d) ", nbit, "must be multiple of 4 and no larger than 64.\n"
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self.ck = SignalIn ( "ck", 1 )
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self.selrom = SignalIn ( "selrom", 1 )
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self.ad = SignalIn ( "ad", adrange )
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self.data = SignalOut ( "data", self.nbit )
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self.vdd = VddIn ( "vdd" )
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self.vss = VssIn ( "vss" )
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def Netlist ( self, type ) :
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### Acquisition du tableau des valeurs a encoder ###
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# ICI IL FAUT APPELER LE PARSER
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# for(i=0 ; i<1024 ; i++) {
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# data[2*i] = i;
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# data[2*i+1] = 1024 - i;
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# }
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# dpgen_ROM_code ( LV_name, self.nbit, self.nword, 0, 0, data )
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# Signaux internes
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nck = Signal ( "nck", 1 )
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prech = Signal ( "prech", 1 )
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nprech = Signal ( "nprech", 1 )
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mux0 = Signal ( "mux0", 1 )
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mux1 = Signal ( "mux1", 1 )
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mux2 = Signal ( "mux2", 1 )
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mux3 = Signal ( "mux3", 1 )
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mux4 = Signal ( "mux4", 1 )
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mux5 = Signal ( "mux5", 1 )
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mux6 = Signal ( "mux6", 1 )
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mux7 = Signal ( "mux7", 1 )
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sel0 = Signal ( "sel0", 1 )
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sel1 = Signal ( "sel1", 1 )
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sel2 = Signal ( "sel2", 1 )
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sel3 = Signal ( "sel3", 1 )
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sel4 = Signal ( "sel4", 1 )
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sel5 = Signal ( "sel5", 1 )
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sel6 = Signal ( "sel6", 1 )
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sel7 = Signal ( "sel7", 1 )
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bit0 = Signal ( "bit0", self.nbit )
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bit1 = Signal ( "bit1", self.nbit )
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bit2 = Signal ( "bit2", self.nbit )
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bit3 = Signal ( "bit3", self.nbit )
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bit4 = Signal ( "bit4", self.nbit )
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bit5 = Signal ( "bit5", self.nbit )
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bit6 = Signal ( "bit6", self.nbit )
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bit7 = Signal ( "bit7", self.nbit )
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line0 = Signal ( "line0", self.nbit )
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line1 = Signal ( "line1", self.nbit )
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line2 = Signal ( "line2", self.nbit )
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line3 = Signal ( "line3", self.nbit )
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line4 = Signal ( "line4", self.nbit )
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line5 = Signal ( "line5", self.nbit )
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line6 = Signal ( "line6", self.nbit )
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line7 = Signal ( "line7", self.nbit )
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mux0 = Signal ( "mux0", 1 )
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mux1 = Signal ( "mux1", 1 )
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mux2 = Signal ( "mux2", 1 )
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mux3 = Signal ( "mux3", 1 )
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mux4 = Signal ( "mux4", 1 )
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mux5 = Signal ( "mux5", 1 )
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mux6 = Signal ( "mux6", 1 )
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mux7 = Signal ( "mux7", 1 )
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a0 = Signal ( "a0", 1 )
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na0 = Signal ( "na0", 1 )
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a1 = Signal ( "a1", 1 )
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na1 = Signal ( "na1", 1 )
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a2 = Signal ( "a2", 1 )
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na2 = Signal ( "na2", 1 )
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a3 = Signal ( "a3", 1 )
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na3 = Signal ( "na3", 1 )
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a4 = Signal ( "a4", 1 )
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na4 = Signal ( "na4", 1 )
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a5 = Signal ( "a5", 1 )
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na5 = Signal ( "na5", 1 )
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a6x = Signal ( "a6x", 1 )
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na6x = Signal ( "na6x", 1 )
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a7x = Signal ( "a7x", 1 )
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na7x = Signal ( "na7x", 1 )
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a8x = Signal ( "a8x", 1 )
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na8x = Signal ( "na8x", 1 )
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a9x = Signal ( "a9x", 1 )
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na9x = Signal ( "na9x", 1 )
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col = Signal ( "col", self.nbit )
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In = {}
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Bit = {}
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Out = {}
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for i in range ( self.nbit ) :
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valeur = i % 4
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if valeur == 0 :
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cellin = "rom_data_invss"
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cellmid = "rom_data_midvss"
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if type == 0 : cellout = "rom_data_outvss"
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else : cellout = "rom_data_outvss_ts"
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elif valeur == 1 :
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cellin = "rom_data_insel"
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cellmid = "rom_data_midsel"
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if type == 0 : cellout = "rom_data_outsel"
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else : cellout = "rom_data_outsel_ts"
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elif valeur == 2:
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cellin = "rom_data_insel"
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cellmid = "rom_data_midsel"
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if type == 0 : cellout = "rom_data_outsel"
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else : cellout = "rom_data_outsel_ts"
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elif valeur == 3 :
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cellin = "rom_data_invss"
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cellmid = "rom_data_midvss"
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if type == 0 : cellout = "rom_data_outvss"
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else : cellout = "rom_data_outvss_ts"
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In[i] = Inst ( cellin
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, "in%d" % i
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, map = { 'prech' : prech
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, 'bit0' : bit0[i]
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, 'bit1' : bit1[i]
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, 'bit2' : bit2[i]
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, 'bit3' : bit3[i]
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, 'bit4' : bit4[i]
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, 'bit5' : bit5[i]
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, 'bit6' : bit6[i]
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, 'bit7' : bit7[i]
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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BitBis = {}
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Bit[i] = BitBis
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for j in range ( 0, self.nword, 64 ) :
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Bit[i][j] = Inst ( cellmid
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, "bit%d_%d" % ( i, j )
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, map = { 'sela' : line0[j]
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, 'selb' : line2[j]
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, 'selc' : line4[j]
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, 'seld' : line6[j]
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, 'bit0' : bit0 [i]
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, 'bit1' : bit1 [i]
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, 'bit2' : bit2 [i]
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, 'bit3' : bit3 [i]
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, 'bit4' : bit4 [i]
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, 'bit5' : bit5 [i]
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, 'bit6' : bit6 [i]
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, 'bit7' : bit7 [i]
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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Bit[i][j+32] = Inst ( cellmid
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, "bit%d_%d" % ( i, j+32 )
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, map = { 'sela' : line1[j]
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, 'selb' : line3[j]
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, 'selc' : line5[j]
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, 'seld' : line7[j]
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, 'bit0' : bit0 [i]
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, 'bit1' : bit1 [i]
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, 'bit2' : bit2 [i]
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, 'bit3' : bit3 [i]
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, 'bit4' : bit4 [i]
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, 'bit5' : bit5 [i]
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, 'bit6' : bit6 [i]
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, 'bit7' : bit7 [i]
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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thisMap = { 'nprech' : nprech
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, 'mux0' : mux0
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, 'mux1' : mux1
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, 'mux2' : mux2
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, 'mux3' : mux3
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, 'mux4' : mux4
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, 'mux5' : mux5
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, 'mux6' : mux6
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, 'mux7' : mux7
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, 'bit0' : bit0[i]
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, 'bit1' : bit1[i]
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, 'bit2' : bit2[i]
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, 'bit3' : bit3[i]
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, 'bit4' : bit4[i]
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, 'bit5' : bit5[i]
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, 'bit6' : bit6[i]
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, 'bit7' : bit7[i]
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, 'q' : data[i]
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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if type == 1 :
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thisMap['enx'] = enx
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thisMap['nenx'] = nenx
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Out[i] = Inst ( cellout
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, "out%d" % i
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, map = thisMap
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)
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## Cellules decodeur ##
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# Lignes 0 et 1
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Prech = Inst ( "rom_dec_prech"
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, "prech"
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, map = { 'nck' : nck
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, 'prech' : prech
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, 'nprech' : nprech
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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And01 = {}
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for j in range ( 0, self.nword, 64 ) :
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thisMap = { 'nck0' : nck
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, 'nck1' : nck
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, 'sel0' : sel0
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, 'sel1' : sel1
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, 'line0' : line0[j]
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, 'line1' : line1[j]
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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if self.nword != 64 : thisMap['col'] = col[j]
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else : thisMap['col'] = One ( 1 )
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And01[j] = Inst ( "rom_dec_line01"
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, "and01_%d" % j
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, map = thisMap
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)
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if type == 0 : model = "rom_dec_selmux01"
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else : model = "rom_dec_selmux01_rs"
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thisMap = { 'a0' : a0
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, 'na0' : na0
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, 'a1' : a1
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, 'na1' : na1
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, 'a2' : a2
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, 'na2' : na2
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, 'a3' : a3
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, 'na3' : na3
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, 'a4' : a4
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, 'na4' : na4
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, 'a5' : a5
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, 'na5' : na5
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, 'ck' : self.ck
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, 'selrom' : self.selrom
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, 'nck' : nck
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, 'mux0' : mux0
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, 'sel0' : sel0
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, 'mux1' : mux1
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, 'sel1' : sel1
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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if type == 1 :
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thisMap['enx'] = enx
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thisMap['nenx'] = nenx
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Selmux01 = Inst ( model
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, "selmux01"
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, map = thisMap
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)
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# Lignes 2 et 3
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Ad4 = Inst ( "rom_dec_adbuf"
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, "ad4"
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, map = { 'ad' : self.ad[4]
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, 'adx' : a4
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, 'nadx' : na4
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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Ad5 = Inst ( "rom_dec_adbuf"
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, "ad5"
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, map = { 'ad' : self.ad[5]
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, 'adx' : a5
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, 'nadx' : na5
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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And23 = {}
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for j in range ( 0, self.nword, 64 ) :
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thisMap = { 'nck2' : nck
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, 'nck3' : nck
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, 'sel2' : sel2
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, 'sel3' : sel3
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, 'line2' : line2[j]
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, 'line3' : line3[j]
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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if self.nword != 64 : thisMap['col'] = col[j]
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else : thisMap['col'] = One ( 1 )
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And23[j] = Inst ( "rom_dec_line23"
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, "and23_%d" % j
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, map = thisMap
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)
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if type == 0 : model = "rom_dec_selmux23"
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else : model = "rom_dec_selmux23_rs"
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thisMap = { 'a0' : a0
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, 'na0' : na0
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, 'a1' : a1
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, 'na1' : na1
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, 'a2' : a2
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, 'na2' : na2
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, 'a3' : a3
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, 'na3' : na3
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, 'a4' : a4
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, 'na4' : na4
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, 'a5' : a5
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, 'na5' : na5
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, 'ck' : self.ck
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, 'selrom' : self.selrom
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, 'nck' : nck
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, 'mux2' : mux2
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, 'sel2' : sel2
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, 'mux3' : mux3
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, 'sel3' : sel3
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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if type == 1 :
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thisMap['enx'] = enx
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thisMap['nenx'] = nenx
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Selmux23 = Inst ( "rom_dec_selmux23"
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, "selmux23"
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, map = thisMap
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)
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# Lignes 4 et 5
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Ad2 = Inst ( "rom_dec_adbuf"
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, "ad2"
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, map = { 'ad' : self.ad[2]
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, 'adx' : a2
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, 'nadx' : na2
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
|
|
Ad3 = Inst ( "rom_dec_adbuf"
|
|
, "ad3"
|
|
, map = { 'ad' : self.ad[3]
|
|
, 'adx' : a3
|
|
, 'nadx' : na3
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
|
|
And45 = {}
|
|
for j in range ( 0, self.nword, 64 ) :
|
|
thisMap = { 'nck4' : nck
|
|
, 'nck5' : nck
|
|
, 'sel4' : sel4
|
|
, 'sel5' : sel5
|
|
, 'line4' : line4[j]
|
|
, 'line5' : line5[j]
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
if self.nword != 64 : thisMap['col'] = col[j]
|
|
else : thisMap['col'] = One ( 1 )
|
|
And45[j] = Inst ( "rom_dec_line45"
|
|
, "and45_%d" % j
|
|
, map = thisMap
|
|
)
|
|
|
|
if type == 0 : model = "rom_dec_selmux45"
|
|
else : model = "rom_dec_selmux45_rs"
|
|
thisMap = { 'a0' : a0
|
|
, 'na0' : na0
|
|
, 'a1' : a1
|
|
, 'na1' : na1
|
|
, 'a2' : a2
|
|
, 'na2' : na2
|
|
, 'a3' : a3
|
|
, 'na3' : na3
|
|
, 'a4' : a4
|
|
, 'na4' : na4
|
|
, 'a5' : a5
|
|
, 'na5' : na5
|
|
, 'ck' : self.ck
|
|
, 'selrom' : self.selrom
|
|
, 'nck' : nck
|
|
, 'mux4' : mux4
|
|
, 'sel5' : sel4
|
|
, 'mux5' : mux5
|
|
, 'sek5' : sel5
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
if type == 1 :
|
|
thisMap['enx'] = enx
|
|
thisMap['nenx'] = nenx
|
|
Selmux45 = Inst ( model
|
|
, "selmux23"
|
|
, map = thisMap
|
|
)
|
|
|
|
# Lignes 6 et 7
|
|
Ad0 = Inst ( "rom_dec_adbuf"
|
|
, "ad0"
|
|
, map = { 'ad' : self.ad[0]
|
|
, 'adx' : a0
|
|
, 'nadx' : na0
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
Ad1 = Inst ( "rom_dec_adbuf"
|
|
, "ad1"
|
|
, map = { 'ad' : self.ad[1]
|
|
, 'adx' : a1
|
|
, 'nadx' : na1
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
|
|
And67 = {}
|
|
for j in range ( 0, self.nword, 64 ) :
|
|
thisMap = { 'nck6' : nck
|
|
, 'nck7' : nck
|
|
, 'sel6' : sel6
|
|
, 'sel7' : sel7
|
|
, 'line6' : line6[j]
|
|
, 'line7' : line7[j]
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
if self.nword != 64 : thisMap['col'] = col[j]
|
|
else : thisMap['col'] = One ( 1 )
|
|
And67[j] = Inst ( "rom_dec_line67"
|
|
, "and67_%d" % j
|
|
, map = thisMap
|
|
)
|
|
|
|
if self.nword != 128 : # pas de sortie tristate
|
|
if type == 0 : model = "rom_dec_selmux67"
|
|
else : model = "rom_dec_selmux67_ts"
|
|
thisMap = { 'a0' : a0
|
|
, 'na0' : na0
|
|
, 'a1' : a1
|
|
, 'na1' : na1
|
|
, 'a2' : a2
|
|
, 'na2' : na2
|
|
, 'a3' : a3
|
|
, 'na3' : na3
|
|
, 'a4' : a4
|
|
, 'na4' : na4
|
|
, 'a5' : a5
|
|
, 'na5' : na5
|
|
, 'ck' : self.ck
|
|
, 'selrom' : self.selrom
|
|
, 'nck' : nck
|
|
, 'mux6' : mux6
|
|
, 'sel6' : sel6
|
|
, 'mux7' : mux7
|
|
, 'sel7' : sel7
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
if type == 1 :
|
|
thisMap['enx'] = enx
|
|
thisMap['nenx'] = nenx
|
|
Selmux67 = Inst ( model
|
|
, "selmux67"
|
|
, map = thisMap
|
|
)
|
|
else : # pas de sortie tristate - 128 mots
|
|
if type == 0 : model = "rom_dec_selmux128"
|
|
else : model = "rom_dec_selmux128_ts"
|
|
thisMap = { 'a0' : a0
|
|
, 'na0' : na0
|
|
, 'a1' : a1
|
|
, 'na1' : na1
|
|
, 'a2' : a2
|
|
, 'na2' : na2
|
|
, 'a3' : a3
|
|
, 'na3' : na3
|
|
, 'a4' : a4
|
|
, 'na4' : na4
|
|
, 'a5' : a5
|
|
, 'na5' : na5
|
|
, 'a6' : self.ad[6]
|
|
, 'selrom' : self.selrom
|
|
, 'a6x' : col[64]
|
|
, 'na6x' : col[0]
|
|
, 'mux6' : mux6
|
|
, 'sel6' : sel6
|
|
, 'mux7' : mux7
|
|
, 'sel7' : sel7
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
if type == 1 :
|
|
thisMap['enx'] = enx
|
|
thisMap['nenx'] = nenx
|
|
Selmux67 = Inst ( model
|
|
, "selmux67"
|
|
, map = thisMap
|
|
)
|
|
|
|
# Ligne 9 dans le cas 1024 mots
|
|
if self.nword == 1024 :
|
|
Nop = Inst ( "rom_dec_nop"
|
|
, "nop"
|
|
, map = { 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
|
|
Col = {}
|
|
for j in range ( 0, self.nword, 64 ) :
|
|
thisMap = { 'q' : col[j]
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
if ( j >> 6 ) % 2 == 0 : thisMap['i0'] = na6x
|
|
else : thisMap['i0'] = a6x
|
|
if ( j >> 7 ) % 2 == 0 : thisMap['i1'] = na7x
|
|
else : thisMap['i1'] = a7x
|
|
if ( j >> 8 ) % 2 == 0 : thisMap['i2'] = na8x
|
|
else : thisMap['i2'] = a8x
|
|
if ( j >> 9 ) % 2 == 0 : thisMap['i3'] = na9x
|
|
else : thisMap['i3'] = a9x
|
|
Col[j] = Inst ( "rom_dec_col4"
|
|
, "col_%d" % j
|
|
, map = thisMap
|
|
)
|
|
|
|
ColBuf6 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf6"
|
|
, map = { 'a' : self.ad[6]
|
|
, 'ax' : a6x
|
|
, 'nax' : na6x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
)
|
|
ColBuf7 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf7"
|
|
, map = { 'a' : self.ad[7]
|
|
, 'ax' : a7x
|
|
, 'nax' : na7x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
ColBuf8 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf8"
|
|
, map = { 'a' : self.ad[8]
|
|
, 'ax' : a8x
|
|
, 'nax' : na8x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
ColBuf9 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf9"
|
|
, map = { 'a' : self.ad[9]
|
|
, 'ax' : a9x
|
|
, 'nax' : na9x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
|
|
# Ligne 9 dans le cas 512 mots
|
|
if self.nword == 512 :
|
|
Nop = Inst ( "rom_dec_nop"
|
|
, "nop"
|
|
, map = { 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
|
|
for j in range ( 0, self.nword, 64 ) :
|
|
thisMap = { 'q' : col[j]
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
if ( j >> 6 ) % 2 == 0 : thisMap['i0'] = na6x
|
|
else : thisMap['i0'] = a6x
|
|
if ( j >> 7 ) % 2 == 0 : thisMap['i1'] = na7x
|
|
else : thisMap['i1'] = a7x
|
|
if ( j >> 8 ) % 2 == 0 : thisMap['i2'] = na8x
|
|
else : thisMap['i2'] = a8x
|
|
Col[j] = Inst ( "rom_dec_col3"
|
|
, "col_%d" % j
|
|
, map = thisMap
|
|
)
|
|
|
|
Colbuf6 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf6"
|
|
, map = { 'a' : ad[6]
|
|
, 'ax' : a6x
|
|
, 'nax' : na6x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
Colbuf7 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf7"
|
|
, map = { 'a' : ad[7]
|
|
, 'ax' : a7x
|
|
, 'nax' : na7x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
Colbuf8 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf8"
|
|
, map = { 'a' : ad[8]
|
|
, 'ax' : a8x
|
|
, 'nax' : na8x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
|
|
# Ligne 9 dans le cas 256 mots
|
|
if self.nword == 256 :
|
|
Nop = Inst ( "rom_dec_nop"
|
|
, "nop"
|
|
, map = { 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
|
|
Col = {}
|
|
for j in range ( 0, self.nword, 64 ) :
|
|
thisMap = { 'q' : col[j]
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
if ( j >> 6 ) % 2 == 0 : thisMap['i0'] = na6x
|
|
else : thisMap['i0'] = a6x
|
|
if ( j >> 7 ) % 2 == 0 : thisMap['i1'] = na7x
|
|
else : thisMap['i1'] = a7x
|
|
Col[j] = Inst ( "rom_dec_col2"
|
|
, "col_%d" % j
|
|
, map = thisMap
|
|
)
|
|
|
|
Colbuf6 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf6"
|
|
, map = { 'a' : ad[6]
|
|
, 'ax' : a6x
|
|
, 'nax' : na6x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
ColBuf7 = Inst ( "rom_dec_colbuf"
|
|
, "colbuf7"
|
|
, map = { 'a' : ad[7]
|
|
, 'ax' : a7x
|
|
, 'nax' : na7x
|
|
, 'vdd' : self.vdd
|
|
, 'vss' : self.vss
|
|
}
|
|
)
|
|
|
|
def Layout ( self ) :
|
|
## Placement des lignes du plan memoire ##
|
|
for i in range ( self.nbit ) :
|
|
val = i % 4
|
|
if val == 0 : sym = NOSYM
|
|
elif val == 1 : sym = SYM_Y
|
|
elif val == 2 : sym = NOSYM
|
|
elif val == 3 : sym = SYM_Y
|
|
|
|
Place ( In(i], sym, 0, i*HCELL )
|
|
|
|
for j in range ( 0, self.nword, 64 ) :
|
|
PlaceRight ( Bit[i][j], sym )
|
|
PlaceRight ( Bit[i][j+32], sym )
|
|
|
|
PlaceRight ( Out[i], sym )
|
|
|
|
## Placement des cellules decodeur ##
|
|
|
|
# Lignes 0 et 1
|
|
Place ( Prech, NOSYM, 0, nbit*HCELL )
|
|
for j in range ( 0, self.nword, 64 ) : PlaceRight ( And01[j], NOSYM )
|
|
PlaceRight ( Selmux01, NOSYM )
|
|
|
|
# Lignes 2 et 3
|
|
Place ( Ad4, SYM_Y, 0, (nbit+3)*HCELL )
|
|
Place ( Ad5, NOSYM, 0, (nbit+2)*HCELL )
|
|
for j in range ( 0, self.nword, 64 ) : PlaceRight ( And23[j], NOSYM )
|
|
PlaceRight ( Selmux23, NOSYM )
|
|
|
|
# Lignes 4 et 5
|
|
Place ( Ad2, SYM_Y, 0, (nbit+5)*HCELL )
|
|
Place ( Ad3, NOSYM, 0, (nbit+4)*HCELL )
|
|
for j in range ( 0, self.nword, 64 ) : PlaceRight ( And45[j], NOSYM )
|
|
Place ( Selmux45, NOSYM )
|
|
|
|
# Lignes 6 et 7
|
|
Place ( Ad0, SYM_Y, 0, (nbit+7)*HCELL )
|
|
Place ( Ad1, NOSYM, 0, (nbit+6)*HCELL )
|
|
for j in range ( 0, self.nword, 64 ) : PlaceRight ( And67[j], NOSYM )
|
|
PlaceRight ( Selmux67, NOSYM )
|
|
|
|
# Ligne 9 dans le cas 1024 mots
|
|
if self.nword == 1024 :
|
|
Place ( Nop, NOSYM, 0, (nbit+8)*HCELL )
|
|
for j in range ( 0, self.nword, 64 ) : PlaceRight ( Col, NOSYM )
|
|
PlaceRight ( ColBuf6, NOSYM )
|
|
PlaceRight ( ColBuf7, NOSYM )
|
|
PlaceRight ( ColBuf8, NOSYM )
|
|
PlaceRight ( ColBuf9, NOSYM )
|
|
# Ligne 9 dans le cas 512 mots
|
|
elif self.nword == 512 :
|
|
Place ( Nop, NOSYM, 0, (nbit+8)*HCELL )
|
|
for j in range ( 0, self.nword, 64 ) : PlaceRight ( Col[j], NOSYM )
|
|
PlaceRight ( ColBuf6, NOSYM )
|
|
PlaceRight ( ColBuf7, NOSYM )
|
|
PlaceRight ( ColBuf8, NOSYM )
|
|
# Ligne 9 dans le cas 256 mots
|
|
elif self.nword == 256 :
|
|
Place ( Nop, NOSYM, 0, (nbit+8)*HCELL )
|
|
for j in range ( 0, self.nword, 64 ) : PlaceRight ( Col[j], NOSYM )
|
|
PlaceRight ( ColBuf6, NOSYM )
|
|
PlaceRight ( ColBuf7, NOSYM )
|
|
|
|
def ROM_VHDL ( self ) :
|
|
global LV_flags
|
|
global LV_ModelName
|
|
|
|
pass
|
|
# fileName = LV_ModelName + ".vbe"
|
|
#
|
|
# file = open ( fileName, "w+" )
|
|
#
|
|
# if self.nword == 64 : adrange = 6
|
|
# elif self.nword == 128 : adrange = 7
|
|
# elif self.nword == 256 : adrange = 8
|
|
# elif self.nword == 512 : adrange = 9
|
|
# elif self.nword == 1024 : adrange = 10
|
|
#
|
|
# sBusWide0 = VHDL_BUS_WIDE ( self.nbit - 1, 0, self.nbit, LV_flags )
|
|
# sBusWide1 = VHDL_BUS_WIDE ( adrange - 1, 0, self.nbit, LV_flags )
|
|
#
|
|
# ## Entity description ##
|
|
# file.write ( "\nENTITY %s IS\n PORT (\n" % LV_ModelName )
|
|
#
|
|
# file.write ( "%14s : in BIT;\n" % "ck" )
|
|
# file.write ( "%14s : in BIT;\n" % "selrom" )
|
|
# file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "ad", sBusWide1 ) )
|
|
# file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "data", sBusWide0 ) )
|
|
#
|
|
# ## Power supplies terminals ##
|
|
# file.write ( "%14s : in BIT;\n" % "vdd" )
|
|
# file.write ( "%14s : in BIT\n" % "vss" )
|
|
#
|
|
# ## End of entity description ##
|
|
# file.write ( " );\nEND %s;\n\n\n" % LV_ModelName )
|
|
#
|
|
# ## Architecture description ##
|
|
# file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % LV_ModelName )
|
|
#
|
|
# ## Signals ##
|
|
#
|
|
#
|
|
#
|
|
# ## Behavior ##
|
|
# file.write ( "\nBEGIN\n\n" )
|
|
#
|
|
#
|
|
#
|
|
#
|
|
#
|
|
# ## Assert ##
|
|
# file.write ( " ASSERT (vdd = '1')\n" )
|
|
# file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % LV_modelName )
|
|
# file.write ( " SEVERITY WARNING;\n\n" )
|
|
#
|
|
#
|
|
# file.write ( " ASSERT (vss = '0')\n" )
|
|
# file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % LV_modelName )
|
|
# file.write ( " SEVERITY WARNING;\n\n" )
|
|
#
|
|
# ## End of Architectural description ##
|
|
# file.write ( "END VBE;\n" )
|
|
#
|
|
# file.close ()
|
|
|
|
####################
|
|
##### DpgenROM #####
|
|
####################
|
|
class DpgenROM ( TopRom ) :
|
|
|
|
def Interface ( self ) : TopRom.Interface ( self )
|
|
def Netlist ( self ) : TopRom.Netlist ( self, 0 )
|
|
def Layout ( self ) : topRom.Layout ( self )
|
|
def Vbe ( self ) : topRom.Vbe ( self )
|
|
|
|
|
|
######################
|
|
##### DpgenROMTS #####
|
|
######################
|
|
class DpgenROMTS ( TopRom ) :
|
|
|
|
def Interface ( self ) : TopRom.Interface ( self )
|
|
def Netlist ( self ) : TopRom.Netlist ( self, 1 )
|
|
def Layout ( self ) : topRom.Layout ( self )
|
|
def Vbe ( self ) : topRom.Vbe ( self )
|