1146 lines
44 KiB
Python
1146 lines
44 KiB
Python
#!/usr/bin/python
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# This file is part of the Coriolis Project.
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# Copyright (C) Laboratoire LIP6 - Departement ASIM
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# Universite Pierre et Marie Curie
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#
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# Main contributors :
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# Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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# Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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# Hugo Clement <Hugo.Clement@lip6.fr>
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# Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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# Damien Dupuis <Damien.Dupuis@lip6.fr>
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# Christian Masson <Christian.Masson@lip6.fr>
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# Marek Sroka <Marek.Sroka@lip6.fr>
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#
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# The Coriolis Project is free software; you can redistribute it
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# and/or modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# The Coriolis Project is distributed in the hope that it will be
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# useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with the Coriolis Project; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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#
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# License-Tag
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# Authors-Tag
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# ===================================================================
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#
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# x-----------------------------------------------------------------x
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# | |
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./dpgen_RF2.py" |
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# | *************************************************************** |
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# | U p d a t e s |
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# | |
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# x-----------------------------------------------------------------x
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from stratus import *
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# Banc de registre triple acces : deux lectures, une ecriture
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# Le programme genere une net-list et un placement optimise.
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#
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# La largeur est egale a (nmot * 35) + 150
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# La hauteur est egale a (nbit + 8) * 50
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#
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# Pour la partie "donnees", on utilise les cellules suivantes :
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# colonne d'entree
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# - rf2_inmux_mem
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# - rf2_inmux_buf
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# colonne centrale
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# - rf2_mid_mem
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# - rf2_mid_mem_r0
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# - rf2_mid_buf
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# colonne de sortie
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# - rf2_out_mem
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# - rf2_out_buf
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#
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# Pour le decodeur, on utilise les cellules suivantes :
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# - rf2_dec_bufad0
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# - rf2_dec_bufad1_l
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# - rf2_dec_bufad2_l
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# - rf2_dec_bufad1_r
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# - rf2_dec_bufad2_r
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# - rf2_dec_nbuf
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# - rf2_dec_nor3
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# - rf2_dec_nao3
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# - rf2_dec_nand2
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# - rf2_dec_nand3
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# - rf2_dec_nand4
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#----------------------------------------------------------------
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# DEBUT PROGRAMME PRINCIPAL
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#----------------------------------------------------------------
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# aFunction : le type :
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# DPGEN_RF2 (sans decodeur)
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# DPGEN_RF2R0 (sans decodeur, avec R0 colle a 0)
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# DPGEN_RF2D (avec decodeur)
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# DPGEN_RF2DR0 (avec decodeur, avec R0 colle a 0)
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#
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# aAL : liste des parametres :
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# Model_name : nom de modele.
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# flags : indexation des connecteurs.
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# nbit : nombre de bits (largeur du bus).
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# nmot : nombre de mots.
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# - le nombre de mots doit etre pair, 6 =< nmot =< 32
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# - le nombre de bits doit etre pair, 2 =< nbit =< 64
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#----------------------------------------------------------------
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#################################
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##### Classe mere : top_rf2 #####
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#################################
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class top_rf2 ( Model ) :
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## Interface ##
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###############
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def Interface ( self, nbit, nword, type ) :
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global adrange
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if nword % 2 == 1 or nword > 32 or nword < 4 :
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print "Error in DpgenRf2 : the word number must be even, larger than 4 and no larger than 32\n"
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sys.exit ( 1 )
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if nword == 4 and ( type == 2 or type == 3 ) :
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print "Error in DpgenRf2 : the word number must be larger than 4\n"
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sys.exit ( 1 )
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if nbit % 2 == 1 or nbit > 64 or nbit < 2 :
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print "Error in DpgenRf2 : the bit number must be even and no larger than 64\n"
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sys.exit ( 1 )
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adrange = 2
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if nword > 4 : adrange = 3
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if nword > 8 : adrange = 4
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if nword > 16 : adrange = 5
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if type < 2 : # c'est un banc de registres sans decodeur
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self._ck = SignalIn ( "ck", 1 )
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self._sel = SignalIn ( "sel", 1 )
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self._sela = SignalIn ( "sela", nword )
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self._selb = SignalIn ( "selb", nword )
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self._selw = SignalIn ( "selw", nword )
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self._datain0 = SignalIn ( "datain0", nbit )
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self._datain1 = SignalIn ( "datain1", nbit )
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self._dataouta = SignalOut ( "dataouta", nbit )
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self._dataoutb = SignalOut ( "dataoutb", nbit )
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else : # c'est un banc de registres avec decodeur
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self._ck = SignalIn ( "ck", 1 )
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self._sel = SignalIn ( "sel", 1 )
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self._wen = SignalIn ( "wen", 1 )
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self._rena = SignalIn ( "rena", 1 )
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self._renb = SignalIn ( "renb", 1 )
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self._adra = SignalIn ( "adra", adrange )
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self._adrb = SignalIn ( "adrb", adrange )
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self._adw = SignalIn ( "adw" , adrange )
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self._datain0 = SignalIn ( "datain0", nbit )
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self._datain1 = SignalIn ( "datain1", nbit )
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self._dataouta = SignalOut ( "dataouta", nbit )
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self._dataoutb = SignalOut ( "dataoutb", nbit )
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self._selw = Signal ( "selw", nword )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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## Netlist ##
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#############
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def Netlist ( self, nbit, nword, type ) :
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global adrange
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# Signaux
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sel0 = Signal ( "sel0", 1 )
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sel1 = Signal ( "sel1", 1 )
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xcks = Signal ( "xcks", 1 )
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nck = Signal ( "nck", 1 )
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nwen = Signal ( "nwen", 1 )
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nrena = Signal ( "nrena", 1 )
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nrenb = Signal ( "nrenb", 1 )
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adw0x = Signal ( "adw0x", 1 )
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nadw0x = Signal ( "nadw0x", 1 )
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adw1x = Signal ( "adw1x", 1 )
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nadw1x = Signal ( "nadw1x", 1 )
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adw2x = Signal ( "adw2x", 1 )
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nadw2x = Signal ( "nadw2x", 1 )
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adw3x = Signal ( "adw3x", 1 )
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nadw3x = Signal ( "nadw3x", 1 )
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adw4x = Signal ( "adw4x", 1 )
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nadw4x = Signal ( "nadw4x", 1 )
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adra0x = Signal ( "adra0x", 1 )
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nadra0x = Signal ( "nadra0x", 1 )
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adra1x = Signal ( "adra1x", 1 )
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nadra1x = Signal ( "nadra1x", 1 )
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adra2x = Signal ( "adra2x", 1 )
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nadra2x = Signal ( "nadra2x", 1 )
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adra3x = Signal ( "adra3x", 1 )
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nadra3x = Signal ( "nadra3x", 1 )
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adra4x = Signal ( "adra4x", 1 )
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nadra4x = Signal ( "nadra4x", 1 )
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adrb0x = Signal ( "adrb0x", 1 )
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nadrb0x = Signal ( "nadrb0x", 1 )
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adrb1x = Signal ( "adrb1x", 1 )
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nadrb1x = Signal ( "nadrb1x", 1 )
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adrb2x = Signal ( "adrb2x", 1 )
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nadrb2x = Signal ( "nadrb2x", 1 )
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adrb3x = Signal ( "adrb3x", 1 )
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nadrb3x = Signal ( "nadrb3x", 1 )
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adrb4x = Signal ( "adrb4x", 1 )
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nadrb4x = Signal ( "nadrb4x", 1 )
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dinx = Signal ( "dinx", nbit )
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busa = Signal ( "busa", nbit )
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busb = Signal ( "busb", nbit )
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if type >= 2 :
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self._sela = Signal ( "sela", nword )
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self._selb = Signal ( "selb", nword )
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write = []
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reada = []
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readb = []
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for i in range ( nword ) :
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write += [Signal ( "write%d" % i, 1 )]
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reada += [Signal ( "reada%d" % i, 1 )]
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readb += [Signal ( "readb%d" % i, 1 )]
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nandw = []
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nandra = []
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nandrb = []
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for i in range ( nword >> 1 ) :
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nandw += [Signal ( "nandw%d" % i, 1 )]
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nandra += [Signal ( "nandra%d" % i, 1 )]
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nandrb += [Signal ( "nandrb%d" % i, 1 )]
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# placement des lignes de bit en dessous des buffers
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self.In = {}
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self.Bit = {}
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self.Out = {}
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for i in range ( nbit ) :
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self.In[nbit-1-i] = Inst ( 'rf2_inmux_mem'
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, 'in%d' % ( nbit - 1 - i )
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, map = { 'datain0' : self._datain0[nbit - 1 - i]
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, 'datain1' : self._datain1[nbit - 1 - i]
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, 'sel0' : sel0
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, 'sel1' : sel1
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, 'dinx' : dinx[nbit - 1 - i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.BitBis = {}
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for j in range ( 0, nword, 2 ) :
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if j == 0 and ( type == 1 or type == 3 ) :
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self.BitBis[j] = Inst ( 'rf2_mid_mem_r0'
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, 'bit%d_%d' % ( nbit - 1 - i , j )
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, map = { 'dinx' : dinx[nbit - 1 - i]
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, 'write' : write[j]
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, 'reada' : reada[j]
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, 'readb' : readb[j]
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, 'busa' : busa[nbit - 1 - i]
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, 'busb' : busb[nbit - 1 - i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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else :
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self.BitBis[j] = Inst ( 'rf2_mid_mem'
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, 'bit%d_%d' % ( nbit - 1 - i, j )
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, map = { 'dinx' : dinx[nbit - 1 - i]
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, 'write' : write[j]
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, 'reada' : reada[j]
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, 'readb' : readb[j]
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, 'busa' : busa[nbit - 1 - i]
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, 'busb' : busb[nbit - 1 - i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.BitBis[j+1] = Inst ( 'rf2_mid_mem'
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, 'bit%d_%d' % ( nbit - 1 - i, j + 1 )
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, map = { 'dinx' : dinx[nbit - 1 - i]
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, 'write' : write[j + 1]
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, 'reada' : reada[j + 1]
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, 'readb' : readb[j + 1]
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, 'busa' : busa[nbit - 1 - i]
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, 'busb' : busb[nbit - 1 - i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Bit[nbit-1-i] = self.BitBis
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self.Out[nbit-1-i] = Inst ( 'rf2_out_mem'
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, 'out%d' % ( nbit - 1 - i )
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, map = { 'busa' : busa[nbit - 1 - i]
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, 'busb' : busb[nbit - 1 - i]
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, 'xcks' : xcks
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, 'dataouta' : self._dataouta[nbit - 1 - i]
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, 'dataoutb' : self._dataoutb[nbit - 1 - i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# placement de la ligne contenant les buffers
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self.InBuf = Inst ( 'rf2_inmux_buf'
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, 'inbuf'
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, map = { 'sel' : self._sel
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, 'sel0' : sel0
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, 'sel1' : sel1
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Buf = {}
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for j in range ( 0, nword, 2 ) :
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self.Buf[j] = Inst ( 'rf2_mid_buf'
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, 'buf%d' % j
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, map = { 'selra' : self._sela[j]
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, 'selrb' : self._selb[j]
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, 'selw' : self._selw[j]
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, 'nck' : nck
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, 'reada' : reada[j]
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, 'readb' : readb[j]
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, 'write' : write[j]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Buf[j+1] = Inst ( 'rf2_mid_buf'
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, 'buf%d' % ( j + 1 )
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, map = { 'selra' : self._sela[j + 1]
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, 'selrb' : self._selb[j + 1]
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, 'selw' : self._selw[j + 1]
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, 'nck' : nck
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, 'reada' : reada[j + 1]
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, 'readb' : readb[j + 1]
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, 'write' : write[j + 1]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.OutBuf = Inst ( 'rf2_out_buf'
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, 'outbuf'
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, map = { 'ck' : self._ck
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, 'nck' : nck
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, 'xcks' : xcks
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# placement des cellules du decodeur ecriture
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if type == 2 or type == 3 :
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half = nword >> 1
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# Premiere ligne decodeur ecriture
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self.Adw0 = Inst ( 'rf2_dec_bufad0'
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, 'adw0'
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, map = { 'i' : self._adw[0]
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, 'nq' : nadw0x
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, 'q' : adw0x
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.SelW = {}
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for j in range ( half ) :
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self.SelW[2*j] = Inst ( 'rf2_dec_nor3'
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, 'selw%d' % ( 2 * j )
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, map = { 'i0' : nandw[j]
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, 'i1' : adw0x
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, 'i2' : nwen
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, 'nq' : self._selw[2 * j]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.SelW[2*j+1] = Inst ( 'rf2_dec_nor3'
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, 'selw%d' % ( 2 * j + 1 )
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, map = { 'i0' : nandw[j]
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, 'i1' : nadw0x
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, 'i2' : nwen
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, 'nq' : self._selw[2 * j + 1]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Wen = Inst ( 'rf2_dec_nbuf'
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, 'wen'
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, map = { 'i' : self._wen
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, 'nq' : nwen
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# Deuxieme ligne decodeur ecriture
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if adrange == 5 : # adresse sur 5 bits
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self.Adw12 = Inst ( 'rf2_dec_bufad2_l'
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, 'adw12'
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, map = { 'i0' : self._adw[1]
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, 'i1' : self._adw[2]
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, 'nq0' : nadw1x
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, 'q0' : adw1x
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, 'nq1' : nadw2x
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, 'q1' : adw2x
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Nand4W = {}
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for j in range ( half ) :
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thisMap = { 'nq' : nandw[j]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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if j % 2 == 0 : thisMap['i0'] = nadw1x
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else : thisMap['i0'] = adw1x
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if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x
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else : thisMap['i1'] = adw2x
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if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadw3x
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else : thisMap['i2'] = adw3x
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if ( j >> 3 ) % 2 == 0 : thisMap['i3'] = nadw4x
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else : thisMap['i3'] = adw4x
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self.Nand4W[j] = Inst ( 'rf2_dec_nand4'
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, 'nand4w%d' % j
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, map = thisMap
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)
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self.Adw34 = Inst ( 'rf2_dec_bufad2_l'
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, 'adw34'
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, map = { 'i0' : self._adw[3]
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, 'i1' : self._adw[4]
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, 'nq0' : nadw3x
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, 'q0' : adw3x
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, 'nq1' : nadw4x
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, 'q1' : adw4x
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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if adrange == 4 : # adresse sur 4 bits
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self.Adw12 = Inst ( 'rf2_dec_bufad2_l'
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, 'adw12'
|
|
, map = { 'i0' : self._adw[1]
|
|
, 'i1' : self._adw[2]
|
|
, 'nq0' : nadw1x
|
|
, 'q0' : adw1x
|
|
, 'nq1' : nadw2x
|
|
, 'q1' : adw2x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.Nand3W = {}
|
|
|
|
for j in range ( half ) :
|
|
thisMap = { 'nq' : nandw[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if j % 2 == 0 : thisMap['i0'] = nadw1x
|
|
else : thisMap['i0'] = adw1x
|
|
if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x
|
|
else : thisMap['i1'] = adw2x
|
|
if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadw3x
|
|
else : thisMap['i2'] = adw3x
|
|
|
|
self.Nand3W[j] = Inst ( 'rf2_dec_nand3'
|
|
, 'nand3w%d' % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.Adw3 = Inst ( 'rf2_dec_bufad1_r'
|
|
, 'adw3'
|
|
, map = { 'i' : self._adw[3]
|
|
, 'nq' : nadw3x
|
|
, 'q' : adw3x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
if adrange == 3 : # adresse sur 3 bits
|
|
self.Adw1 = Inst ( 'rf2_dec_bufad1_l'
|
|
, 'adw1'
|
|
, map = { 'i' : self._adw[1]
|
|
, 'nq' : nadw1x
|
|
, 'q' : adw1x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.Nand2W = {}
|
|
|
|
for j in range ( half ) :
|
|
thisMap = { 'nq' : nandw[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if j % 2 == 0 : thisMap['i0'] = nadw1x
|
|
else : thisMap['i0'] = adw1x
|
|
if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x
|
|
else : thisMap['i1'] = adw2x
|
|
|
|
self.Nand2W[j] = Inst ( 'rf2_dec_nand2'
|
|
, 'nand2w%d' % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.Adw2 = Inst ( 'rf2_dec_bufad1_r'
|
|
, 'adw2'
|
|
, map = { 'i' : self._adw[2]
|
|
, 'nq' : nadw2x
|
|
, 'q' : adw2x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
# placement des cellules du decodeur lecture A
|
|
if type == 2 or type == 3 :
|
|
half = nword >> 1
|
|
|
|
# Premiere ligne decodeur lecture A
|
|
self.Adra0 = Inst ( 'rf2_dec_bufad0'
|
|
, 'adra0'
|
|
, map = { 'i' : self._adra[0]
|
|
, 'nq' : nadra0x
|
|
, 'q' : adra0x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.SelRa = {}
|
|
|
|
for j in range ( half ) :
|
|
if j == 0 :
|
|
self.SelRa[2*j] = Inst ( 'rf2_dec_nao3'
|
|
, 'sela%d' % ( 2 * j )
|
|
, map = { 'i0' : nandra[j]
|
|
, 'i1' : adra0x
|
|
, 'i2' : self._rena
|
|
, 'nq' : self._sela[2 * j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
else :
|
|
self.SelRa[2*j] = Inst ( 'rf2_dec_nor3'
|
|
, 'sela%d' % ( 2 * j )
|
|
, map = { 'i0' : nandra[j]
|
|
, 'i1' : adra0x
|
|
, 'i2' : nrena
|
|
, 'nq' : self._sela[2 * j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.SelRa[2*j+1] = Inst ( 'rf2_dec_nor3'
|
|
, 'sela%d' % ( 2 * j + 1 )
|
|
, map = { 'i0' : nandra[j]
|
|
, 'i1' : nadra0x
|
|
, 'i2' : nrena
|
|
, 'nq' : self._sela[2 * j + 1]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.RenA = Inst ( 'rf2_dec_nbuf'
|
|
, 'rena'
|
|
, map = { 'i' : self._rena
|
|
, 'nq' : nrena
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
# Deuxieme ligne decodeur lecture A
|
|
if adrange == 5 : # adresse sur 5 bits
|
|
self.Adra12 = Inst ( 'rf2_dec_bufad2_l'
|
|
, 'adra12'
|
|
, map = { 'i0' : self._adra[1]
|
|
, 'i1' : self._adra[2]
|
|
, 'nq0' : nadra1x
|
|
, 'q0' : adra1x
|
|
, 'nq1' : nadra2x
|
|
, 'q1' : adra2x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.Nand4Ra = {}
|
|
|
|
for j in range ( half ) :
|
|
thisMap = { 'nq' : nandra[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if j % 2 == 0 : thisMap['i0'] = nadra1x
|
|
else : thisMap['i0'] = adra1x
|
|
if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadra2x
|
|
else : thisMap['i1'] = adra2x
|
|
if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadra3x
|
|
else : thisMap['i2'] = adra3x
|
|
if ( j >> 3 ) % 2 == 0 : thisMap['i3'] = nadra4x
|
|
else : thisMap['i3'] = adra4x
|
|
|
|
self.Nand4Ra[j] = Inst ( 'rf2_dec_nand4'
|
|
, 'nand4ra%d' % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.Adra34 = Inst ( 'rf2_dec_bufad2_r'
|
|
, 'adra34'
|
|
, map = { 'i0' : self._adra[3]
|
|
, 'i1' : self._adra[4]
|
|
, 'nq0' : nadra3x
|
|
, 'q0' : adra3x
|
|
, 'nq1' : nadra4x
|
|
, 'q1' : adra4x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
if adrange == 4 : # adresse sur 4 bits
|
|
self.Adra12 = Inst ( 'rf2_dec_bufad2_l'
|
|
, 'adra12'
|
|
, map = { 'i0' : self._adra[1]
|
|
, 'i1' : self._adra[2]
|
|
, 'nq0' : nadra1x
|
|
, 'q0' : adra1x
|
|
, 'nq1' : nadra2x
|
|
, 'q1' : adra2x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.Nand3Ra = {}
|
|
|
|
for j in range ( half ) :
|
|
thisMap = { 'nq' : nandra[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if j % 2 == 0 : thisMap['i0'] = nadra1x
|
|
else : thisMap['i0'] = adra1x
|
|
if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadra2x
|
|
else : thisMap['i1'] = adra2x
|
|
if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadra3x
|
|
else : thisMap['i2'] = adra3x
|
|
|
|
self.Nand3Ra[j] = Inst ( 'rf2_dec_nand3'
|
|
, 'nand3ra%d' % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.Adra3 = Inst ( 'rf2_dec_bufad1_r'
|
|
, 'adra3'
|
|
, map = { 'i' : self._adra[3]
|
|
, 'nq' : nadra3x
|
|
, 'q' : adra3x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
if adrange == 3 : # adresse sur 3 bits
|
|
self.Adra1 = Inst ( 'rf2_dec_bufad1_l'
|
|
, 'adra1'
|
|
, map = { 'i' : self._adra[1]
|
|
, 'nq' : nadra1x
|
|
, 'q' : adra1x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.Nand2Ra = {}
|
|
|
|
for j in range ( half ) :
|
|
thisMap = { 'nq' : nandra[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if j % 2 == 0 : thisMap['i0'] = nadra1x
|
|
else : thisMap['i0'] = adra1x
|
|
if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadra2x
|
|
else : thisMap['i1'] = adra2x
|
|
|
|
self.Nand2Ra[j] = Inst ( 'rf2_dec_nand2'
|
|
, 'nand2ra%d' % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.Adra2 = Inst ( 'rf2_dec_bufad1_r'
|
|
, 'adra2'
|
|
, map = { 'i' : self._adra[2]
|
|
, 'nq' : nadra2x
|
|
, 'q' : adra2x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
# placement des cellules du decodeur lecture B
|
|
if type == 2 or type == 3 :
|
|
half = nword >> 1
|
|
|
|
# Premiere ligne decodeur lecture A
|
|
self.Adrb0 = Inst ( 'rf2_dec_bufad0'
|
|
, 'adrb0'
|
|
, map = { 'i' : self._adrb[0]
|
|
, 'nq' : nadrb0x
|
|
, 'q' : adrb0x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.SelRb = {}
|
|
|
|
for j in range ( half ) :
|
|
if j == 0 :
|
|
self.SelRb[2*j] = Inst ( 'rf2_dec_nao3'
|
|
, 'selb%d' % ( 2 * j )
|
|
, map = { 'i0' : nandrb[j]
|
|
, 'i1' : adrb0x
|
|
, 'i2' : self._renb
|
|
, 'nq' : self._selb[2 * j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
else :
|
|
self.SelRb[2*j] = Inst ( 'rf2_dec_nor3'
|
|
, 'selb%d' % ( 2 * j )
|
|
, map = { 'i0' : nandrb[j]
|
|
, 'i1' : adrb0x
|
|
, 'i2' : nrenb
|
|
, 'nq' : self._selb[2 * j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.SelRb[2*j+1] = Inst ( 'rf2_dec_nor3'
|
|
, 'selb%d' % ( 2 * j + 1 )
|
|
, map = { 'i0' : nandrb[j]
|
|
, 'i1' : nadrb0x
|
|
, 'i2' : nrenb
|
|
, 'nq' : self._selb[2 * j + 1]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.RenB = Inst ( 'rf2_dec_nbuf'
|
|
, 'renb'
|
|
, map = { 'i' : self._renb
|
|
, 'nq' : nrenb
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
# Deuxieme ligne decodeur lecture A
|
|
if adrange == 5 : # adresse sur 5 bits
|
|
self.Adrb12 = Inst ( 'rf2_dec_bufad2_l'
|
|
, 'adrb12'
|
|
, map = { 'i0' : self._adrb[1]
|
|
, 'i1' : self._adrb[2]
|
|
, 'nq0' : nadrb1x
|
|
, 'q0' : adrb1x
|
|
, 'nq1' : nadrb2x
|
|
, 'q1' : adrb2x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.Nand4Rb = {}
|
|
|
|
for j in range ( half ) :
|
|
thisMap = { 'nq' : nandrb[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
if j % 2 == 0 : thisMap['i0'] = nadrb1x
|
|
else : thisMap['i0'] = adrb1x
|
|
if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadrb2x
|
|
else : thisMap['i1'] = adrb2x
|
|
if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadrb3x
|
|
else : thisMap['i2'] = adrb3x
|
|
if ( j >> 3 ) % 2 == 0 : thisMap['i3'] = nadrb4x
|
|
else : thisMap['i3'] = adrb4x
|
|
|
|
self.Nand4Rb[j] = Inst ( 'rf2_dec_nand4'
|
|
, 'nand4rb%d' % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.Adrb34 = Inst ( 'rf2_dec_bufad2_r'
|
|
,'adrb34'
|
|
, map = { 'i0' : self._adrb[3]
|
|
, 'i1' : self._adrb[4]
|
|
, 'nq0' : nadrb3x
|
|
, 'q0' : adrb3x
|
|
, 'nq1' : nadrb4x
|
|
, 'q1' : adrb4x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
if adrange == 4 : # adresse sur 4 bits
|
|
self.Adrb12 = Inst ( 'rf2_dec_bufad2_l'
|
|
, 'adrb12'
|
|
, map = { 'i0' : self._adrb[1]
|
|
, 'i1' : self._adrb[2]
|
|
, 'nq0' : nadrb1x
|
|
, 'q0' : adrb1x
|
|
, 'nq1' : nadrb2x
|
|
, 'q1' : adrb2x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.Nand3Rb = {}
|
|
|
|
for j in range ( half ) :
|
|
thisMap = { 'nq' : nandrb[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if j % 2 == 0 : thisMap['i0'] = nadrb1x
|
|
else : thisMap['i0'] = adrb1x
|
|
if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadrb2x
|
|
else : thisMap['i1'] = adrb2x
|
|
if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadrb3x
|
|
else : thisMap['i2'] = adrb3x
|
|
|
|
self.Nand3Rb[j] = Inst ( 'rf2_dec_nand3'
|
|
, 'nand3rb%d' % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.Adrb3 = Inst ( 'rf2_dec_bufad1_r'
|
|
, 'adrb3'
|
|
, map = { 'i' : self._adrb[3]
|
|
, 'nq' : nadrb3x
|
|
, 'q' : adrb3x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
if adrange == 3 : # adresse sur 3 bits
|
|
self.Adrb1 = Inst ( 'rf2_dec_bufad1_l'
|
|
, 'adrb1'
|
|
, map = { 'i' : self._adrb[1]
|
|
, 'nq' : nadrb1x
|
|
, 'q' : adrb1x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.Nand2Rb = {}
|
|
|
|
for j in range ( half ) :
|
|
thisMap = { 'nq' : nandrb[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if j % 2 == 0 : thisMap['i0'] = nadrb1x
|
|
else : thisMap['i0'] = adrb1x
|
|
if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadrb2x
|
|
else : thisMap['i1'] = adrb2x
|
|
|
|
self.Nand2Rb[j] = Inst ( 'rf2_dec_nand2'
|
|
, 'nand2rb%d' % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.Adrb2 = Inst ( 'rf2_dec_bufad1_r'
|
|
, 'adrb2'
|
|
, map = { 'i' : self._adrb[2]
|
|
, 'nq' : nadrb2x
|
|
, 'q' : adrb2x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
|
|
## Layout ##
|
|
############
|
|
def Layout ( self, nbit, nword, type ) :
|
|
global adrange
|
|
|
|
HCELL = 50
|
|
|
|
# placement des lignes de bit en dessous des buffers
|
|
bottom = 0
|
|
|
|
sym1 = NOSYM
|
|
sym2 = SYM_X
|
|
for i in range ( nbit ) :
|
|
if i % 2 : # lignes impaires
|
|
sym1 = SYM_Y
|
|
sym2 = SYMXY
|
|
else : # lignes paires
|
|
sym1 = NOSYM
|
|
sym2 = SYM_X
|
|
|
|
Place ( self.In[i], sym1, XY ( 0, bottom + i * HCELL ) )
|
|
|
|
for j in range ( 0, nword, 2 ) :
|
|
if j == 0 and ( type == 1 or type == 3 ) : PlaceRight ( self.Bit[i][j], sym1 )
|
|
else : PlaceRight ( self.Bit[i][j], sym1 )
|
|
|
|
PlaceRight ( self.Bit[i][j + 1], sym2 )
|
|
|
|
PlaceRight ( self.Out[i], sym1 )
|
|
|
|
# s_placement de la ligne contenant les buffers
|
|
bottom = nbit * HCELL
|
|
|
|
Place ( self.InBuf, NOSYM, XY ( 0, bottom ) )
|
|
|
|
for j in range ( 0, nword, 2 ) :
|
|
PlaceRight ( self.Buf[j], NOSYM )
|
|
PlaceRight ( self.Buf[j + 1], SYM_X )
|
|
|
|
PlaceRight ( self.OutBuf, NOSYM )
|
|
|
|
# s_placement des cellules du decodeur ecriture
|
|
if type == 2 or type == 3 :
|
|
half = nword >> 1
|
|
|
|
# Premiere ligne decodeur ecriture
|
|
bottom = ( nbit + 2 ) * HCELL
|
|
|
|
Place ( self.Adw0, NOSYM, XY ( 0, bottom ) )
|
|
|
|
for j in range ( half ) :
|
|
PlaceRight ( self.SelW[2 * j], SYM_X )
|
|
PlaceRight ( self.SelW[2 * j + 1], NOSYM )
|
|
|
|
PlaceRight ( self.Wen, NOSYM )
|
|
|
|
# Deuxieme ligne decodeur ecriture
|
|
bottom = ( nbit + 3 ) * HCELL
|
|
|
|
if adrange == 5 : # adresse sur 5 bits
|
|
Place ( self.Adw12, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand4W[j], SYM_Y, FIXED )
|
|
PlaceRight ( self.Adw34, SYMXY )
|
|
|
|
if adrange == 4 : # adresse sur 4 bits
|
|
Place ( self.Adw12, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand3W[j], SYM_Y )
|
|
PlaceRight ( self.Adw3, SYMXY )
|
|
|
|
if adrange == 3 : # adresse sur 3 bits
|
|
Place ( self.Adw1, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand2W[j], SYM_Y )
|
|
PlaceRight ( self.Adw2, SYMXY )
|
|
|
|
# s_placement des cellules du decodeur lecture A
|
|
if type == 2 or type == 3 :
|
|
half = nword >> 1
|
|
|
|
# Premiere ligne decodeur lecture A
|
|
bottom = ( nbit + 4 ) * HCELL
|
|
|
|
Place ( self.Adra0, NOSYM, XY ( 0, bottom ) )
|
|
|
|
for j in range ( half ) :
|
|
PlaceRight ( self.SelRa[2 * j], NOSYM )
|
|
PlaceRight ( self.SelRa[2 * j + 1], SYM_X )
|
|
|
|
PlaceRight ( self.RenA, NOSYM )
|
|
|
|
# Deuxieme ligne decodeur lecture A
|
|
bottom = ( nbit + 5 ) * HCELL
|
|
|
|
if adrange == 5 : # adresse sur 5 bits
|
|
Place ( self.Adra12, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand4Ra[j], SYM_Y )
|
|
PlaceRight ( self.Adra34, SYMXY )
|
|
|
|
if adrange == 4 : # adresse sur 4 bits
|
|
Place ( self.Adra12, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand3Ra[j], SYM_Y )
|
|
PlaceRight ( self.Adra3, SYMXY )
|
|
|
|
if adrange == 3 : # adresse sur 3 bits
|
|
Place ( self.Adra1, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand2Ra[j], SYM_Y )
|
|
PlaceRight ( self.Adra2, SYMXY )
|
|
|
|
# s_placement des cellules du decodeur lecture B
|
|
if type == 2 or type == 3 :
|
|
half = nword >> 1
|
|
|
|
# Premiere ligne decodeur lecture A
|
|
bottom = ( nbit + 6 ) * HCELL
|
|
|
|
Place ( self.Adrb0, NOSYM, XY ( 0, bottom ) )
|
|
|
|
for j in range ( half ) :
|
|
PlaceRight ( self.SelRb[2 * j], NOSYM )
|
|
PlaceRight ( self.SelRb[2 * j + 1], SYM_X )
|
|
|
|
PlaceRight ( self.RenB, NOSYM )
|
|
|
|
# Deuxieme ligne decodeur lecture A
|
|
bottom = ( nbit + 7 ) * HCELL
|
|
|
|
if adrange == 5 : # adresse sur 5 bits
|
|
Place ( self.Adrb12, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand4Rb[j], SYM_Y )
|
|
PlaceRight ( self.Adrb34, SYMXY )
|
|
|
|
if adrange == 4 : # adresse sur 4 bits
|
|
Place ( self.Adrb12, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand3Rb[j], SYM_Y )
|
|
PlaceRight ( self.Adrb3, SYMXY )
|
|
|
|
if adrange == 3 : # adresse sur 3 bits
|
|
Place ( self.Adrb1, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( half ) : PlaceRight ( self.Nand2Rb[j], SYM_Y )
|
|
PlaceRight ( self.Adrb2, SYMXY )
|
|
|
|
|
|
|
|
## VBE ##
|
|
#########
|
|
def Vbe ( self ) :
|
|
print 'RF2 behavior not implemented'
|
|
|
|
|
|
|
|
|
|
|
|
#####################
|
|
##### DPGEN_RF2 #####
|
|
#####################
|
|
class DpgenRf2 ( top_rf2 ) :
|
|
|
|
def Interface ( self ) :
|
|
top_rf2.Interface ( self, self._param['nbit'], self._param['nword'], 0 )
|
|
|
|
def Netlist ( self ) :
|
|
top_rf2.Netlist ( self, self._param['nbit'], self._param['nword'], 0 )
|
|
|
|
def Layout ( self ) :
|
|
top_rf2.Layout ( self, self._param['nbit'], self._param['nword'], 0 )
|
|
|
|
|
|
#######################
|
|
##### DPGEN_RF2R0 #####
|
|
#######################
|
|
class DpgenRf2r0 ( top_rf2 ) :
|
|
|
|
def Interface ( self ) :
|
|
top_rf2.Interface ( self, self._param['nbit'], self._param['nword'], 1 )
|
|
|
|
def Netlist ( self ) :
|
|
top_rf2.Netlist ( self, self._param['nbit'], self._param['nword'], 1 )
|
|
|
|
def Layout ( self ) :
|
|
top_rf2.Layout ( self, self._param['nbit'], self._param['nword'], 1 )
|
|
|
|
|
|
######################
|
|
##### DPGEN_RF2D #####
|
|
######################
|
|
class DpgenRf2d ( top_rf2 ) :
|
|
|
|
def Interface ( self ) :
|
|
top_rf2.Interface ( self, self._param['nbit'], self._param['nword'], 2 )
|
|
|
|
def Netlist ( self ) :
|
|
top_rf2.Netlist ( self, self._param['nbit'], self._param['nword'], 2 )
|
|
|
|
def Layout ( self ) :
|
|
top_rf2.Layout ( self, self._param['nbit'], self._param['nword'], 2 )
|
|
|
|
|
|
########################
|
|
##### DPGEN_RF2DR0 #####
|
|
########################
|
|
class DpgenRf2dr0 ( top_rf2 ) :
|
|
|
|
def Interface ( self ) :
|
|
top_rf2.Interface ( self, self._param['nbit'], self._param['nword'], 3 )
|
|
|
|
def Netlist ( self ) :
|
|
top_rf2.Netlist ( self, self._param['nbit'], self._param['nword'], 3 )
|
|
|
|
def Layout ( self ) :
|
|
top_rf2.Layout ( self, self._param['nbit'], self._param['nword'], 3 )
|