701487247d
* Bug: In CRL Core, in VectorPortMap::VhdlPortMap(), if the connection
was made to *non-contiguous* bits of an otherwise *contiguous* vector,
it was using a span instead of the separate bits. Now check that
bits are contiguous (delta: +1/-1) and the delta do not change of
sign.
* Change: In Etesian & Kite, the Python interface function ::setViewer()
was checking that the argument was indeed a CellViewer, but in text
mode it is None. Now, silently ignore the argument if it cannot be
converted into CellViewer.
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| cmake_modules | ||
| src | ||
| CMakeLists.txt | ||