coriolis/kite
Jean-Paul Chaput 6d366a08bc Etesian integration with Chip & ClockTree plugins.
* New: In Hurricane, in DebugSession, add a new method to activate the
    trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
    no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
    the flattening of the clock net(s). For more safety perform the
    DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
    DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
    needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
    if some cells are already placed. Typically the buffers of a clock
    tree.
      Pass the correct orienation to row_compatible_orientation().
      Do not try to add feeds in the ISPD05 benchmarks. For now the
    benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
    to be routed as an ordinary signal when the clock tree is not
    used.
* New: In Kite, in BuildPowerRails, management & detection for the
    pre-routed clock.
      In KiteEngine constructor, early initialization of the blockage
    net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
    configuration parameter 'clockTree.placerEngine' to select between
    Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
    in the vertical layer to prevent the router to use the vertical
    tracks in under the prower lines (for example, blockage in M3
    with power line M5).
      In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
    the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
    signals and *not* the power pad.
      Add more meaningful error messages if a pad global signal is
    not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
    that is *from the bottom of the cell AB* (not from 'zero').
2015-02-24 13:13:17 +01:00
..
cmake_modules * All tools: 2010-05-19 14:31:10 +00:00
doc Correction of SoC.css, adjust the look of the class index big letters. 2014-06-10 00:04:48 +02:00
src Etesian integration with Chip & ClockTree plugins. 2015-02-24 13:13:17 +01:00
CMakeLists.txt Starting to implement support for Windows/Cygwin. 2014-07-13 13:14:49 +02:00