coriolis/crlcore
Jean-Paul Chaput 51a3236962 Add management of fixed wires to Kite (for chip ClockTree)
* Change: In Hurricane, in Plug::setNet(), more informative error messages.
* Change: In Hurricane, In Segment, more informative error messages.
* Change: In Hurricane, In DeepNet, accessor for the Net occurrence.
* Bug: In Katabatic, in AutoSegment::create(), error message uses correct
    variables (vertical was using horizontal)...
* Change: In Kite, in BuildPowerRails, already existing wiring in instances
    is copied up as blockage. Uses blockage layer instead of true layer
    (it was a bug).
* Change: In Kite, in BuildPreRouted, consider as manual global routing
    nets with only default wiring (default size wire & contacts).
    Non-default routing is flagged as fixed (with the NetRoutingState
    property).
2014-08-15 19:26:49 +02:00
..
cmake_modules * ./crlcore: 2013-03-13 13:38:38 +00:00
doc Correction of SoC.css, adjust the look of the class index big letters. 2014-06-10 00:04:48 +02:00
etc Added support for MOSIS 180nm SCMOS technology (SCN6M_DEEP). 2014-08-03 16:36:21 +02:00
src Add management of fixed wires to Kite (for chip ClockTree) 2014-08-15 19:26:49 +02:00
CMakeLists.txt Starting to implement support for Windows/Cygwin. 2014-07-13 13:14:49 +02:00