333 lines
17 KiB
ReStructuredText
333 lines
17 KiB
ReStructuredText
.. -*- Mode: rst -*-
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.. include:: ../etc/definitions.rst
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.. URLs that changes between the various backends.
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.. _Stratus Documentation: file:///usr/share/doc/coriolis2/en/html/stratus/index.html
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.. |ChipStructure-1| image:: ./images/chip-structure-1.png
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:alt: Chip Top Structure
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:align: middle
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:width: 90%
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.. _Python Interface to Coriolis:
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Python Interface for |Hurricane| / |Coriolis|
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=============================================
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The (almost) complete interface of |Hurricane| is exported as a |Python| module
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and some part of the other components of |Coriolis| (each one in a separate
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module). The interface has been made to mirror as closely as possible the
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C++ one, so the C++ doxygen documentation could be used to write code with
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either languages.
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`Summary of the C++ Documentation <file:../../../index.html>`_
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A script could be run directly in text mode from the command line or through
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the graphical interface (see :ref:`Python Scripts in Cgt`).
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Asides for this requirement, the python script can contain anything valid
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in |Python|, so don't hesitate to use any package or extention.
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Small example of Python/Stratus script: ::
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from Hurricane import *
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from Stratus import *
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def doSomething ():
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# ...
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return
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def ScriptMain ( **kw ):
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editor = None
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if kw.has_key('editor') and kw['editor']:
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editor = kw['editor']
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stratus.setEditor( editor )
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doSomething()
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return
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if __name__ == "__main__" :
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kw = {}
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success = ScriptMain( **kw )
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shellSuccess = 0
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if not success: shellSuccess = 1
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sys.exit( shellSuccess )
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ScriptMain ()
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This typical script can be executed in two ways:
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#. Run directly as a |Python| script, thanks to the ::
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if __name__ == "__main__" :
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part (this is standart |Python|). It is a simple adapter that will
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calls :cb:`ScriptMain()`.
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#. Through |cgt|, either in text or graphical mode. In that case, the
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:cb:`ScriptMain()` is directly called trough a sub-interpreter.
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The arguments of the script are passed through the ``**kw`` dictionnary.
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+----------------------+-----------------------------------------------+
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| \*\*kw Dictionnary |
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+----------------------+-----------------------------------------------+
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| Parameter Key/Name | Contents type |
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+======================+===============================================+
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| ``'cell'`` | A Hurricane cell on which to work. Depending |
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| | on the context, it may be ``None``. |
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| | For example, when run from |cgt|, it the cell |
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| | currently loaded in the viewer, if any. |
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+----------------------+-----------------------------------------------+
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| ``'editor'`` | The viewer from which the script is run, when |
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| | lauched through |cgt|. |
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+----------------------+-----------------------------------------------+
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Plugins
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~~~~~~~
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Plugins are |Python| scripts specially crafted to integrate with |cgt|.
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Their entry point is a :cb:`ScriptMain()` method as described in
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`Python Interface to Coriolis`_. They can be called by user scripts
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through this method.
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Chip Placement
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--------------
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Automatically perform the placement of a complete chip. This plugin, as well
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as the other P&R tools expect a specific top-level hierarchy for the design.
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The top-level hierarchy must contains the instances of all the I/O pads and
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**exactly one** instance of the chip's core model.
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|bcenter| |ChipStructure-1| |ecenter|
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The designer must provide a configuration file that define the rules for the
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placement of the top-level hierarchy (that is, the pads and the core).
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This file must be named after the chip's name, by appending ``_chip.py``
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(obviously, it is a |Python| file). For instance if the chip netlist file
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is called ``amd2901_crl.vst``, then the configuration file must be named
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``amd2901_crl_chip.vst``.
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Example of chip placement configuration file (for ``AM2901``): ::
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chip = \
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{ 'pads.south' : [ 'p_a3' , 'p_a2' , 'p_a1' , 'p_r0'
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, 'p_vddick0', 'p_vssick0', 'p_a0' , 'p_i6'
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, 'p_i8' , 'p_i7' , 'p_r3' ]
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, 'pads.east' : [ 'p_zero' , 'p_i0' , 'p_i1' , 'p_i2'
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, 'p_vddeck0', 'p_vsseck0', 'p_q3' , 'p_b0'
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, 'p_b1' , 'p_b2' , 'p_b3' ]
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, 'pads.north' : [ 'p_noe' , 'p_y3' , 'p_y2' , 'p_y1'
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, 'p_y0' , 'p_vddeck1', 'p_vsseck1', 'p_np'
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, 'p_ovr' , 'p_cout' , 'p_ng' ]
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, 'pads.west' : [ 'p_cin' , 'p_i4' , 'p_i5' , 'p_i3'
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, 'p_ck' , 'p_d0' , 'p_d1' , 'p_d2'
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, 'p_d3' , 'p_q0' , 'p_f3' ]
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, 'core.size' : ( 1500, 1500 )
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, 'chip.size' : ( 3000, 3000 )
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, 'chip.clockTree' : True
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}
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The file must contain *one dictionnary* named ``chip``.
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+----------------------+-------------------------------------------------------+
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| Chip Dictionnary |
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+----------------------+-------------------------------------------------------+
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| Parameter Key/Name | Value/Contents type |
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+======================+=======================================================+
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| ``'pad.south'`` | Ordered list (left to right) of pad instances names |
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| | to put on the south side of the chip |
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+----------------------+-------------------------------------------------------+
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| ``'pad.east'`` | Ordered list (down to up) of pad instances names |
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| | to put on the east side of the chip |
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+----------------------+-------------------------------------------------------+
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| ``'pad.north'`` | Ordered list (left to right) of pad instances names |
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| | to put on the north side of the chip |
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+----------------------+-------------------------------------------------------+
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| ``'pad.west'`` | Ordered list (down to up) of pad instances names |
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| | to put on the west side of the chip |
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+----------------------+-------------------------------------------------------+
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| ``'core.size'`` | The size of the core (to be used by the placer) |
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+----------------------+-------------------------------------------------------+
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| ``'chip.size'`` | The size of the whole chip. The sides must be great |
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| | enough to accomodate all the pads |
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+----------------------+-------------------------------------------------------+
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| ``'chip.clockTree'`` | Whether to generate a clock tree or not. This calls |
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| | the ClockTree plugin |
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+----------------------+-------------------------------------------------------+
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Configuration parameters, defaults are defined in ``etc/coriolis2/<STECHNO>/plugins.conf``.
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+-----------------------------------+------------------+----------------------------+
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| Parameter Identifier | Type | Default |
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+===================================+==================+============================+
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| **Chip Plugin Parameters** |
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+-----------------------------------+------------------+----------------------------+
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|``chip.block.rails.count`` | TypeInt | :cb:`5` |
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| +------------------+----------------------------+
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| | The minimum number of rails around the core |
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| | block. Must be odd and suppérior to 5. |
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| | One rail for the clock and at least two pairs |
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| | of power/grounds |
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+-----------------------------------+------------------+----------------------------+
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|``chip.block.rails.hWidth`` | TypeInt | :cb:`12` |
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| +------------------+----------------------------+
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| | The horizontal with of the rails |
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+-----------------------------------+------------------+----------------------------+
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|``chip.block.rails.vWidth`` | TypeInt | :cb:`12` |
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| +------------------+----------------------------+
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| | The vertical with of the rails |
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+-----------------------------------+------------------+----------------------------+
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|``chip.block.rails.hSpacing`` | TypeInt | :cb:`6` |
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| +------------------+----------------------------+
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| | The spacing, *edge to edge* of two adjacent |
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| | horizontal rails |
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+-----------------------------------+------------------+----------------------------+
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|``chip.block.rails.vSpacing`` | TypeInt | :cb:`6` |
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| +------------------+----------------------------+
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| | The spacing, *edge to edge* of two adjacent |
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| | vertical rails |
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+-----------------------------------+------------------+----------------------------+
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|``chip.pad.pck`` | TypeString | :cb:`pck_px` |
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| +------------------+----------------------------+
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| | The model name of the pad connected to the |
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| | chip external clock |
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+-----------------------------------+------------------+----------------------------+
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|``chip.pad.pvddeck`` | TypeString | :cb:`pvddeck_px` |
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| +------------------+----------------------------+
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| | The model name of the pad connected to the |
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| | ``vdde`` (external power) and suppling it to |
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| | the core |
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+-----------------------------------+------------------+----------------------------+
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|``chip.pad.pvsseck`` | TypeString | :cb:`pvsseck_px` |
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| +------------------+----------------------------+
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| | The model name of the pad connected to the |
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| | ``vsse`` (external ground) and suppling it to |
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| | the core |
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+-----------------------------------+------------------+----------------------------+
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|``chip.pad.pvddick`` | TypeString | :cb:`pvddick_px` |
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| +------------------+----------------------------+
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| | The model name of the pad connected to the |
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| | ``vddi`` (internal power) and suppling it to |
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| | the core |
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+-----------------------------------+------------------+----------------------------+
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|``chip.pad.pvssick`` | TypeString | :cb:`pvssick_px` |
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| +------------------+----------------------------+
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| | The model name of the pad connected to the |
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| | ``vssi`` (internal ground) and suppling it to |
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| | the core |
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+-----------------------------------+------------------+----------------------------+
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.. note::
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If no clock tree is generated, then the clock rail is *not* created.
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So even if the requested number of rails ``chip.block.rails.count`` is, say 5,
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only four rails (2* ``power``, 2* ``ground``) will be generateds.
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Clock Tree
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----------
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Insert a clock tree into a block. The clock tree uses the H strategy.
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The clock net is splitted into sub-nets, one for each branch of the
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tree.
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* On **chips** design, the sub-nets are createds in the model of the
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core block (then trans-hierarchically flattened to be shown at
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chip level).
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* On **blocks**, the sub nets are created directly in the top block.
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* The sub-nets are named according to a simple geometrical scheme.
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A common prefix ``ck_htree``, then one postfix by level telling
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on which quarter of plane the sub-clock is located:
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#. ``_bl``: bottom left plane quarter.
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#. ``_br``: bottom right plane quarter.
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#. ``_tl``: top left plane quarter.
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#. ``_tr``: top right plane quarter.
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We can have ``ck_htree_bl``, ``ck_htree_bl_bl``, ``ch_htree_bl_tl`` and so on.
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The clock tree plugin works in four steps:
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#. Build the clock tree: creates the top-block abutment box, compute the
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levels of H tree neededs and place the clock buffers.
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#. Once the clock buffers are placed, calls the placer (|etesian|) to place
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the ordinary standart cells, whithout disturbing clock H-tree buffers.
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#. At this point we know the exact positions of all the DFFs, so we can
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connect them to the nearest H-tree leaf clock signal.
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#. Leaf clock signals that are not connecteds to any DFFs are removed.
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Netlist reorganisation:
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* Obviously the top block or chip core model netlist is modificated to
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contains all the clock sub-nets. The interface is *not* changed.
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* If the top block contains instances of other models *and* those models
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contains DFFs that get re-connecteds to the clock sub-nets (from the
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top level). Change both the model netlist and interface to propagate
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the relevant clock sub-nets to the instanciated model. The new model
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with the added clock signal is renamed with a ``_clocked`` suffix.
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For example, the sub-block model ``ram.vst`` will become ``ram_clocked.vst``.
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.. note::
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If you are to re-run the clock tree plugin on a netlist, be careful
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to erase any previously generated ``_clocked`` file (both netlist and
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layout: ``rm *.clocked.{ap,vst}``). And restart |cgt| to clear it's
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memory cache.
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Configuration parameters, defaults are defined in ``etc/coriolis2/<STECHNO>/plugins.conf``.
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+-----------------------------------+------------------+----------------------------+
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| Parameter Identifier | Type | Default |
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+===================================+==================+============================+
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| **ClockTree Plugin Parameters** |
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+-----------------------------------+------------------+----------------------------+
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|``clockTree.minimumSide`` | TypeInt | :cb:`300` |
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| +------------------+----------------------------+
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| | The minimum size below which the clock tree |
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| | will stop to perform quadri-partitions |
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+-----------------------------------+------------------+----------------------------+
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|``clockTree.buffer`` | TypeString | :cb:`buf_x2` |
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| +------------------+----------------------------+
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| | The buffer model to use to drive sub-nets |
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+-----------------------------------+------------------+----------------------------+
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|``clockTree.placerEngine`` | TypeString | :cb:`Etesian` |
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| +------------------+----------------------------+
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| | The placer to use. Other value is ``Mauka`` |
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| | the simulated annealing placer which will go |
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| | into retirement very soon |
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+-----------------------------------+------------------+----------------------------+
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Recursive-Save (RSave)
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----------------------
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Perform a recursive top down save of all the models from the top cell
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loaded in |cgt|. Force a write of any non-terminal model. This plugin is used
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by the clock tree plugin after the netlist clock sub-nets creation.
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A Simple Example: AM2901
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~~~~~~~~~~~~~~~~~~~~~~~~
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To illustrate the capabilities of |Coriolis| tools and |Python| scripting, a small
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example, derived from the |Alliance| :cb:`AM2901` is supplied.
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This example contains only the synthetized netlists and the :cb:`doChip.py` script
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which perform the whole P&R of the design.
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You can generate the chip using one of the following method:
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#. **Command line mode:** directly run the script: ::
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dummy@lepka:AM2901> ./doChip -V --cell=amd2901
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#. **Graphic mode:** launch |cgt|, load chip netlist ``amd2901`` (the top cell)
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then run the |Python| script :cb:`doChip.py`.
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.. note::
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Between two consecutive run, be sure to erase the netlist/layout generateds: ::
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dummy@lepka:AM2901> rm *clocked*.vst *.ap
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