155 lines
6.1 KiB
Python
155 lines
6.1 KiB
Python
#!/usr/bin/env python
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# -*- coding: utf-8 -*-
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#
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# This file is part of the Coriolis Software.
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# Copyright (c) UPMC 2019-2018, All Rights Reserved
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#
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# +-----------------------------------------------------------------+
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# | C O R I O L I S |
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# | C u m u l u s - P y t h o n T o o l s |
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# | |
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# | Author : Jean-Paul CHAPUT |
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# | E-mail : Jean-Paul.Chaput@lip6.fr |
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# | =============================================================== |
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# | Python : "./plugins/core2chip/cmos.py" |
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# +-----------------------------------------------------------------+
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import re
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from Hurricane import DbU
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from Hurricane import DataBase
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from Hurricane import UpdateSession
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from Hurricane import Breakpoint
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from Hurricane import Transformation
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from Hurricane import Instance
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from Hurricane import Net
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import Viewer
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from CRL import Catalog
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from CRL import AllianceFramework
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from helpers.io import ErrorMessage
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from core2chip.core2chip import IoPad
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from core2chip.core2chip import CoreToChip
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class cmos ( CoreToChip ):
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def __init__ ( self, core ):
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CoreToChip.__init__ ( self, core )
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self.ringNetNames = [ 'vsse', 'vssi', 'vdde', 'vddi', ('cki', 'ck') ]
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self.ioPadInfos = { IoPad.IN : CoreToChip.IoPadInfo( 'pi_px' , 'pad', ['t',] )
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, IoPad.OUT : CoreToChip.IoPadInfo( 'po_px' , 'pad', ['i',] )
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, IoPad.TRI_OUT : CoreToChip.IoPadInfo( 'pot_px' , 'pad', ['i', 'b' ] )
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, IoPad.BIDIR : CoreToChip.IoPadInfo( 'piot_px', 'pad', ['i', 't', 'b' ] )
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}
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self._getPadLib()
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return
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def _getPadLib ( self ):
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self.padLib = AllianceFramework.get().getLibrary( "pxlib" )
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if not self.padLib:
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message = [ 'CoreToChip.cmos._getPadLib(): Unable to find Alliance "pxlib" library' ]
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raise ErrorMessage( 1, message )
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return
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def getNetType ( self, netName ):
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if netName.startswith('vss'): return Net.Type.GROUND
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if netName.startswith('vdd'): return Net.Type.POWER
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if netName in ('cki', 'ck'): return Net.Type.CLOCK
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return Net.Type.LOGICAL
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def isGlobal ( self, netName ):
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if netName in self.ringNetNames: return True
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return False
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def getCell ( self, masterCellName ):
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#cell = self.padLib.getCell( masterCellName )
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cell = AllianceFramework.get().getCell( masterCellName, Catalog.State.Views )
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if not cell:
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raise ErrorMessage( 1, 'cmos.getCell(): I/O pad library "%s" does not contain cell named "%s"' \
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% (self.padLib.getName(),masterCellName) )
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return cell
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def _buildGroundPads ( self, ioNet ):
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ioNet.buildNets()
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vssi = self.chip.getNet( 'vssi' )
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vssi.setExternal( True )
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vssi.setGlobal ( True )
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vssi.setType ( Net.Type.GROUND )
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vssi.merge( ioNet.chipIntNet )
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ioNet.chipIntNet = vssi
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vsse = self.chip.getNet( 'vsse' )
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vsse.setExternal( True )
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vsse.setGlobal ( True )
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vsse.setType ( Net.Type.GROUND )
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vsse.merge( ioNet.chipExtNet )
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ioNet.chipExtNet = vsse
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pads = []
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pads.append( Instance.create( self.chip
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, 'p_' + ioNet.padInstanceName + 'ick_%d' % self.groundPadCount
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, self.getCell('pvssick_px') ) )
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pads.append( Instance.create( self.chip
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, 'p_' + ioNet.padInstanceName + 'eck_%d' % self.groundPadCount
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, self.getCell('pvsseck_px') ) )
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CoreToChip._connect( pads[0], ioNet.chipIntNet, 'vssi' )
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CoreToChip._connect( pads[1], ioNet.chipExtNet, 'vsse' )
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for pad in pads: self._connectRing( pad )
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self.groundPadCount += 1
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self.chipPads += pads
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return
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def _buildPowerPads ( self, ioNet ):
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ioNet.buildNets()
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vddi = self.chip.getNet( 'vddi' )
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vddi.setExternal( True )
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vddi.setGlobal ( True )
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vddi.setType ( Net.Type.POWER )
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vddi.merge( ioNet.chipIntNet )
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ioNet.chipIntNet = vddi
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vdde = self.chip.getNet( 'vdde' )
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vdde.setExternal( True )
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vdde.setGlobal ( True )
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vdde.setType ( Net.Type.POWER )
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vdde.merge( ioNet.chipExtNet )
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ioNet.chipExtNet = vdde
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pads = [ ]
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pads.append( Instance.create( self.chip
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, 'p_' + ioNet.padInstanceName + 'ick_%d' % self.powerPadCount
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, self.getCell('pvddick_px') ) )
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pads.append( Instance.create( self.chip
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, 'p_' + ioNet.padInstanceName + 'eck_%d' % self.powerPadCount
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, self.getCell('pvddeck_px') ) )
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CoreToChip._connect( pads[0], ioNet.chipIntNet, 'vddi' )
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CoreToChip._connect( pads[1], ioNet.chipExtNet, 'vdde' )
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for pad in pads: self._connectRing( pad )
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self.powerPadCount += 1
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self.chipPads += pads
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return
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def _buildClockPads ( self, ioNet ):
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ioNet.buildNets()
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pads = [ ]
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pads.append( Instance.create( self.chip
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, 'p_' + ioNet.padInstanceName + '_%d' % self.clockPadCount
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, self.getCell('pck_px') ) )
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CoreToChip._connect( pads[0], ioNet.chipExtNet, 'pad' )
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for pad in pads: self._connectRing( pad )
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self.clockPadCount += 1
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self.chipPads += pads
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p = re.compile( r'pv[ds]{2}[ei]ck_px' )
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for pad in self.chipPads:
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if p.match( pad.getMasterCell().getName() ):
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CoreToChip._connect( pad, ioNet.chipIntNet, 'cko' )
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return
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