coriolis

History

Jean-Paul Chaput 81f3b2fa56 * ./cumulus: - Bug: In placeandroute.py/createGrid(), VIAs of the big clock grid must have the same width as the wires (12l). But due to the layer extension the VIA side must be of 11l. - Bug: In placeandroute.py/createGrid(), wires connecting cell clock pin to the clock trunk must respect the preferred routing direction. The only exception being when the wire is completly enclosed under the trunk wire. This is for the obstacle stage of the detailed router.	2012-01-02 21:20:36 +00:00
..
src	* ./cumulus:	2012-01-02 21:20:36 +00:00
CMakeLists.txt	* <All Tools>/CMakeLists.txt:	2011-02-15 13:16:15 +00:00

Jean-Paul Chaput 81f3b2fa56 * ./cumulus:

- Bug: In placeandroute.py/createGrid(), VIAs of the big clock grid must
        have the same width as the wires (12l). But due to the layer extension
        the VIA side must be of 11l.
    - Bug: In placeandroute.py/createGrid(), wires connecting cell clock pin
        to the clock trunk must respect the preferred routing direction.
        The only exception being when the wire is completly enclosed under
        the trunk wire. This is for the obstacle stage of the detailed router.

2012-01-02 21:20:36 +00:00

src

* ./cumulus:

2012-01-02 21:20:36 +00:00

CMakeLists.txt

* <All Tools>/CMakeLists.txt:

2011-02-15 13:16:15 +00:00