coriolis/crlcore
Jean-Paul Chaput 0217ca1f26 Force VST driver to clear all Vhdl properties after running.
* Change: In CRL::vstDriver(), remove all Vhdl properties after running.
    The properties are not updated if the cell (Entity) change, so the
    next time it is called, an incomplete or incoherent state was saved
    (for example, incomplete "port map"). Removing all properties is
    less efficient but works.
* Cleanup: In CRL/helpers/overlay, remove forgotten debug message.
2020-10-23 22:26:50 +02:00
..
cmake_modules Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
doc Full update of the generated documentation. 2020-04-27 14:14:03 +02:00
etc Change the type of parameters for Etesian from Percentage to Double. 2020-10-18 23:17:00 +02:00
python Force VST driver to clear all Vhdl properties after running. 2020-10-23 22:26:50 +02:00
src Force VST driver to clear all Vhdl properties after running. 2020-10-23 22:26:50 +02:00
CMakeLists.txt Groudwork for routing density driven placement. Compliance with clang 5.0.1. 2019-12-09 01:57:44 +01:00