\begin{itemize}
    \item Name : DpgenFifo -- Fifo Macro-Generator
    \item Description : Generates a FIFO pf \verb-ergNumber- words of \verb-n- bits named \verb-modelname-.
    \item How it works :
    \begin{itemize}
        \item datain0 and datain1 : the two write busses. Only one is used to actually write the FIFO, it is selected by the sel signal.
        \item sel : when set to \verb-zero- the datain0 is used to write the register word, otherwise it will be datain1.
        \item r, rok : set r when a word is requested, rok tells that a word has effectively been popped (rok == not empty).
        \item w, wok : set w when a word is pushed, wok tells that the word has effectively been pushed (wok == not full).
    \end{itemize}
    \item Terminal Names :
    \begin{itemize}
        \item ck : clock signal (input, 1 bit)
        \item reset : reset signal (input, 1 bit)
        \item r : read requested (input, 1 bit)
        \item w : write requested (input, 1 bit)
        \item rok : read acknowledge (output, 1 bit)
        \item wok : write acknowledge (output, 1 bit) 
        \item sel : select the write bus (input, 1 bit)
        \item datain0 : first write bus (input, \verb-n- bits)
        \item datain1 : second write bus (input, \verb-n- bits)
        \item dataout : read bus (output, \verb-n- bits)
        \item vdd : power
        \item vss : ground
    \end{itemize}
    \item Parameters : Parameters are given with a map called \verb-param-.
    \begin{itemize}
        \item nbit : Defines the size of the words (even, between 2 and 64)
        \item nword : Defines the number of words (even, between 4 and 32)
    \end{itemize}
%    \item Behavior :
%\begin{verbatim}
%\end{verbatim}
    \item Example :
\begin{verbatim}
class myClass ( Model ) :
    global nbit, nword
    nbit  = 4
    nword = 16

  def Interface ( self ) :  

    self._ck      = LogicIn    (       "ck",       1 )
    self._reset   = LogicIn    (    "reset",       1 )
    self._r       = LogicIn    (        "r",       1 )
    self._w       = LogicIn    (        "w",       1 )
    self._rok     = LogicInOut (      "rok",       1 )
    self._wok     = LogicInOut (      "wok",       1 )
    self._sel     = LogicIn    (      "sel",       1 )
    
    self._datain0 = LogicIn    (  "datain0",    nbit )
    self._datain1 = LogicIn    (  "datain1",    nbit )
    self._dataout = LogicOut   (  "dataout",    nbit ) 
    
    self._vdd   = VddIn    ( "vdd" )
    self._vss   = VssIn    ( "vss" )
    
  def Netlist ( self ) :
      
    Inst ( 'DpgenFifo'
         , param = { 'nword'   : nword
                   , 'nbit'    : nbit
                   }
         , map   = { 'ck'      : self._ck
                   , 'reset'   : self._reset
                   , 'r'       : self._r
                   , 'w'       : self._w
                   , 'rok'     : self._rok
                   , 'wok'     : self._wok
                   , 'sel'     : self._sel
                   , 'datain0' : self._datain0
                   , 'datain1' : self._datain1
                   , 'dataout' : self._dataout
                   , 'vdd'     : self._vdd
                   , 'vss'     : self._vss
                   }
         )
\end{verbatim}
\end{itemize}