The H-Tree support is now allowed for any net, not only the clocks and
not only top-level nets. This allow to better management of the LS180
internal clock signal.
* New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
of the function to allow the user to select nets that will *not*
be flattened. This makes the NoClockFlatten flag effectively obsolete,
we keep it for backward compatibility.
The net names can be of non top level ones. In that case, they must
use the name an HyperNet will get (the Occurrence name). For example:
"instance1.instance2.deep_net_name".
* New: In PyCell, update the wrapper for the new parameter of flattenNets(),
new utility function pyListToStringSet() to translate a Python list into
a C++ set of names.
* New: In EtesianEngine, add support for a list of nets to be excluded
from the flattening procedure. Those excluded nets will also be
excludeds from the Coloquinte nets *and* HFNS synthesis, as they
are likely to be manageds by a H-Tree.
* Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
flagged as manually detailed route.
* New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
on nets that are already fixed or detaled route. This replace the
clock exclusion.
* New: In cumulus/plugins.{block,htree,chip}, replace the concept
of clock-tree by the more generic H-Tree. That is, we can ask the P&R
to create H-Tree on any net of the design, not only the ones matcheds
as clock. The net does not even need to be top-level.
This is to manage the PLL internal clock generated by the PLL in
the LS180 chip.
Start to change all reference to "clock" into "H-Tree".
* Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
there was an inversion of the H & V routing gauges to compute the
track into which put the H-Tree center to corona edge wiring.
This was causing tracks to be used twice, seen in the ao68000 test
bench.
* New: In Anabatic::DiodeWire, use "antennaDiodeMaxWL" to compute the number
of diodes to insert in a wire only cluster. Use boxes instead of segments
to define the area as segments can be splitted by the diodes inserteds
at the DiodeRps stage.
* New: In DiodeWire::createDiodes(), specific diode insertion method.
Try to instert first in long horizontal wires.
When a long *horizontal* wire connect to a cluster, an antenna effect
may be created *before* the METAL3 is deposited, if the cluster's diode
is not *directly* connected to the gate through *only* METAL2. So, we
add a "forced halo" where the long horizontal connecting wires will be
broken by a diode *near* the gate. This problem do not occur for long
connecting METAL3, as the diode will be connected by then. Note that
we are hard-coding the gauge routing direction in the algorithm.
With that modification, only one antenna effect remains in LibreSOC
LS180. May be corrected by post-treatement.
* New: In Anabatic::DiodeCluster::mergeForcedhalo() add specific secondary
areas where diode must be insterted in addition to the one of the
RroutingPad cluster. To "isolate" the cluster from long horizontal
wires.
Protecting clusters of sinks is not enough. There can be very long
wires that far exceed the protection capacity of one diode. Instead
of putting a bunch of diodes near the sinks, we choose to put them
regularly along the interconncting wires.
With this approach we are down to 7 antenna violations on LibreSOC
LS180 test chip.
This will get less good results on arlet6502 & ao6800 because of the
core being a long way from the I/O pads. Should create jumpers on thoses,
but it is for later.
First part of the antenna effect protection : diode insertions.
Anabatic::antennaProtect(Net*) and it's supporting infrastructure
has been rewritten & simplificated. Must be used in conjuction
with the "Flexlib" bloat model of Etesian. A cursory description
of the algorithm has been added in the source file.
* New: GCell::hasNet() to tell if net is going through a GCell,
either as a straigth wire or has a local GContact (turn,
branch, terminal).
* New: Etesian::BloatFlexib class (tagged "Flexlib") suited for
flexlib uses. It is derived from "nsxlib".
To have enough space to insert all the wanted diodes, we
enlarge "mx2_x2" & "mx3_x2" of resp. 1 and 2 pitches.
This is an empiric finding, Yosys seems very fond of thoses
gates and we often see them underneath area where no space
was available to put a diode... May need some more fine grained
analysis.
* Change: In AutoSegment::canMoveUp(), hard code for FlexLib a track
reserve of one when trying to move up.
In FlexLib, the router promotes too easily METAL2 towards METAL4,
clogging the higher level. So we end up with the METAL2 level
under-saturated and the METAL4 over saturated, leading to routing
failures.
Now we assume that there is "one track less available" in METAL4.
As for now, solves the problem for LibreSOC.
* Bug: In NetBuilderHV::_do_xG_1PinM2(), for METAL2 pins on the EAST
side, we were computing the track from the XMax position of the
GCell. Now, with complete discoupling of the routing pitches and
GCell size, this is most of the time false.
Replace with a true computation of the last track of routing
area.
* Bug: In NetBuilderHV::_do_xG_1PinM2(), when the M2 pin is on the *east*
side and there are three globals, we must swap htee1 & htee2.
Otherwise, we the SW/NE contacts do not have the right numbers
of free segments attach.
* New: In AnabaticEngine::cleanupGlobal(), check that no global component
is left behind, sure sign that the global to detailed building went
wrong.
* New: In AnabaticEngine::_gutAnabatic(), perform progessive compaction
of segment of null length.
CAUTION: Reduced segments *may* not be null length segments.
They are "less or equal" than one perpandicular pitch and
can have their layer put into the perpandicular one.
They non-null one *must* be excluded for the compaction.
Null segments are compacted starting from the one connecteds to
non-null length segments. This is to avoid the compaction starting
in the middle of a whole set of zero-segments that will block further
compaction.
This behavior was causing "zero-length" segment on orphaned layers
that were causing minumal area DRC errors.
* Change: AutoSegment::canReduce() is modified so it now takes a flag
argument to tell it to look for collapisble zero-length segments.
* New: AutoSegment::getNonReduceds(): returns the number of non-zero
length segments connecteds to the current one.
* Change: In AutoSegment::reduceDoglegLayer(), use the perpandicular
width of the routing layer instead of the regular (parallel) one.
This was causing DRC errors.
* Change: In AutoSegment::canReduce(), no longer allow short METAL2
connected only to VIA12 to be reduced in METAL1, as we do not
control the METAL1 level of layers. This problem started to
show when connecting to diodes (antenna).
Should get rid of METAL1 DRC violations.
* Change: In AutoSegment::isMiddleStack(), reject configurations where
we have a Tee in the same direction as the segment. That is, (HTee + H)
or (VTee + V). It is unlikely that the two segments of the tee will
be of null size.
* Change: In AutoSegment::isMiddlestack(), we where previously only
detecting (turn+turn) or (turn+terminal) topologies. This was
too restrictive. Added (terminal+XTee) when the tee is perpandicular
to the segment, for example horizontal + VTee.
Fix minimal area DRC error in METAL2 for TSMC.
We use the segments extensions (dxTarget & dyTarget) to enlarge if
needed the segments. This new implementation is completely at
Anabatic level and should not be seen (i.e. managed) at Katana level.
* Change: In AutoHorizontal & AutoVertical, change the semantic of
getSourceU() and getTargetU(). formerly they where the end
position of the segment (with extension included), now they
gives the position of the anchor contacts, that is the axis
of the perpandiculars.
* New: AutoSegment::getLength() is still a proxy toward the
Segment::getLength() which returns the length of segment with
dxSource & dxTarget. We introduce a getAnchoredlength()
which returns the length between the centers of the S/T
anchors. That is axis to axis.
This is this length which is now used througout Anabatic.
* New: In AutoSegment::_extentionCaps, add a fourth item to hold
the segment minimal length (to respect minimal area given
the wire width).
* New: In AutoSegment::getExtensionCap(), if the segment has
a non-zero S/T extension, returns it instead of the S/T
contact extension *if it is greated*. The check of the
extension can be disabled by the Flag::NoSegExt flag.
* Change: In AutoSegment::isMiddleStack(), security check on
the presence of source and targets. More accurate detection
of perpandicular in "same layer" with a non-zero length,
So the area is OK, even with a short segment.
* New: AutoSegment::expandToMinLength(), check if a segment is
under the minimal length and expand it if need be by playing
with the dxTarget & dxSource. Tag minimal segments with the
AutoSegment::SegAtMinArea flag. Also try to keep the segment
*inside* it's former (supposedly wider) interval.
* New: AutoSegment::unexpandToMinLength(), to be called on a
formerly minimal sized segment which as grown up. Reset
it's S/T extensions to zero and unset the flag SegAtMinArea.
* Change: In AutoHorizontal::updateOrient(), when the extension
are non-zero, also swap them if needed, to keep the exact
footprint of the segment.
* New: In AutoSegment::revalidate(), check that the segment
respect the minimal length (area), and expand it if needed.
Conversely, if the segment has grown up from a minimal
length state, reset it's extensions to zero.
* Change: In Anabatic::Session::revalidate(), invalidateds
segments are now sorted in such a way that the "middle stack"
ones are revalidateds last. Not recall 100% why...
* New: In Katana::TrackCost, add a computation of the free interval
length we are into (if any). Not used yet, keep it for future
use.
* Change: In KatanaEngine::finalizeLayout(), remove the call to
segments minimum area protection. It is now obsoleted by the
new implementation in Anabatic.
* Change: In Track::check(), call the minimum size/area checker
Track::checkMinArea().
* New: In AutoSegment::getExtensionCap(), when a routing layer has a
minimal area defined, compute the minimal wire length (given it's
width). Then, for segments identified as "MiddleStack" (local
with turns at each end towards opposite layers), if their length
is below minimal, return a longer extention cap.
This may be optimized because with this, the segment extension
is symmetric on both side while it could be made assymetric.
* Change: In NetBuilder::getPositions(), ordering of source/target points
is now integrated to this function instead of left to the caller.
In case of real (non-symbolic) routing gauge, skrink the ends of
half the wire width.
* Change: In NetBuilderHV::doRp_AutoContacts(), in case of non-METAL1
RoutingPad, put the axis of the segment on the nearest track.
Issue a warning if we have to shift, as it may be a potential
source of routing problems.
* New: Anabatic::Session::getNearestTrackaAxis(), proxy to compute
track positions, knowing the design abutment box.
* Bug: In Katana::PreProcess::propagateCagedConstraints(), when
looking at all the slave components anchoreds on a RoutingPad,
if they do not have an AutoSegment lookup, skip them instead
of crashing.
* New: In cumulus/plugins.block.Block.placeMacro(), new method to
place a macro cell, partly delegating to the Macro block wrapper.
Must be called *after* both core and corona abutment boxes have
been set.
Adjust the macro block position so the METAL2 & METAL3 pins
are exactly on pitch regarding the full routing grid. The reference
being the corona.
A shift, less than one pitch may be applied, leading in some
cases of overlapping abutment boxes. But this shouldn't be a
problem.
The macro to place is designated through a path of instances
names, rooted at the *core* (not the corona). Meaning that the
head instance must be one of the core.
* Change: In cumulus/plugins.chip.Chip, the complete chip I/O pads
plus corona and core placement is moved out from doPnR() and
put into doChipFloorplan(). It is now mandatory to call this
method *before* doPnR().
Those methods are now cleanly separated so we can perform macro
block placement or any inner core floorplaning operations between
them.
* Change: In cumulus/plugins.macro.Macro, instead of creating large
pads for the I/O pins so whatever the block position, they will
be under a grid point, create a simple dogleg to put them on
grid.
To ensure that they are "on grid", the block pins must be
in METAL2 (horizontal E/W) or METAL3 (vertical N/S) and the block
is assumed to be placed so the bottom left corner of it's
abutment box is exactly on one grid point for M2/M3.
This should be done by Block.placeMacro().
* New: In KatanaEngine::exportExternalnets(), for commercial tools to
correctly regenerate the external pins from GDSII files it seems
necessary that all segments needs to have TEXT label. So make them
external components.
* New: In Anabatic::NetBuilder::_do_1G_1M3(), RoutingPad in METAL3 from
blocks are most likely to be offgrid in real mode, we must account
for that case. When an offgrid METAL3 is found, a strap of METAL2
is added, as it may be less than one pitch, it will be reduced into
METAL3 often.
* New: In Anabatic::NetBuilder::doRp_Access(), Support for offgrid METAL2
is added but not enabled yet. Seems to need more polishing.
* Bug: In Anabatic::GCell::updateDensity(), the GoStraight flag is now
set in this function when the density of blockage is above 40%.
(should be parametrized in the future). This is linked with the
Katabatic TrackFixedsegment bug.
* Bug: In Anabatic::GCell::Key::Compare, the densities of the GCell
where sorted in the *wrong* order, that is *less denser first*.
This was making the layer assignment working on it's head.
WTF, how did it ever work.
Also sort on global saturation.
* Change: In EtesianEngine::globalPlace(), disable the call to
antennaProtect(). First reason is that, after all, Coloquinte
do not handle so well the resizing of the cells "on the fly",
it overspill the boundaries sometimes. Second reason is that
as we cannot know the routing tree at this stage, we will not
be able to choose the correct points for diode insertions.
We only have a Steiner tree wich may not be the same as a
density driven Dijkstra.
* Change: In Etesian::Area, the Occurrence to the Instances where
not stored in a uniform way. Some where starting from the
placed sub-block, some where starting from the top level
(corona), making their processing (and remembering it) tricky.
Now, they are all expressed from the top cell (corona).
The coordinate system is now systematically the one of the
top block (*not* the block).
Create various overloaded functions EtesianEngine::toCell()
and EtesianEngine::toBlock() to ease Occurrence & coordinate
translations.
* New: In Etesian::Slice::createDiodeUnder(), add a X position hint.
Search is done by going through the whole slice range and
minimizing the distance to the hint. If it starts to be too
slow, we may optimize.
* Bug: In EtesianEngine::toColoquinte(), the placement of the top
level external pins was not taken into account (this at last
explain their weird positioning).
* New: AnabaticEngine::antennaProtect(), new algorithm to avoid
antenna effect. This step must be done *after* global routing
and *before* detailed routing. This way we have access to the
real routing and can mend it (along with the netlist) to
insert diodes at the rigth points.
From the global routing we build clusters (DiodeCluster) of
RoutingPads connected through a set of wire whose total length
is below the antenna effect threshold. Long wires connecting the
clusters are also tagged because we need to put a diode between
them and the first RoutingPad of the cluster. This is to avoid
a long METAL2 wire connecting to the RoutingPad before the diode is
connected through METAL3 (in case of misalignment).
This protection is not even enough. For *very long* wires, we
needs to put *more* than one diode (this is to be implemented).
Integrate new features and bug fixes so the Arlet 6502 benchs successfully
passes real DRC with reference industrial tools. Short summary:
* Manage minimum area for VIAs in Katana::Tracks.
* Allow different wire width for wires perpandicular to the prefered
routing direction.
* StackedVIAs used in the clock tree no longer assume an uniform
routing grid (same offset & pitch all the way up).
* Some hard-coded patches in PowerRails for FlexLib.
* New: In CRL/symbolic/cmos/kite.py & cmos45/kite.py, update the
RoutingLayerGauges by adding the new PWireWidth parameter.
Always zero in case of symbolic layout (too fine tuning).
* New: In CRL::RoutingGauge, add accessor to PWireWidth parameter.
Modify the clone method.
* New: In CRL::RoutingLayerGauge, add new parameter "PWireWidth"
to give the width of a wire when it not drawn in the prefered
routing direction. If it is set to zero, the normal width is
used.
* New: In CRL::PyRoutingGauge, export the updated constructor
interface. It is *not* backward compatible, one must add the
PWireWidth parameter in the various kite.py configuration
files (in etc/).
* Change: In AnabaticEngine::_gutAnabatic(), disable the minimum
area detection mechanism, replaced by a more complete one in
Katana::Track. Left commented out for now, but will be removed
in the future.
* Change: In Anabatic::AutoContact::updateLayer(), now systematically
calls setLayerAndWidth() to potentially resize the VIAs. This is
needed in real mode as VIAs are *not* macro-generated but have
their real final size.
* Change: In Anabatic::AutoContact::setLayerAndWidth(), select the
width and height of the contact using the gauge wire width *and*
perpandicular *wire width*.
* Change: In Anabatic::AutoSegment::_initialize(), the "VIA to same cap"
to PWireWidth/2, this will be the size of the VIA in the
non-preferred direction at the end cap (non-square in real mode).
* Change: In Anabatic::AutoSegment::getExtensionCap(), makes different
cases for symbolic and real. Use raw length in real, add half the
wire width in symbolic.
Add a flag to get the extension cap *only*, not increased of
half the minimal spacing.
* Change: In Anabatic::AutoSegment::bloatStackedStrap(), enhanced,
but finally unused...
* New: In Anabatic::AutoSegment::create(), use the PWireWidth when
the segment is not in the preferred routing direction (and of
minimal width).
* New: In Anabatic::Configuration, add new getPWirewidth(),
DPHorizontalWidth() and DPVerticalWidth() accessors.
* Change: In AnabaticEngine::setupPreRouteds(), skip components in
in "cut" material. We are only interested in objects containing
some metal (happens in real mode when VIAs cuts are really there).
* New: In Katana::PowerRailsPlanes::Rail::doLayout(), add an hard-coded
patch that artificially enlarge the *wide wire* so the spacing for
wide wire is enforced. For now, two pitches on each side for
"FlexLib" gauge.
* New: In Katana::Track, add support to find and correct small wire
chunks so they respect the minimum area rules.
Two helper functions:
* ::hasSameLayerTurn(), to find if a a TrackElement as non-zero length
perpandicular is same layer connected to it.
* ::toFoundryGrid(), to ensure that all coordinates will be on the
foundry grid (may move in a more shared location).
* ::expandToMinArea(), try to expand, *in the routing direction*
the too small wire so it respect the minimal area. Check for the
free space in the track.
Track::minExpandArea() go through all the TrackElements in the track
to look for too small ones and correct them.
* Change: In Katana::RoutingPlane, add an accessor to get the tracks.
* New: In KatanaEngine::finalizeLayout(), add a post-treatment to find
for minimal area violations.
* Change: In cumulus/plugins.block.configuration.GaugeConf, add a
routingBb attribute that will serve as a common reference to all
the functions calculation track positions. We must not have two
different reference for the core and the corona. The reference
is always the corona when we working on a complete chip.
* New: In cumulus/plugins.block.configuration.GaugeConf.getTrack(),
Simplified and more reliable way of getting tracks positions.
Use the routingBb.
* New: In cumulus/plugins.block.configuration.GaugeConf.rpAccess(),
Make use of getTrack() to get every metal strap on the right
X/Y position.
* New: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
As those wires are left alone by the router, it is our responsability
to abide by the minimal area rule here. Hence the code duplication
from the router (bad).
Mainly wires made for the clock tree, I mean.
* Bug: In cumulus/plugins.chip.configuration.ChipConf.setupICore(),
the core instance must be placed on the GCell grid, defined by the
slice height (X *and* Y).
* Bug: In cumulus/plugins.chip.corona.Builder(), forgot to use bigvia
for the corners of the inner ring.
* Bug: In cumulus/plugins.chip.pads.corona._createCoreWire(), hard-coded
patch for LibreSOCIO, the power/ground connectors toward the core
are too wide and can create DRC errors when put side by side.
Shrink them by the minimal distance.
* Bug: In Anabatic::AutoSegment::reduce(), no longer reduce *again*
an already reduced segment.
This bug was seen through a side effect, it was causing the
"reduced perpandicular" counter to be incremented too much and
so it cannot get back to zero, blocking the layer reduction
(AutoSegment::reduceDoglegLayer()) and some bad VIAs where left
over.
More debug information in reduce & raise functions.
* Change: In Katana::Session::_revalidate(), process to be raised
segments *before* segments that can be reduceds.
* New: In Hurricane::Layer, add support for a minimal area (given in
microns). Exported in the Python interface.
* New: In Anabatic::AutoSegment::bloatStackedStrap(), method to
enlarge too small vertically stacked VIAs. For now just create
a square ensuring the minimal area. Potentially cause DRC error in
some cases so needs to be refined.
* New: In Anabatic::_gutAnabatic(), check for too little stacked VIAs
and display a report.
* New: In Hurricane::NetRoutingProperty, add and change the meaning
of the following flags:
- ManualGlobalRoute : now means that a global routing *trunk*
is present, made of "gmetalh", "gmetalv" & "gcontact".
- Manualdetailroute : added, get the former meaning of
ManualGlobalRoute, that is, the detailed routing is
already present for this net, but can be changed by the
detailed router. Implies that it respect the Terminal,
HTee & VTee structuration.
* New: Add Anabatic::Diskstra::loadFixedGlobal(), to account
a manually global net into the edges capacities.
* New: In Anabatic::Edges::ripup(), exclude manually global routed
segments from the ripup. Change the segment sorting function
so that thoses segments are put in head of list (considered
as "smaller").
* Change: In AnabaticEngine::setupPreRouteds(), now detect manual
global routed and manual detail routed signals, and tag them
accordingly.
* New: In AnabaticEngine::Configuration & Session, add proxies
for the global routing layers ("gmetalh", "gmetalv", "gcontact").
* New: In Anabatic::Constants, add flags for global fixed and
detail routed nets.
* Change: In KatanaEngine::updateEstimateDensity(), now use int64_t
for flute coordinates.
* New: Add CRL::RoutingGauge::hasLayer(), to know if a layer is
managed by the gauge (comparison by mask).
* In NetBuilder::_do_xG_1PinM3(), in the three global case, an
incorrect connexion was made.
* In NetBuilder::_do_2G_xM1_1PinM2(), in the global E+W case,
segment between vtee1 <-> turn1 must be vertical.
* Bug: In Anabatic::AutoHorizontal::_slacken(), when creating the target
dogleg, if the target was a fixed pin (M2) on the east side, the
vertical was put righ on the side, which is *not* an allowed track.
The exact east side is not covered by a vertical track (this comes
from a policy adpopted for the GCell, to avoid overlapping tracks
on the border). So we got an error message when katana tries to
bind it to a track. Now shift one perpandicular pitch to the *left*
for the EAST pins.
* Change: In Anabatic::NetBuilderHV::_do_1G_xM1_1PinM2(), the M2 pin
(horizonal) was directly aligned with the outgoing global through
a H-Tee. This was too rigid. Now it can be misaligned.
* Change: In AnabaticEngine::_desaturate(), now use a STL priority
queue built upon a vector with duplicates of the GCell keys.
Much much more faster than the previous set with a custom
sorting key over the GCell. Insertion & removal where getting
a lot of time. Now it's down to less than a minutes, even for
big designs.
* Change; In Anabatic::GCells, add the ability to clone the GCell
key, to use it independently in GCells sorting containers.
This way the cloned value do not change when the GCell is
updated. Keep track of the latest (most up to date) cloned
key.
* Bug: In Anabatic::NetBuilderHV::_do_2G_xM1_1PinM2(), in the case of a
bend of global wires, the topology was faulty. Too rigid topology,
the global wire was forcibly aligned on the external Pin.
* New: In Anabatic::AutoContactTerminal, new method "isOnPin()" to
know if the terminal contact is on a Pin. Introduced in base
class.
* Bug: In Anabatic::AutoHorizontal::_canSlacken() & AutoVertical,
forbid slackening from a Pin. As Pin are all on the side of the
cell (aligneds) and the perpandicular segment will be locked on
the Pin, it generates intractable overlaps for the router.
* Bug: In Anabatic::Configuration::selectRpComponent(), always select
the Pin as the best component. It is mandatory for a block that
we pick up the terminal at the periphery and not one deep inside
the block.
* Bug: In Hurricane::RoutingPad::setOnBestcomponent(), same rule as
in Anabatic, if there is any, the Pin must always be the best
RoutingPad component.
* Bug: In Hurricane/Commons.h, modify the getRecord<>() templates so
that for both vector<Element> and vector<Element*>, the individual
record created for each element are donne with pointers. That is,
for the vector<Element> case, we take a pointer.
As a general policy, except for the POD types, always use pointers
or references to data in the records/inspector. Never uses values
that can call the copy constructor.
Suppress INSPECTOR_PV_SUPPORT() macro, keep only
INSPECTOR_PR_SUPPORT().
Provide value support only for getString<>() template.
This value & copy constructor problem was causing a crash when
trying to inspect Hurricane::AnalogCellExtension.
* New: In Hurricane::Technology, change the API of the PhysicalRule,
now we can only create/get PhysicalRule, but setting the value of
the rule itself must be done on the rule.
Enhance PhysicalRule to provide for stepped rules, non isotropic
and ratio rules.
Merge TwoLayersPhysicalrule in PhysicalRule, much simpler to
suppress the management of derived classes. That means that we
loose a little memory as some fields are mutually exclusive.
Not a problem considering that there will not be so many of thoses
objects.
* New: In CRL/helpers.analogtechno.py, enhanced DTR support for rules
like:
('minSpacing' , 'metal1', ((0.4,20.0), (0.8,1000.0)), Length, 'REF.1')
('minEnclosure', 'metal1', 'cut1', (0.2,0.3) , Length, 'REF.2')
('minDensity' , 'metal1', 0.30 , Unit , 'REF.3')
The DTR parser has been updated, but not the oroshi.dtr Rule
cache for analog components. Given a rule name, the value used
will be the horizontal one of the first step.
* Change: In hurricane/doc/hurricane, re-generate the documentation
with updated support for Technology & PhysicalRule.
* New: In Anabatic::NetBuilder, some GCells configurations of Libre-SOC
"test_issuer" (soclayout/experiments9) did have more METAL1 terminals
than was though possible. Just added more entries in the connexity
table for bigger numbers of METAL1. No new configuration was added,
used the already existing ones.
* Bug: In Anabatic::AutoHorizontal & AutoVertical, in getGCells()
method, do not display the "NULL GCell under" error message if the
segment has just been created. It could on a "wrong" axis position
so the line probing method may fail.
* Bug: In AnabaticEngine CTOR, if the "blockagenet" is created there,
do not forget to set it's type to BLOCKAGE (to avoid later warnings).
* Bug: In Anabatic::NetBuilder::_load(), do not display a warning if the
blockage net has no RoutingPads (it *must* not have one).
* Bug: In Bora::SlicingNode::clearGlobalRouting(), as we are unrouting the
cell, the flags set up by Katana must be reset. The Cell is no longer
"Terminal" and it's nets are "Un-flattened".
* Bug: In Anabatic::Session::_revalidateTopology(), when iterating over
_segmentInvalidateds, the vector can be modified. If it leads to a
reallocation we end up on invalid iterators (using freed memory so
sometimes with overwritten contents). Now, iterate with an index
which warranty that we get a valid item at each iteration of the
loop. And, of course, the vector is ensured to not shrink...
* Change: In Anabatic::Session::Session(), reserve (pre-allocate) at least
1024 elements for all vectors. Mostly prevent the above bug and
avoid constant reallocation.
* Change: In CRL::LefParser::_macroCbk(), create a Catalog entry for the
newly read MACRO (that is Cell) and sets the Logical, Physical,
InMemory and TerminalNetlist flags.
* Bug: In CRL::LefParser::_siteCbk(), check for NULL cell gauge.
* New: In CRL::AllianceFramework, add setCellGauge(), to set the default
cell gauge. Exported to Python.
* Change: In CRL/etc/common/technology.py, create variables for VIA
layers, so we can modify their properties afterwards.
* New: In CRL/etc/node45/freepdk45, port the configuration files to the
new Python "importable" format.
Note: in kite.py, all the gauges (Routing & Cells) must be named
"LEF.CoreSite" to please my LEF parser, so it can match the gauge
name with the SITE name for standard cells.
* Bug: In Anabatic::NetBuilderVH::_do_2G(), forgotten to be reimplemented
from the base class. Simply redirect to _do_xG().
* Change: In Katana::PowerRailsPlanes::PowerRailsplanes(), create plane
from the layers in the RoutingGauge and their associated blockages
instead of sweeping through all the basic layers.
Allow to distinguish bewteen "METAL" (symbolic) and "metal" (real).
* Bug: In Katana::NegociateWindow::createTrackSegment(), *fixed* AutoSegment
in conflict with blockage where removeds. This was creating "holes"
in the Anabatic articulated segment structure. Now just *don't*
create the TrackSegment. Pass the regression tests, but not sure
it is not generating problems elsewhere.
* New: AnabaticEngine::checkPlacement() to issue more clear errors about
a defective placement.
* New: In Anabatic::NetBuilderHV(), added configurations to manage
one Pin M3 + one M1 terminal plus 2 & 3 globals:
* _do_2G_1M1_1PinM3()
* _do_3G_1M1_1PinM3()
They were occuring for the first time in soclayout/experiment7
in the "flat" approach.
* New: In Katana::runNegociate(), mark the newly routed netlist as
"NetlistTerminal" so it is not placed and routed *again* when
reused as an instance (mostly interract with Etesian).
* Bug: In Katana::AutoSegment::_preDestroy(), remove the segment from
the source & target AutoContact cache.
In LibreSOC/experiment7, weird placement caused fixed AutoSegment
overlaping blockage to be deleteds. It seems to have never occured
before (or at least, no ended up in core dump).
* Bug: In Hurricane::NetRoutingState::getSymValue(), outrageously bad
computation of the symmetric coordinate when the value was superior
to the axis... (shame on me).
* Change: In Anabatic::Disjkstra::load(), for symmetrically paired nets,
check that the axis of symmetry is *outside* the searchArea.
Otherwise, the two mirrored areas overlaps and the two nets will
unescapably be on top of each other. Issue a warning but still
continue.
* Change: In Anabatic::Vertex::isRestricted(), allow perpandicular
wire to go through struts or thin (less than one routing pitch)
node. May have to recheck in the future and restrict to struts
only.
* Bug: In Bora::HVSlicingNode::updateSymNetAxis(), rescursive call in
child node was not systematically done (bad curly brace position).
Also checks that symmetries are not empty before accessing the
front element (one less core dump).
Jean-Paul Chaput