The policy about how to create slots was not completly clear.
Now, only add *pointers* or *references* to class attributes,
never do a "copy by value". Reflect that change in SlotTemplate<>
various partial specializations.
Hammer in your head that in C++ functions templates do not allow
for partial specialization. So write only *one* template for
::getSlot<>() (refdefinition simply got ignoreds, at least with gcc).
* Bug: In Slot, only one template for getSlot<> (see above).
Adjust SlotTemplates<> to provides partial specialization only for:
* "const Data&".
* "Data*".
* "const Data*".
* "Data* const"
* "Record*".
* Bug: In Instance::_getRecord(), suppress slot based on transient
values "XCenter" & "YCenter".
* Bug: In CRL::ToolEngine::_getRecord(), suppress slot "Name" based
on a transient value.
* Change: In ::getRecord(std::list<Elementt>*) (and variant), pass
all elements to ::getSlot() as (const Element*).
* In CRL::GdsStream::operator<<(Cell*), when encountering an *external*
component, try to find a ".pin" layer associated (if not already
in it). Then drive the BOUNDARY & TEXT in it. This way, Cadence/
Calibre seems to be able to recognize them as Pin.
height is a multiple of sliceHeight. Otherwise, in some situations,
fixed cell may peek out of the placement area, triggering
Coloquinte assert (which says that the top of the cell is *above*
the top row).
* New: In cumulus/plugins.block.hfns4.py, perform simple HFNS by breaking
the net into sub-nets of at most 10 sinks (hard-coded for now).
As this method is called *after* the netlist as been virtually
flattened, we have to create the RoutingPad at the top level
ourselves. Sub-nets are created at the Cell top-level (same
approach as for clock synthesis, because there is no smart way
to guess where they should be).
* New: In cumulus/plugins.block.block.py, perform HFNS (#4) *before*
doing placement. To see the real sink count on each net, we must
perform the virtual net flattening first (Cell::flattenNets()).
* Change: In cumulus/plugins.block.configuration, allow the creation
of spare buffer in any cell (instead of only "self.cellPnR").
* Change: In cumulus/plugins.block.spares.Spares.raddTransNet(),
Check if intermediate masterNet exists in Cells before trying
to blindly re-create it.
* New: In Etesian/Placement::Area, added support to take into account
bulk inside cells. Currently only hard-wired configuration for
FlexLib is available. Should add a front-end to analyse the
cells of the library to lookup for bulk ties in the future.
* New: In CRL::GdsDriver, create TEXT record under each external
Net component. Seems to be the aknoweledged way to signal
external pins.
* New: In CRL::GdsParser, read TEXT record and create Net and
external components that are in the same layer and at the
same position.
* New: In Etesian::Configuration, added "etesian.lacthUpDistance" to
control tie cells insertion (for polarization contacts).
* New: Etesian/Placement as a complete replacement for FeedCells.
Rebuild the complete slicing structure of the placement to
serve as a building block for post-placement changes under
Coriolis. Currently used to regularly insert body ties.
This is not optimal as we displace cells in each slice in
a non-coordinated manner.
* New: In cumulus/plugins/block.configuration.FeedsConf, register
the "etesian.latchUpDistance" parameter. Provides the tie width.
* New: In cumulus/plugins.block.spares, add ties around the buffer
pool block and "cap ties" at both end of each slice.
* New: In cumulus/plugins.block.spares, added creation of vertical
stacks of feed cells, for their N/P tie contacts, to ensure
correct bulk polarization. Fail, because the placer cannot
cope with such massive obstacles, the vertical columns are
too close to manage.
* New: In cumulus/plugins.block.configuration, add support to
FeedsConf so lone instances can be created (for the first
bulk trial).
* New: In CRL/hepers, new function onFGrid() to ensure a DbU is on the
foundry grid. Rounding is always done to the inferior integer.
* New: In CRL/GdsDriver, added a set of isOnGrid() functions to check
that all coordinates of various objects are on the foundry grid.
Use isOnGrid() in most objects processed in
GdsStream::operator<<(Cell*).
* Bug: In cumulus/plugins.chip.pads.Corner, correctly round the
coordinates of the 45 degree segments so they are still on the
foundry grid.
* New: In cumulus/plugins.core2chip.libresocio.CoreToChip, use new
configuration variable "chip.useAbstractpads" to select between the
abstract version (GPIO, VDD, ...) and the full version (IOPadInOut,
IOPadVdd, ...) layout.
* New: In cumulus/plugins.chip.pads.Corona._createCorewire(), add an
hard-coded limitation for LibreSOCIO I/O pad to corona wires to
always be below the maximal threshold.
* Change: In cumulus/plugins.block.configuration.BlockConf.save(),
cumulus/plugins.block.Block.save(),
cumulus/plugins.chip.Chip.save(),
cumulus/plugins.core2chip.core2chip.CoreToChip.buildChip(),
Add a "flags" parameter to control the way logical views (aka "vst")
are saved. Mainly allowing to pass on the VstUseConcat option in
order for Alliance tools to be able to read them back (lvx, asimut).
* Change: In cumulus/plugins.core2chip.core2chip.CoreToChip.buildChip(),
don't stop at the first I/O pad signal missing on the core, but
display all the missing ones (LKCL proposal).
* In cumulus/block.configuration, the rsave method was buggy. It did stop
it did not save "terminal" master cells (i.e. a cell without instance)
instead of "netlistTerminal" (explicitely flagged for standard cells).
The result was that some "empty netlist" in the complete "ls180"
from LibreSOC went missing. Causing cougar to complain.
* Change: In CRL::Model::staticInit(), when trying to guess the ouput
of the tie low & tie high cells check if the net name is not a
power or ground. A bad input was choosen with FlexLib as the
vdd/vss nets where not typed as POWER/GROUND.
* Change: In Hurricane::QuadTree_GosUnder::Locator::progress(), directly
prune the elements which sizes are under the threshold. This allows
the too small Instances to be directly skipped. This was the key
point slowing the walktrough. We were systematically going through
all the instances (that is consistent with the perf traces).
* Change: In Hurricane::Cell_OccurrencesUnder, add a threshold parameter
to pass on the QuadTree (through getInstancesUnder()).
Needed for the CellWidget selection to have the same problem as
the display itself (select only what is displayed).
* New: In Hurricane::CellView, add two new parameters:
1. "viewer.minimumSize" set the original size of the window, in pixels.
(doubled for HiDPI).
2. "viewer.pixelThreshold", the size, in pixels, under which
components/instances will not be displayeds.
* New: In CRL/etc/cmos.misc.py, added parameters "viewer.minimumSize"
and "viewer.pixelsThreshold".
* Change: In Hurricane::Contact, as it is the base class of Pin, a
width *or* height can rightfully be null (according to the
Pin orientation).
Put the check in a Contact::_postCheck() function.
* Change: In Hurricane::Contact, replace all the "const DbU::Unit&"
parameters by simply "DbU::Unit".
* Change: In Hurricane::Pin, add a dedicated _postCheck() function.
* New: In cumulus/plugins.blocks.iospecs.IoSpecs, new class to manage
I/O pads placement. Support for reading the JSON pinmux format
(courtesy of LKCL & StackOverflow).
* Change: In cumulus/plugins.block.bigvia.BigVia, center the VIA cut
matrix. Issue a BIG warning when no one cut could be drawn
(temporarily disabled until I fix the corona).
* Change: In EtesianEngine, V-Pitch and H-Pitch are now initialized
from the Cell gauge "slice step". It may still be best if the
METAL2 routing grid is still a fractional ratio of the cell height.
* Change: In Hurricane::Contact::Contact(), check width & hieight of
the contact against the minimal size, if below, bellow a warning
and increase the dimension.
May too paranoid when used on turn in same metal (no cut).
Integrate new features and bug fixes so the Arlet 6502 benchs successfully
passes real DRC with reference industrial tools. Short summary:
* Manage minimum area for VIAs in Katana::Tracks.
* Allow different wire width for wires perpandicular to the prefered
routing direction.
* StackedVIAs used in the clock tree no longer assume an uniform
routing grid (same offset & pitch all the way up).
* Some hard-coded patches in PowerRails for FlexLib.
* New: In CRL/symbolic/cmos/kite.py & cmos45/kite.py, update the
RoutingLayerGauges by adding the new PWireWidth parameter.
Always zero in case of symbolic layout (too fine tuning).
* New: In CRL::RoutingGauge, add accessor to PWireWidth parameter.
Modify the clone method.
* New: In CRL::RoutingLayerGauge, add new parameter "PWireWidth"
to give the width of a wire when it not drawn in the prefered
routing direction. If it is set to zero, the normal width is
used.
* New: In CRL::PyRoutingGauge, export the updated constructor
interface. It is *not* backward compatible, one must add the
PWireWidth parameter in the various kite.py configuration
files (in etc/).
* Change: In AnabaticEngine::_gutAnabatic(), disable the minimum
area detection mechanism, replaced by a more complete one in
Katana::Track. Left commented out for now, but will be removed
in the future.
* Change: In Anabatic::AutoContact::updateLayer(), now systematically
calls setLayerAndWidth() to potentially resize the VIAs. This is
needed in real mode as VIAs are *not* macro-generated but have
their real final size.
* Change: In Anabatic::AutoContact::setLayerAndWidth(), select the
width and height of the contact using the gauge wire width *and*
perpandicular *wire width*.
* Change: In Anabatic::AutoSegment::_initialize(), the "VIA to same cap"
to PWireWidth/2, this will be the size of the VIA in the
non-preferred direction at the end cap (non-square in real mode).
* Change: In Anabatic::AutoSegment::getExtensionCap(), makes different
cases for symbolic and real. Use raw length in real, add half the
wire width in symbolic.
Add a flag to get the extension cap *only*, not increased of
half the minimal spacing.
* Change: In Anabatic::AutoSegment::bloatStackedStrap(), enhanced,
but finally unused...
* New: In Anabatic::AutoSegment::create(), use the PWireWidth when
the segment is not in the preferred routing direction (and of
minimal width).
* New: In Anabatic::Configuration, add new getPWirewidth(),
DPHorizontalWidth() and DPVerticalWidth() accessors.
* Change: In AnabaticEngine::setupPreRouteds(), skip components in
in "cut" material. We are only interested in objects containing
some metal (happens in real mode when VIAs cuts are really there).
* New: In Katana::PowerRailsPlanes::Rail::doLayout(), add an hard-coded
patch that artificially enlarge the *wide wire* so the spacing for
wide wire is enforced. For now, two pitches on each side for
"FlexLib" gauge.
* New: In Katana::Track, add support to find and correct small wire
chunks so they respect the minimum area rules.
Two helper functions:
* ::hasSameLayerTurn(), to find if a a TrackElement as non-zero length
perpandicular is same layer connected to it.
* ::toFoundryGrid(), to ensure that all coordinates will be on the
foundry grid (may move in a more shared location).
* ::expandToMinArea(), try to expand, *in the routing direction*
the too small wire so it respect the minimal area. Check for the
free space in the track.
Track::minExpandArea() go through all the TrackElements in the track
to look for too small ones and correct them.
* Change: In Katana::RoutingPlane, add an accessor to get the tracks.
* New: In KatanaEngine::finalizeLayout(), add a post-treatment to find
for minimal area violations.
* Change: In cumulus/plugins.block.configuration.GaugeConf, add a
routingBb attribute that will serve as a common reference to all
the functions calculation track positions. We must not have two
different reference for the core and the corona. The reference
is always the corona when we working on a complete chip.
* New: In cumulus/plugins.block.configuration.GaugeConf.getTrack(),
Simplified and more reliable way of getting tracks positions.
Use the routingBb.
* New: In cumulus/plugins.block.configuration.GaugeConf.rpAccess(),
Make use of getTrack() to get every metal strap on the right
X/Y position.
* New: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
As those wires are left alone by the router, it is our responsability
to abide by the minimal area rule here. Hence the code duplication
from the router (bad).
Mainly wires made for the clock tree, I mean.
* Bug: In cumulus/plugins.chip.configuration.ChipConf.setupICore(),
the core instance must be placed on the GCell grid, defined by the
slice height (X *and* Y).
* Bug: In cumulus/plugins.chip.corona.Builder(), forgot to use bigvia
for the corners of the inner ring.
* Bug: In cumulus/plugins.chip.pads.corona._createCoreWire(), hard-coded
patch for LibreSOCIO, the power/ground connectors toward the core
are too wide and can create DRC errors when put side by side.
Shrink them by the minimal distance.
* Bug: In Anabatic::AutoSegment::reduce(), no longer reduce *again*
an already reduced segment.
This bug was seen through a side effect, it was causing the
"reduced perpandicular" counter to be incremented too much and
so it cannot get back to zero, blocking the layer reduction
(AutoSegment::reduceDoglegLayer()) and some bad VIAs where left
over.
More debug information in reduce & raise functions.
* Change: In Katana::Session::_revalidate(), process to be raised
segments *before* segments that can be reduceds.
* New: In Hurricane::Layer, add support for a minimal area (given in
microns). Exported in the Python interface.
* New: In Anabatic::AutoSegment::bloatStackedStrap(), method to
enlarge too small vertically stacked VIAs. For now just create
a square ensuring the minimal area. Potentially cause DRC error in
some cases so needs to be refined.
* New: In Anabatic::_gutAnabatic(), check for too little stacked VIAs
and display a report.
* New: In cumulus/plugins/chip.corona.HorizontalRail & VerticalRail,
use the new BigVia instead of StackVia to generate a matrix of
cut when in real mode. Stick to the one massive VIA when in
symbolic.
* New: In cumulus/plugins/block.bigvia.BigVia to generate matrixes
of cut VIA.
* Bug: In CRL::GdsDriver::hasLayout(), a Cell was saved in the GDSII
stream only if it has a layout, but the check was not accurate
enough. In the Arlet6502, the whole core was missing.
Now check for the abscence of Plugs (not unfinished Nets) and
PLACED/FIXED instances.
* Change: In documentation/build.py, more PEP8 & Python 3 future compliance.
Correct copy of the tools HTML docs on my laptop, to have a full
offline copy of the doc.
* New: In documentation/contents/pages/check-toolkit, duplicate the doc
from alliance-check-toolkit README. Seems it has been inadvertently
removed at some point (?). Have to be careful to maintain in synch
with the toolkit.
* Change: <tool>/doc/*/SoC.css, use Roboto fonts when availables.
* Update: Commit the whole pre-generated docs (Doxygen, Pelican).
Jean-Paul Chaput
Staf Verhaegen