From fafea3fd0253d776c0fed25b8debf2f506973786 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Mon, 12 Jul 2010 15:33:22 +0000 Subject: [PATCH] Initial import of stratus1 --- stratus1/CMakeLists.txt | 68 + stratus1/LICENSE | 340 ++++ stratus1/configure.in | 28 + stratus1/devdoc/.latex2html-init | 308 ++++ stratus1/devdoc/ASIM.css | 164 ++ stratus1/devdoc/Makefile | 37 + stratus1/devdoc/man_inst.tex | 52 + stratus1/devdoc/man_model.tex | 66 + stratus1/devdoc/man_net.tex | 73 + stratus1/devdoc/man_stratus.tex | 119 ++ stratus1/devdoc/see_also.tex | 3 + stratus1/devdoc/stratus.tex | 90 ++ stratus1/doc/.latex2html-init | 308 ++++ stratus1/doc/ASIM.css | 164 ++ stratus1/doc/Makefile.am | 2 + stratus1/doc/Makefile.manual | 34 + stratus1/doc/developper/.latex2html-init | 308 ++++ stratus1/doc/developper/ASIM.css | 164 ++ stratus1/doc/developper/Makefile | 37 + stratus1/doc/developper/Makefile.am | 70 + stratus1/doc/developper/html.entry | 1 + stratus1/doc/developper/man_inst.tex | 50 + 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stratus1/src/stratus/st_parser.py create mode 100644 stratus1/src/stratus/st_placeAndRoute.py create mode 100644 stratus1/src/stratus/st_placement.py create mode 100644 stratus1/src/stratus/st_ref.py create mode 100644 stratus1/src/stratus/st_shifter.py create mode 100644 stratus1/src/stratus/st_slansky.py create mode 100644 stratus1/src/stratus/stratus.py create mode 100644 stratus1/src/stratus/util.py create mode 100644 stratus1/src/stratus/util_Const.py create mode 100644 stratus1/src/stratus/util_Defs.py create mode 100644 stratus1/src/stratus/util_Gen.py create mode 100644 stratus1/src/stratus/util_Misc.py create mode 100644 stratus1/src/stratus/util_Place.py create mode 100644 stratus1/src/stratus/util_Route.py create mode 100644 stratus1/src/stratus/util_Shift.py create mode 100644 stratus1/src/stratus/util_uRom.py diff --git a/stratus1/CMakeLists.txt b/stratus1/CMakeLists.txt new file mode 100644 index 00000000..2f69d534 --- /dev/null +++ b/stratus1/CMakeLists.txt @@ -0,0 +1,68 @@ +PROJECT(STRATUS1) + +CMAKE_MINIMUM_REQUIRED(VERSION 2.4.0) +IF(COMMAND CMAKE_POLICY) + CMAKE_POLICY(SET CMP0003 NEW) +ENDIF(COMMAND CMAKE_POLICY) + +IF(APPLE) + EXECUTE_PROCESS( + COMMAND sw_vers -productVersion + OUTPUT_VARIABLE OSX_VERSION + OUTPUT_STRIP_TRAILING_WHITESPACE) + MESSAGE(STATUS "OSX_VERSION='${OSX_VERSION}'") + IF(${OSX_VERSION} MATCHES "^10\\.[012345]\\.?") + MESSAGE(STATUS "OSX < 10.6") + ELSE(${OSX_VERSION} MATCHES "^10\\.[012345]\\.?") + SET(CMAKE_OSX_ARCHITECTURES "i386;ppc") # for QT4.5 32bits on snow leopard + ENDIF(${OSX_VERSION} MATCHES "^10\\.[012345]\\.?") +ENDIF(APPLE) + +SET(CMAKE_C_FLAGS_DEBUG "-g -Wall" CACHE STRING "Debug options." FORCE) +SET(CMAKE_CXX_FLAGS_DEBUG "-g -Wall" CACHE STRING "Debug options." FORCE) +#SET(CMAKE_LINKER_FLAGS_DEBUG "-pg" CACHE STRING "Debug options." FORCE) +#SET(CMAKE_SHARED_LINKER_FLAGS_DEBUG "-pg" CACHE STRING "Debug options." FORCE) +#SET(CMAKE_MODULE_LINKER_FLAGS_DEBUG "-pg" CACHE STRING "Debug options." FORCE) +#SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "-pg" CACHE STRING "Debug options." FORCE) + +# This macro has to be included in all the tools CMakeLists.txt as it's +# the sole means of localizing other tools/projects. +MACRO(SETUP_PROJECT_PATHS project) + IF( NOT("$ENV{${project}_TOP}" STREQUAL "") ) + MESSAGE("-- ${project}_TOP is set to $ENV{${project}_TOP}") + SET(PROJECT_MODULE_PATH "${DESTDIR}$ENV{${project}_TOP}/share/cmake/Modules/") + LIST(INSERT CMAKE_MODULE_PATH 0 "${PROJECT_MODULE_PATH}") + ENDIF( NOT("$ENV{${project}_TOP}" STREQUAL "") ) + + IF( NOT("$ENV{${project}_USER_TOP}" STREQUAL "") ) + MESSAGE("-- ${project}_USER_TOP is set to $ENV{${project}_USER_TOP}") + SET(PROJECT_MODULE_PATH "${DESTDIR}$ENV{${project}_USER_TOP}/share/cmake/Modules/") + LIST(INSERT CMAKE_MODULE_PATH 0 "${PROJECT_MODULE_PATH}") + ENDIF( NOT("$ENV{${project}_USER_TOP}" STREQUAL "") ) + + LIST(REMOVE_DUPLICATES CMAKE_MODULE_PATH) +ENDMACRO(SETUP_PROJECT_PATHS project) + +SETUP_PROJECT_PATHS(VLSISAPD) +SETUP_PROJECT_PATHS(CORIOLIS) + +STRING(REGEX MATCH "^/usr" IS_USR "$ENV{CORIOLIS_TOP}") +STRING(REGEX MATCH "^/opt" IS_OPT "$ENV{CORIOLIS_TOP}") +IF(IS_USR OR IS_OPT) + MESSAGE("-- Using system-wide /etc.") + SET(SYS_CONF_DIR "/etc" CACHE STRING "System configuration directory (/etc)" FORCE) +ELSE(IS_USR OR IS_OPT) + MESSAGE("-- Using install tree /etc.") + SET(SYS_CONF_DIR "etc" CACHE STRING "System configuration directory (/etc)" FORCE) +ENDIF(IS_USR OR IS_OPT) + +FIND_PACKAGE(PythonLibs REQUIRED) +FIND_PACKAGE(PythonSitePackages REQUIRED) +FIND_PACKAGE(VLSISAPD REQUIRED) +FIND_PACKAGE(HURRICANE REQUIRED) +FIND_PACKAGE(CORIOLIS REQUIRED) + +SET_LIB_LINK_MODE() + +ADD_SUBDIRECTORY(src) +ADD_SUBDIRECTORY(etc) diff --git a/stratus1/LICENSE b/stratus1/LICENSE new file mode 100644 index 00000000..3912109b --- /dev/null +++ b/stratus1/LICENSE @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/stratus1/configure.in b/stratus1/configure.in new file mode 100644 index 00000000..d7d9ddd1 --- /dev/null +++ b/stratus1/configure.in @@ -0,0 +1,28 @@ + +AC_INIT(src/st_model.py) + +STRATUS_VERSION=3.1 +STRATUS_RELEASE=20090304 +VERSION=$STRATUS_VERSION.$STRATUS_RELEASE + +AM_INIT_AUTOMAKE(stratus,$VERSION) + +AC_PROG_MAKE_SET +AM_CORIOLIS + +AC_OUTPUT([ +coriolis-stratus.spec +Makefile +src/Makefile +src/lib/Makefile +src/dpgen/Makefile +doc/Makefile +doc/stratus/Makefile +doc/stratus/images/Makefile +doc/developper/Makefile +doc/dpgen/Makefile +doc/patterns/Makefile +etc/Makefile +modules/Makefile +modules/patterns/Makefile +]) diff --git a/stratus1/devdoc/.latex2html-init b/stratus1/devdoc/.latex2html-init new file mode 100644 index 00000000..41736623 --- /dev/null +++ b/stratus1/devdoc/.latex2html-init @@ -0,0 +1,308 @@ + +# -*- Perl -*- +# +#LaTeX2HTML Version 96.1 : dot.latex2html-init +# +### Command Line Argument Defaults ####################################### + +$MAX_SPLIT_DEPTH = 4; # Stop making separate files at this depth + +$MAX_LINK_DEPTH = 2; # Stop showing child nodes at this depth + +$NOLATEX = 0; # 1 = do not pass unknown environments to Latex + +$EXTERNAL_IMAGES = 0; # 1 = leave the images outside the document + +$ASCII_MODE = 0; # 1 = do not use any icons or internal images + +# 1 = use links to external postscript images rather than inlined bitmap +# images. +$PS_IMAGES = 0; + +#$TITLE = "Titre"; # The default is "No Title" + +$DESTDIR = ''; # Put the result in this directory + +# When this is set, the generated HTML files will be placed in the +# current directory. If set to 0 the default behaviour is to create (or reuse) +# another file directory. +$NO_SUBDIR = 0; + + +# Supply your own string if you don't like the default +$ADDRESS = "$address_data[0]
\n$address_data[1]"; + +$NO_NAVIGATION = 0; # 1 = do not put a navigation panel at the top of each page + +# Put navigation links at the top of each page. +# If the page exceeds $WORDS_IN_PAGE number of words then put one at the bottom of the page. +$AUTO_NAVIGATION = 1; + +# Put a link to the index page in the navigation panel +$INDEX_IN_NAVIGATION = 1; + +# Put a link to the table of contents in the navigation panel +$CONTENTS_IN_NAVIGATION = 1; + +# Put a link to the next logical page in the navigation panel +$NEXT_PAGE_IN_NAVIGATION = 1; + +# Put a link to the previous logical page in the navigation panel +$PREVIOUS_PAGE_IN_NAVIGATION = 1; + +$INFO = 0; # 0 = do not make a "About this document..." section + +# Reuse images generated during previous runs +$REUSE = 2; + +# When this is 1, the section numbers are shown. The section numbers should +# then match those that would have bee produced by LaTeX. +# The correct section numbers are obtained from the $FILE.aux file generated +# by LaTeX. +# Hiding the seciton numbers encourages use of particular sections +# as standalone documents. In this case the cross reference to a section +# is shown using the default symbol rather than the section number. +$SHOW_SECTION_NUMBERS = 0; + +### Other global variables ############################################### +$CHILDLINE = "
\n"; + +# This is the line width measured in pixels and it is used to right justify +# equations and equation arrays; +$LINE_WIDTH = 500; + +# Used in conjunction with AUTO_NAVIGATION +#$WORDS_IN_PAGE = 300; !!! +$WORDS_IN_PAGE = 50; + +# Affects ONLY the way accents are processed +$default_language = 'english'; + +# The value of this variable determines how many words to use in each +# title that is added to the navigation panel (see below) +# +$WORDS_IN_NAVIGATION_PANEL_TITLES = 4; + +# This number will determine the size of the equations, special characters, +# and anything which will be converted into an inlined image +# *except* "image generating environments" such as "figure", "table" +# or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$MATH_SCALE_FACTOR = 1.6; + +# This number will determine the size of +# image generating environments such as "figure", "table" or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$FIGURE_SCALE_FACTOR = 1.6; + + +# If this is set then intermediate files are left for later inspection. +# This includes $$_images.tex and $$_images.log created during image +# conversion. +# Caution: Intermediate files can be *enormous*. +$DEBUG = 0; + +# If both of the following two variables are set then the "Up" button +# of the navigation panel in the first node/page of a converted document +# will point to $EXTERNAL_UP_LINK. $EXTERNAL_UP_TITLE should be set +# to some text which describes this external link. +$EXTERNAL_UP_LINK = ""; +$EXTERNAL_UP_TITLE = ""; + +# If this is set then the resulting HTML will look marginally better if viewed +# with Netscape. +$NETSCAPE_HTML = 0; + +# Valid paper sizes are "letter", "legal", "a4","a3","a2" and "a0" +# Paper sizes has no effect other than in the time it takes to create inlined +# images and in whether large images can be created at all ie +# - larger paper sizes *MAY* help with large image problems +# - smaller paper sizes are quicker to handle +$PAPERSIZE = "a4"; + +# Replace "english" with another language in order to tell LaTeX2HTML that you +# want some generated section titles (eg "Table of Contents" or "References") +# to appear in a different language. Currently only "english" and "french" +# is supported but it is very easy to add your own. See the example in the +# file "latex2html.config" +$TITLES_LANGUAGE = "english"; + +### Navigation Panel ########################################################## +# +# The navigation panel is constructed out of buttons and section titles. +# These can be configured in any combination with arbitrary text and +# HTML tags interspersed between them. +# The buttons available are: +# $PREVIOUS - points to the previous section +# $UP - points up to the "parent" section +# $NEXT - points to the next section +# $NEXT_GROUP - points to the next "group" section +# $PREVIOUS_GROUP - points to the previous "group" section +# $CONTENTS - points to the contents page if there is one +# $INDEX - points to the index page if there is one +# +# If the corresponding section exists the button will contain an +# active link to that section. If the corresponding section does +# not exist the button will be inactive. +# +# Also for each of the $PREVIOUS $UP $NEXT $NEXT_GROUP and $PREVIOUS_GROUP +# buttons there are equivalent $PREVIOUS_TITLE, $UP_TITLE, etc variables +# which contain the titles of their corresponding sections. +# Each title is empty if there is no corresponding section. +# +# The subroutine below constructs the navigation panels in each page. +# Feel free to mix and match buttons, titles, your own text, your logos, +# and arbitrary HTML (the "." is the Perl concatenation operator). + + +@my_icon_tags = (); +$my_icon_tags{'next'} = 'Next Page'; +$my_icon_tags{'next_page'} = 'Next Page'; +$my_icon_tags{'previous'} = 'Previous Page'; +$my_icon_tags{'previous_page'} = 'Previous Page'; +$my_icon_tags{'up'} = 'Up One Level'; +$my_icon_tags{'contents'} = 'Contents'; +$my_icon_tags{'index'} = 'Index'; +$my_icon_tags{'modules'} = 'Module Index'; + +@my_icon_names = (); +$my_icon_names{'previous_page'} = 'prev'; +$my_icon_names{'next_page'} = 'next'; + + +sub get_my_icon($) { + my $icon_file; + my $name = @_[0]; + my $text = $my_icon_tags{$name}; + if ($my_icon_names{$name}) { + $name = $my_icon_names{$name}; + } + if ($text eq '') { + $name = 'blank'; + } + $icon_file = $name . "." . $IMAGE_TYPE; + $used_icons{$icon_file} = 1; + return "\"$text\""; +} + + +sub use_my_icon($) { + my $s = @_[0]; + if ($s =~ /\/) { + my $r = get_my_icon($1); + $s =~ s/\/$r/; + } + return $s; +} + + +sub make_top_nav_panel() { + my $s; + $s = ('' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
$t_title
" + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
" + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
\n" + . "
\n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub make_bot_nav_panel() { + my $s; + $s = ('
' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
$t_title
" + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
" + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
\n" + . "
\n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub top_navigation_panel { + return "\n" + . make_top_nav_panel() + . "
\n"; +} + + +sub bot_navigation_panel { + return "\n

\n" + . make_bot_nav_panel() + . "\n"; +} + + +#$EXTERNAL_STYLESHEET = "../ASIM.css"; + +$ADDRESS = "Sophie BELLOEIL
20051116.1"; + +$LOCAL_ICONS = 0; + +$USING_STYLES = 1; + +$TRANSPARENT_FIGURES = 1; + +$WHITE_BACKGROUND = 0; + +$used_icons{"home." . $IMAGE_TYPE} = 1; + +1; # This must be the last line diff --git a/stratus1/devdoc/ASIM.css b/stratus1/devdoc/ASIM.css new file mode 100644 index 00000000..180cadb3 --- /dev/null +++ b/stratus1/devdoc/ASIM.css @@ -0,0 +1,164 @@ + + html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 { + font-size: 100%; + font-family: verdana, sans-serif; + } + + body { + color: black; + background: white; + background-color: white; + background-position: top left; + background-attachment: fixed; + background-repeat: no-repeat; + margin-top: 2em; + margin-right: 10%; + margin-left: 10%; + } + + hr { + height: 1px; + border: 0; + color: #004400; + background-color: #004400; + } + + + h1, h2, h3, h4, h5, h6 { + font-family: verdana, sans-serif; + } + + h1 { text-align: center; } + h2, h3, h4, h5, h6 { text-align: left; + padding-top: 2em; + } + h1, h2, h3 { font-family: "Trebuchet MS", sans-serif; + color: #09550B; + } + h1 { font-weight: bold; font-size: 170%; } + h2 { font-weight: bold; font-size: 140%; } + h3 { font-weight: bold; font-size: 118%; } + h4 { font-weight: bold; font-size: 100%; } + h5 { font-style: italic; font-size: 100%; } + h6 { font-variant: small-caps; font-size: 100%; } + + .hide { + display: none; + color: white; + } + + + div.navigation { margin-bottom: 1em; } + div.navigation h1 { margin-top: 2em; clear: both; } + div.navigation table { margin-left: 2em; font-size: 90%; } + div.navigation img { color: white; border: none; } + + + p { + margin-top: 0.6em; + margin-bottom: 0.6em; + margin-left: 0.0em; + margin-right: 0.0em; + } + + p.copyright { font-size: 90%; } + p.copyright small { font-size: 80%; } + + p.changed { + padding-left: 0.2em; + border-left: solid; + border-top: none; + border-bottom: none; + border-right: none; + border-left-width: thin; + border-color: red; + } + + + address { + text-align: right; + font-weight: bold; + font-style: italic; + font-size: 80%; + } + + + blockquote { + margin-left: 4em; + margin-right: 4em; + margin-top: 0.8em; + margin-bottom: 0.8em; + font-style: italic; + color: #003300; + } + + blockquote p { + margin-bottom: 0; + } + + blockquote address { + margin: 0; + } + + + table { + border-collapse: collapse; + /* + margin-left: 0em; + margin-right: 0em; + */ + margin-top: 0.8em; + margin-bottom: 0.8em; + } + + dt, dd { margin-top: 0; margin-bottom: 0; } + dt { font-weight: bold; } + + + pre, tt, code { + font-family: "andale mono", monospace; + font-size: 100%; + white-space: pre; + } + + pre { + font-size: 80%; + border: solid; + border-width: thin; + border-color: #003300; + background-color: #EEEEEE; + padding: 0.5em; + margin-left: 2em; + margin-right: 2em + } + + tt { color: green; } + em { font-style: italic; font-weight: bold; } + strong { font-weight: bold; } + + span.textit { font-style: italic; } + span.textbf { font-weight: bold; } + + .small { font-size: 90%; } + .white { color: #FFFFFF; } + + + ul.toc { + list-style: disc; + list-style: none; + } + + + a:link img, a:visited img { border-style: none; } + a img { color: white; } + + a:link, a:active, a:visited { + color: #09550B; + text-decoration: none; + } + + a:hover, a:focus { + color: #FF9900; + text-decoration: underline; + } + diff --git a/stratus1/devdoc/Makefile b/stratus1/devdoc/Makefile new file mode 100644 index 00000000..f87d676b --- /dev/null +++ b/stratus1/devdoc/Makefile @@ -0,0 +1,37 @@ +all : stratus.pdf stratus/index.html ASIM.css stratus/ASIM.css + +stratus.pdf: *.tex + @pdflatex stratus.tex + @pdflatex stratus.tex +# xdvi stratus.dvi + +viewpdf: stratus.pdf + @acroread stratus.pdf & + + +stratus/index.html: *.tex + @latex2html -no_math -html_version 4.0,math -style ./ASIM.css stratus.tex + +stratus/ASIM.css: ASIM.css + @cp -p ASIM.css stratus/ASIM.css + + +orthographe: stratus.tex + aspell -t --lang=fr -c $< + +clean: + @rm -rf *.dvi \ + *.ps \ + *.lof \ + *.log \ + *.out \ + *.toc \ + *.aux \ + *.bak \ + stratus.pdf \ + stratus/*.html \ + stratus/*.css \ + stratus/*.pl \ + stratus/WARNINGS + @rm -rf stratus/* + @rmdir stratus diff --git a/stratus1/devdoc/man_inst.tex b/stratus1/devdoc/man_inst.tex new file mode 100644 index 00000000..7b095c73 --- /dev/null +++ b/stratus1/devdoc/man_inst.tex @@ -0,0 +1,52 @@ +\subsection{Synopsys} + +\begin{verbatim} +Inst ( model + , name + , param = myParam + , map = myMap + ) +\end{verbatim} + +\subsection{Description} + +Instantiation of an instance. The type of the instance is given by the \verb-model- parameter. The connexions are made thanks to the \verb-map- parameters. + +\subsection{Parameters} + +\begin{itemize} + \item \verb-model- : Name of the mastercell of the instance to create (mandatory argument) + \item \verb-name- : Name of the instance (optional)\\ +When this argument is not defined, the instance has a name created by default. This argument is usefull when one wants to create a layout as well. Indeed, the placement of the instances is much easier when the conceptor has chosen himself the name f the instances. + \item \verb-param- : Dictionnary for parameters of the mastercell (optional : only for mastercells which require it) + \item \verb-map- : Dictionnary for connexions in order to make the netlist\\ +\end{itemize} + +\subsection{Attributes} + +\begin{itemize} + \item \verb-_name- : Name of the instance (the name given as parameter if there's one, a name created otherwise) + \item \verb-_model- : Name of the model given as argument + \item \verb-_real_model- : Name of the model created thanks to \verb-_model- and all the parameters + \item \verb-_map- : Dictionnary \verb-map- given at the instanciation + \item \verb-_param- : Dictionnary \verb-param- given at the instanciation + \item \verb-_st_cell- : The stratus cell which the instance is instanciated in + \item \verb-_st_masterCell- : The stratus master cell of the instance\\ +\end{itemize} +\indent For placement : +\begin{itemize} + \item \verb-_plac- : tells if the instance is placed or not (UNPLACED by default) + \item \verb-_x-, \verb-_y- : the coordinates of the instance (only for placed instances) + \item \verb-_sym- : the symetry of the instance (only for placed instances)\\ +\end{itemize} +\indent And, in connection with Hurricane : +\begin{itemize} + \item \verb-_hur_instance- : The hurricane instance (None by default) + \item \verb-_hur_masterCell- : The Hurricane master cell of the instance (None by default) +\end{itemize} + +\subsection{Methods} + +\begin{itemize} + \item Delete : Deletion of the Hurricane instance +\end{itemize} diff --git a/stratus1/devdoc/man_model.tex b/stratus1/devdoc/man_model.tex new file mode 100644 index 00000000..212e2f00 --- /dev/null +++ b/stratus1/devdoc/man_model.tex @@ -0,0 +1,66 @@ +\subsection{Synopsys} + +\begin{verbatim} +class myClass ( Model ) : + ... + +exemple = myClass ( name, param ) +\end{verbatim} + +\subsection{Description} + +Every cell made is a class herited from class \verb-Model-.\\ +\indent Some methods have to be created, like \verb-Interface-, \verb-Netlist- ... Some methods are inherited from the class \verb-Model-. + +\subsection{Parameters} + +\begin{itemize} + \item \verb-name- : The name of the cell (which is the name of the files which will be created) + \item \verb-param- : A dictionnary which gives all the parameters useful in order to create the cell +\end{itemize} + +\subsection{Attributes} + +\begin{itemize} + \item \verb-_name- : Name of the cell + \item \verb-_st_insts- : List of all the instances of the cell + \item \verb-_st_ports- : List of all the external nets of the cell (except for alimentations and clock) + \item \verb-_st_sigs- : List of all the internal nets of the cell + \item \verb-_st_vdds-, \verb-_st_vsss- : Two tabs of the nets which are instancied as \verb-VddIn- and \verb-VssIn- + \item \verb-_st_cks- : List of all the nets which are instancied as \verb-CkIn- + \item \verb-_st_merge- : List of all the internal nets which have to be merged + \item \verb-_param- : The map given as argument at the creation of the cell + \item \verb-_underCells- : List of all the instances which are cells that have to be created + \item \verb-_and-, \verb-_or-, \verb-_xor-, \verb-_not-, \verb-_buff-, \verb-_mux-, \verb-_reg-, \verb-_shift-, \verb-_comp-, \verb-_add-, \verb-_mult-, \verb-_div- : tells which generator to use when using overloard + \item \verb-_NB_INST- : The number of instances of the cell (useful in order to automatically give a name to the instances) + \item \verb-_TAB_NETS_OUT- and \verb-_TAB_NETS_CAT- : Lists of all the nets automatically created + \item \verb-_insref- : The reference instance (for placement)\\ +\end{itemize} + +\indent And, in connection with Hurricane : +\begin{itemize} + \item \verb-_hur_cell- : The hurricane cell (None by default) + \item \verb-_db- : The database + \item \verb-_lib0- : \verb-self._db.Get_CATA_LIB ( 0 )- + \item \verb-_nb_alims_verticales-, \verb-_nb_pins-, \verb-_nb_vdd_pins-, \verb-_nb_vss_pins-, \verb-standard_instances_list-, \verb-pad_north-, \verb-pad_south-, \verb-pad_east-, \verb-pad_west- : all place and route stuffs ... + +\end{itemize} + +\subsection{Methods} + +Methods of class \verb-Model- are listed below : +\begin{itemize} + \item \verb-HurricanePlug- : Creates the Hurricane cell thanks to the stratus cell.\\Before calling this method, only the stratus cell is created, after this method, both cells are created. This method has to be called before View and Save, and before Layout. + \item \verb-View- : Opens/Refreshes the editor in order to see the created layout + \item \verb-Quit- : Finishes a cell without saving + \item \verb-Save- : Saves the created cell\\If several cells have been created, they are all going to be saved in separated files\\ +\end{itemize} + +Some of those methods have to be defined in order to create a new cell : +\begin{itemize} + \item \verb-Interface- : Description of the external ports of the cell + \item \verb-Netlist- : Description of the netlist of the cell + \item \verb-Layout- : Description of the layout of the cell + \item \verb-Vbe- : Description of the behavior of the cell + \item \verb-Pattern- : Description of the patterns in order to test the cell +\end{itemize} diff --git a/stratus1/devdoc/man_net.tex b/stratus1/devdoc/man_net.tex new file mode 100644 index 00000000..9cdb22e4 --- /dev/null +++ b/stratus1/devdoc/man_net.tex @@ -0,0 +1,73 @@ +\subsection{Synopsys} + +\begin{verbatim} +netInput = LogicIn ( name, arity ) +\end{verbatim} + +\subsection{Description} + +Instanciation of net. Differents kind of nets are listed below : +\begin{itemize} + \item \verb-LogicIn- : Creation of an input port + \item \verb-LogicOut- : Creation of an output port + \item \verb-LogicInOut- : Creation of an inout port + \item \verb-LogicUnknown- : Creation of an input/output port which direction is not defined + \item \verb-TriState- : Creation of a tristate port + \item \verb-CkIn- : Creation of a clock port + \item \verb-VddIn- : Creation of the vdd alimentation + \item \verb-VssIn- : Creation of the vss alimentation + \item \verb-Signal- : Creation of an internal net +\end{itemize} + +\subsection{Parameters} + +\begin{itemize} + \item \verb-name- : Name of the net (mandatory argument) + \item \verb-arity- : Arity of the net (mandatory argument) + \item \verb-indice- : For buses only : the LSB bit (optional argument : set to 0 by default)\\ +\end{itemize} + +\indent Only \verb-CkIn, -\verb-VddIn- and \verb-VssIn- do not have the same parameters : there is only the \verb-name- parameter (they are 1 bit nets). + +\subsection{Attributes} + +\begin{itemize} + \item \verb-_name- : Name of the net + \item \verb-_arity- : Arity of the net (by default set to 0) + \item \verb-_ind- : LSB of the net + \item \verb-_ext- : Tells if the net is external or not (True/False) + \item \verb-_direct- : If the net is external, tells the direction ("IN", "OUT", "INOUT", "TRISTATE", "UNKNOWN") + \item \verb-_h_type- : If the net is an alimentation or a clock, tells the type ("POWER", "GROUND", "CLOCK") + \item \verb-_type- : The arithmetic type of the net ( "nr" ) + \item \verb-_st_cell- : The stratus cell which the net is instanciated in + \item \verb-_real_net- : If the net is a part of a net (Sig) it is the real net corresponding + \item \verb-_alias- : [] by default. When the net has an alias, it's a tab. Each element of the tab correspond to a bit of the net (from the LSB to the MSB), it'a a dictionnary : the only key is the net which this net is an alias from, the value is the bit of the net + \item \verb-_to_merge- : [] by default. The same as \_alias + \item \verb-_to_cat- : [] by default. The same as \_alias\\ +\end{itemize} + +\indent And, in connection with Hurricane : +\begin{itemize} + \item \verb-_hur_net- : A tab with all the hurricane nets corresponding to the stratus net ; From the LSB to the MSB (for example, with a 1 bit net, one gets the hurricane net by doing : \verb-net._hur_net[0]- ). +\end{itemize} + +\subsection{Methods} + +\begin{itemize} + \item \verb-Buffer- : Instanciation of a Buffer + \item \verb-Shift- : Instanciation of a shifter + \item \verb-Mux- : Instanciation of a multiplexor + \item \verb-Reg- : Instanciation of a register + \item \verb-Eq/Ne- : Instanciation of comparison generator + \item \verb-Extend- : A net is extended + \item \verb-Alias- : A net is an alias of another net + \item \verb-Delete- : Deletion of the Hurricane nets\\ +\end{itemize} +\indent And the overloards : +\begin{itemize} + \item \_\_init\_\_ : Initialisation of nets + \item \_\_le\_\_ : initialisation of a net thanks to <= notation + \item \_\_getitem\_\_, \_\_geslice\_\_ : Creation of "Sig" nets : which are part of nets (use of \verb-[]- and \verb-[:]-) + \item \_\_and\_\_, \_\_or\_\_, \_\_xor\_\_, \_\_invert\_\_ : boolean operation with \&, |, \^ , ~ + \item \_\_add\_\_, \_\_mul\_\_, \_\_div\_\_ : arithmetic operators with +, * and / +\end{itemize} diff --git a/stratus1/devdoc/man_stratus.tex b/stratus1/devdoc/man_stratus.tex new file mode 100644 index 00000000..840123c7 --- /dev/null +++ b/stratus1/devdoc/man_stratus.tex @@ -0,0 +1,119 @@ +\subsubsection{Name} + +Stratus -- Procedural design language based upon \emph{Python} + +\subsubsection{Description} + +\emph{Stratus} is a set of \emph{Python} methods/functions dedicated to procedural generation purposes. From a user point of view, \emph{Stratus} is a circuit's description language that allows \emph{Python} programming flow control, variable use, and specialized functions in order to handle vlsi objects.\\ + +\indent Based upon the \emph{Hurricane} data structures, the \emph{Stratus} language gives the user the ability to describe netlist and layout views. + +\subsubsection{Creation of a cell} + +A cell is a hierachical structural description of a circuit in terms of ports (I/Os), signals (nets) and instances : + +\begin{itemize} +\item Method \verb-Interface- + \begin{itemize} + \item LogicIn + \item LogicOut + \item LogicInOut + \item TriState + \item VddIn + \item VssIn + \end{itemize} +\item Method \verb-Netlist- + \begin{itemize} + \item Signal + \item Inst + \item Facilities : \&, |, +, Mux, Shift, Eq/Ne ... + \end{itemize} +\item Method \verb-Layout- + \begin{itemize} + \item Place, PlaceTop, PlaceBottom, PlaceRight, PlaceLeft + \item SetRefIns + \item DefAb, ResizeAb + \item PlaceCentric + \item PlaceGlue, FillCell + \item PadNorth, PadSouth, PadEast, PadWest + \item AlimVerticalRail, AlimHorizontalRail + \item AlimConnectors + \item PowerRing + \item RouteCk + \end{itemize} + \item Method \verb-Pattern- + \item Method \verb-View- + \item Method \verb-Save- +\end{itemize} + +\subsubsection{Syntax highlighting} + +This chapter describes what to do to have the right syntax highlighting when using vi. + +\begin{itemize} + \item Commands to do when you want to change once the coloration of your file : +\end{itemize} +\begin{small} +\begin{verbatim} +:syntax off +:source /asim/coriolis/share/etc/stratus.vim +\end{verbatim} +\end{small} +\begin{itemize} + \item Modification of your .vimrc in order to have the syntax highlighting each time you open a file : +\end{itemize} +\begin{small} +\begin{verbatim} +syntax off +autocmd BufRead,BufNewfile *.py so /asim/coriolis/share/etc/stratus.vim +syntax on +\end{verbatim} +\end{small} + +\subsubsection{Environment variables} + +\begin{itemize} + \item CRL\_IN\_LO, default value : \verb-def- + \item CRL\_OUT\_LO, default value : \verb-def- + \item CRL\_IN\_PH, default value : \verb-def- + \item CRL\_OUT\_PH, default value : \verb-def- + \item CRL\_CATA\_LIB, default value : \verb-.- + \item CRL\_CATAL\_NAME, default value : \verb-CATAL- +\end{itemize} + +\subsubsection{Syntax} + +A \emph{Stratus} file must have a .py extension and must begin as follow : +\begin{verbatim} +#!/usr/bin/python + +from stratus import * +\end{verbatim} + +\indent In order to execute a \emph{Stratus} file (named \verb-file- for example), one has two choices : +\begin{verbatim} +python file.py +\end{verbatim} +\indent Or : +\begin{verbatim} +chmod u+x file.py +./file.py +\end{verbatim} + +\indent The names used in \emph{Stratus}, as arguments to \emph{Stratus} functions, should be alphanumerical, including the underscore. The arguments of \emph{Stratus} are case sensitive, so \textsc{VDD} is not equivalent to \textsc{vdd}.\\ + +\indent Vectorized connectors or signal can be used using the \textsc{[n:m]} construct.\\ + +\subsubsection{Example} + +You can see a concrete example at : \hyperref[ref]{\emph{A concrete example}}{}{Example}{secexample} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Model}}{}{Model}{secmodel} +\hyperref[ref]{\emph{Param}}{}{Param}{secparam} +\hyperref[ref]{\emph{Example}}{}{Example}{secexample} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{Place and Route}}{}{Place and Route}{secroute} +\hyperref[ref]{\emph{Facilities}}{}{Facilities}{secfacilities} diff --git a/stratus1/devdoc/see_also.tex b/stratus1/devdoc/see_also.tex new file mode 100644 index 00000000..32299cf7 --- /dev/null +++ b/stratus1/devdoc/see_also.tex @@ -0,0 +1,3 @@ +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} diff --git a/stratus1/devdoc/stratus.tex b/stratus1/devdoc/stratus.tex new file mode 100644 index 00000000..ddf0da52 --- /dev/null +++ b/stratus1/devdoc/stratus.tex @@ -0,0 +1,90 @@ +\documentclass[12pt]{article} +\usepackage[latin1]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{palatino} +\usepackage{fancyheadings} +\usepackage{float} +\usepackage{subfigure} +\usepackage{wrapfig} +\usepackage[dvips]{graphics} +\usepackage{graphicx} +\usepackage[french]{babel} +\usepackage{epsfig} +\usepackage{multicol} +\usepackage{color} +\usepackage{url} +\usepackage{html} + +\setlength{\topmargin}{0cm} +\setlength{\headheight}{1cm} +\setlength{\textheight}{21cm} +\setlength{\textwidth}{16cm} +\setlength{\oddsidemargin}{0cm} +\setlength{\evensidemargin}{0cm} +\setlength{\columnsep}{0.125in} +\setlength{\columnseprule}{0.5pt} +\setlength{\footskip}{1cm} +%\setlength{\hoffset}{-18pt} +%\setlength{\oddsidemargin}{0pt} % Marge gauche sur pages impaires +%\setlength{\evensidemargin}{9pt} % Marge gauche sur pages paires +%\setlength{\marginparwidth}{54pt} % Largeur de note dans la marge +%\setlength{\textwidth}{481pt} % Largeur de la zone de texte (17cm) +%\setlength{\voffset}{-18pt} % Bon pour DOS +%\setlength{\marginparsep}{7pt} % Séparation de la marge +%\setlength{\topmargin}{0pt} % Pas de marge en haut +%\setlength{\headheight}{13pt} % Haut de page +%\setlength{\headsep}{10pt} % Entre le haut de page et le texte +%\setlength{\footskip}{27pt} % Bas de page + séparation +%\setlength{\textheight}{708pt} % Hauteur de la zone de texte (25cm) +\sloppy + +\newcommand{\image}[4] +% {\begin{figure}[htbp] + {\begin{figure}[h!] + \includegraphics[width=#2\textwidth]{#1} + \end{figure} + } +% \image{fig.eps}{scale} + +%--------------------------------- page style -------------------------------- +\pagestyle{fancy} +\rhead{} +\lhead{} +\rfoot{\thepage} +\lfoot{} +\cfoot{} +\setlength{\footrulewidth}{0.6pt} +%---------------------------------- document --------------------------------- +\date {} +\title {Stratus Developper's Manual} +\author {Sophie Belloeil} + +\begin{document} + +\maketitle + +%%\begin{htmlonly} +%% \htmlrule +%% \noindent La version imprimable de ce document est disponible ici~: \\ +%% \begin{center} +%% \hyperref[hyper]{http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf}{}{} +%% {http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf} +%% \end{center} +%%\end{htmlonly} + +\tableofchildlinks +\htmlrule + +\section{Class Model} +\label{secmodel} +\input{man_model} + +\section{Nets} +\label{secnet} +\input{man_net} + +\section{Instances} +\label{secinst} +\input{man_inst} + +\end{document} diff --git a/stratus1/doc/.latex2html-init b/stratus1/doc/.latex2html-init new file mode 100644 index 00000000..df1398eb --- /dev/null +++ b/stratus1/doc/.latex2html-init @@ -0,0 +1,308 @@ + +# -*- Perl -*- +# +#LaTeX2HTML Version 96.1 : dot.latex2html-init +# +### Command Line Argument Defaults ####################################### + +$MAX_SPLIT_DEPTH = 5; # Stop making separate files at this depth + +$MAX_LINK_DEPTH = 2; # Stop showing child nodes at this depth + +$NOLATEX = 0; # 1 = do not pass unknown environments to Latex + +$EXTERNAL_IMAGES = 0; # 1 = leave the images outside the document + +$ASCII_MODE = 0; # 1 = do not use any icons or internal images + +# 1 = use links to external postscript images rather than inlined bitmap +# images. +$PS_IMAGES = 0; + +#$TITLE = "Titre"; # The default is "No Title" + +$DESTDIR = ''; # Put the result in this directory + +# When this is set, the generated HTML files will be placed in the +# current directory. If set to 0 the default behaviour is to create (or reuse) +# another file directory. +$NO_SUBDIR = 0; + + +# Supply your own string if you don't like the default +$ADDRESS = "$address_data[0]
\n$address_data[1]"; + +$NO_NAVIGATION = 0; # 1 = do not put a navigation panel at the top of each page + +# Put navigation links at the top of each page. +# If the page exceeds $WORDS_IN_PAGE number of words then put one at the bottom of the page. +$AUTO_NAVIGATION = 1; + +# Put a link to the index page in the navigation panel +$INDEX_IN_NAVIGATION = 1; + +# Put a link to the table of contents in the navigation panel +$CONTENTS_IN_NAVIGATION = 1; + +# Put a link to the next logical page in the navigation panel +$NEXT_PAGE_IN_NAVIGATION = 1; + +# Put a link to the previous logical page in the navigation panel +$PREVIOUS_PAGE_IN_NAVIGATION = 1; + +$INFO = 0; # 0 = do not make a "About this document..." section + +# Reuse images generated during previous runs +$REUSE = 2; + +# When this is 1, the section numbers are shown. The section numbers should +# then match those that would have bee produced by LaTeX. +# The correct section numbers are obtained from the $FILE.aux file generated +# by LaTeX. +# Hiding the seciton numbers encourages use of particular sections +# as standalone documents. In this case the cross reference to a section +# is shown using the default symbol rather than the section number. +$SHOW_SECTION_NUMBERS = 0; + +### Other global variables ############################################### +$CHILDLINE = "

\n"; + +# This is the line width measured in pixels and it is used to right justify +# equations and equation arrays; +$LINE_WIDTH = 500; + +# Used in conjunction with AUTO_NAVIGATION +#$WORDS_IN_PAGE = 300; !!! +$WORDS_IN_PAGE = 50; + +# Affects ONLY the way accents are processed +$default_language = 'english'; + +# The value of this variable determines how many words to use in each +# title that is added to the navigation panel (see below) +# +$WORDS_IN_NAVIGATION_PANEL_TITLES = 4; + +# This number will determine the size of the equations, special characters, +# and anything which will be converted into an inlined image +# *except* "image generating environments" such as "figure", "table" +# or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$MATH_SCALE_FACTOR = 1.6; + +# This number will determine the size of +# image generating environments such as "figure", "table" or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$FIGURE_SCALE_FACTOR = 1.6; + + +# If this is set then intermediate files are left for later inspection. +# This includes $$_images.tex and $$_images.log created during image +# conversion. +# Caution: Intermediate files can be *enormous*. +$DEBUG = 0; + +# If both of the following two variables are set then the "Up" button +# of the navigation panel in the first node/page of a converted document +# will point to $EXTERNAL_UP_LINK. $EXTERNAL_UP_TITLE should be set +# to some text which describes this external link. +$EXTERNAL_UP_LINK = ""; +$EXTERNAL_UP_TITLE = ""; + +# If this is set then the resulting HTML will look marginally better if viewed +# with Netscape. +$NETSCAPE_HTML = 0; + +# Valid paper sizes are "letter", "legal", "a4","a3","a2" and "a0" +# Paper sizes has no effect other than in the time it takes to create inlined +# images and in whether large images can be created at all ie +# - larger paper sizes *MAY* help with large image problems +# - smaller paper sizes are quicker to handle +$PAPERSIZE = "a4"; + +# Replace "english" with another language in order to tell LaTeX2HTML that you +# want some generated section titles (eg "Table of Contents" or "References") +# to appear in a different language. Currently only "english" and "french" +# is supported but it is very easy to add your own. See the example in the +# file "latex2html.config" +$TITLES_LANGUAGE = "english"; + +### Navigation Panel ########################################################## +# +# The navigation panel is constructed out of buttons and section titles. +# These can be configured in any combination with arbitrary text and +# HTML tags interspersed between them. +# The buttons available are: +# $PREVIOUS - points to the previous section +# $UP - points up to the "parent" section +# $NEXT - points to the next section +# $NEXT_GROUP - points to the next "group" section +# $PREVIOUS_GROUP - points to the previous "group" section +# $CONTENTS - points to the contents page if there is one +# $INDEX - points to the index page if there is one +# +# If the corresponding section exists the button will contain an +# active link to that section. If the corresponding section does +# not exist the button will be inactive. +# +# Also for each of the $PREVIOUS $UP $NEXT $NEXT_GROUP and $PREVIOUS_GROUP +# buttons there are equivalent $PREVIOUS_TITLE, $UP_TITLE, etc variables +# which contain the titles of their corresponding sections. +# Each title is empty if there is no corresponding section. +# +# The subroutine below constructs the navigation panels in each page. +# Feel free to mix and match buttons, titles, your own text, your logos, +# and arbitrary HTML (the "." is the Perl concatenation operator). + + +@my_icon_tags = (); +$my_icon_tags{'next'} = 'Next Page'; +$my_icon_tags{'next_page'} = 'Next Page'; +$my_icon_tags{'previous'} = 'Previous Page'; +$my_icon_tags{'previous_page'} = 'Previous Page'; +$my_icon_tags{'up'} = 'Up One Level'; +$my_icon_tags{'contents'} = 'Contents'; +$my_icon_tags{'index'} = 'Index'; +$my_icon_tags{'modules'} = 'Module Index'; + +@my_icon_names = (); +$my_icon_names{'previous_page'} = 'prev'; +$my_icon_names{'next_page'} = 'next'; + + +sub get_my_icon($) { + my $icon_file; + my $name = @_[0]; + my $text = $my_icon_tags{$name}; + if ($my_icon_names{$name}) { + $name = $my_icon_names{$name}; + } + if ($text eq '') { + $name = 'blank'; + } + $icon_file = $name . "." . $IMAGE_TYPE; + $used_icons{$icon_file} = 1; + return "\"$text\""; +} + + +sub use_my_icon($) { + my $s = @_[0]; + if ($s =~ /\/) { + my $r = get_my_icon($1); + $s =~ s/\/$r/; + } + return $s; +} + + +sub make_top_nav_panel() { + my $s; + $s = ('' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
$t_title
" + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
" + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
\n" + . "
\n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub make_bot_nav_panel() { + my $s; + $s = ('
' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
$t_title
" + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
" + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
\n" + . "
\n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub top_navigation_panel { + return "\n" + . make_top_nav_panel() + . "
\n"; +} + + +sub bot_navigation_panel { + return "\n

\n" + . make_bot_nav_panel() + . "\n"; +} + + +#$EXTERNAL_STYLESHEET = "../ASIM.css"; + +$ADDRESS = "Sophie BELLOEIL
20051116.1"; + +$LOCAL_ICONS = 0; + +$USING_STYLES = 1; + +$TRANSPARENT_FIGURES = 1; + +$WHITE_BACKGROUND = 0; + +$used_icons{"home." . $IMAGE_TYPE} = 1; + +1; # This must be the last line diff --git a/stratus1/doc/ASIM.css b/stratus1/doc/ASIM.css new file mode 100644 index 00000000..180cadb3 --- /dev/null +++ b/stratus1/doc/ASIM.css @@ -0,0 +1,164 @@ + + html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 { + font-size: 100%; + font-family: verdana, sans-serif; + } + + body { + color: black; + background: white; + background-color: white; + background-position: top left; + background-attachment: fixed; + background-repeat: no-repeat; + margin-top: 2em; + margin-right: 10%; + margin-left: 10%; + } + + hr { + height: 1px; + border: 0; + color: #004400; + background-color: #004400; + } + + + h1, h2, h3, h4, h5, h6 { + font-family: verdana, sans-serif; + } + + h1 { text-align: center; } + h2, h3, h4, h5, h6 { text-align: left; + padding-top: 2em; + } + h1, h2, h3 { font-family: "Trebuchet MS", sans-serif; + color: #09550B; + } + h1 { font-weight: bold; font-size: 170%; } + h2 { font-weight: bold; font-size: 140%; } + h3 { font-weight: bold; font-size: 118%; } + h4 { font-weight: bold; font-size: 100%; } + h5 { font-style: italic; font-size: 100%; } + h6 { font-variant: small-caps; font-size: 100%; } + + .hide { + display: none; + color: white; + } + + + div.navigation { margin-bottom: 1em; } + div.navigation h1 { margin-top: 2em; clear: both; } + div.navigation table { margin-left: 2em; font-size: 90%; } + div.navigation img { color: white; border: none; } + + + p { + margin-top: 0.6em; + margin-bottom: 0.6em; + margin-left: 0.0em; + margin-right: 0.0em; + } + + p.copyright { font-size: 90%; } + p.copyright small { font-size: 80%; } + + p.changed { + padding-left: 0.2em; + border-left: solid; + border-top: none; + border-bottom: none; + border-right: none; + border-left-width: thin; + border-color: red; + } + + + address { + text-align: right; + font-weight: bold; + font-style: italic; + font-size: 80%; + } + + + blockquote { + margin-left: 4em; + margin-right: 4em; + margin-top: 0.8em; + margin-bottom: 0.8em; + font-style: italic; + color: #003300; + } + + blockquote p { + margin-bottom: 0; + } + + blockquote address { + margin: 0; + } + + + table { + border-collapse: collapse; + /* + margin-left: 0em; + margin-right: 0em; + */ + margin-top: 0.8em; + margin-bottom: 0.8em; + } + + dt, dd { margin-top: 0; margin-bottom: 0; } + dt { font-weight: bold; } + + + pre, tt, code { + font-family: "andale mono", monospace; + font-size: 100%; + white-space: pre; + } + + pre { + font-size: 80%; + border: solid; + border-width: thin; + border-color: #003300; + background-color: #EEEEEE; + padding: 0.5em; + margin-left: 2em; + margin-right: 2em + } + + tt { color: green; } + em { font-style: italic; font-weight: bold; } + strong { font-weight: bold; } + + span.textit { font-style: italic; } + span.textbf { font-weight: bold; } + + .small { font-size: 90%; } + .white { color: #FFFFFF; } + + + ul.toc { + list-style: disc; + list-style: none; + } + + + a:link img, a:visited img { border-style: none; } + a img { color: white; } + + a:link, a:active, a:visited { + color: #09550B; + text-decoration: none; + } + + a:hover, a:focus { + color: #FF9900; + text-decoration: underline; + } + diff --git a/stratus1/doc/Makefile.am b/stratus1/doc/Makefile.am new file mode 100644 index 00000000..58c4276a --- /dev/null +++ b/stratus1/doc/Makefile.am @@ -0,0 +1,2 @@ + +SUBDIRS = stratus dpgen developper patterns diff --git a/stratus1/doc/Makefile.manual b/stratus1/doc/Makefile.manual new file mode 100644 index 00000000..671f308c --- /dev/null +++ b/stratus1/doc/Makefile.manual @@ -0,0 +1,34 @@ +all : stratus.pdf stratus/index.html ASIM.css stratus/ASIM.css + +stratus.pdf: *.tex + @pdflatex stratus.tex + @pdflatex stratus.tex +# xdvi stratus.dvi + +viewpdf: stratus.pdf + @acroread stratus.pdf & + + +stratus/index.html: *.tex + @latex2html -no_math -html_version 4.0,math -style ./ASIM.css stratus.tex + +stratus/ASIM.css: ASIM.css + @cp -p ASIM.css stratus/ASIM.css + + +orthographe: stratus.tex + aspell -t --lang=fr -c $< + +clean: + @rm -rf *.dvi \ + *.ps \ + *.lof \ + *.log \ + *.out \ + *.toc \ + *.aux \ + *.bak \ + stratus/*.html \ + stratus/*.css \ + stratus/*.pl \ + stratus/WARNINGS diff --git a/stratus1/doc/developper/.latex2html-init b/stratus1/doc/developper/.latex2html-init new file mode 100644 index 00000000..41736623 --- /dev/null +++ b/stratus1/doc/developper/.latex2html-init @@ -0,0 +1,308 @@ + +# -*- Perl -*- +# +#LaTeX2HTML Version 96.1 : dot.latex2html-init +# +### Command Line Argument Defaults ####################################### + +$MAX_SPLIT_DEPTH = 4; # Stop making separate files at this depth + +$MAX_LINK_DEPTH = 2; # Stop showing child nodes at this depth + +$NOLATEX = 0; # 1 = do not pass unknown environments to Latex + +$EXTERNAL_IMAGES = 0; # 1 = leave the images outside the document + +$ASCII_MODE = 0; # 1 = do not use any icons or internal images + +# 1 = use links to external postscript images rather than inlined bitmap +# images. +$PS_IMAGES = 0; + +#$TITLE = "Titre"; # The default is "No Title" + +$DESTDIR = ''; # Put the result in this directory + +# When this is set, the generated HTML files will be placed in the +# current directory. If set to 0 the default behaviour is to create (or reuse) +# another file directory. +$NO_SUBDIR = 0; + + +# Supply your own string if you don't like the default +$ADDRESS = "$address_data[0]
\n$address_data[1]"; + +$NO_NAVIGATION = 0; # 1 = do not put a navigation panel at the top of each page + +# Put navigation links at the top of each page. +# If the page exceeds $WORDS_IN_PAGE number of words then put one at the bottom of the page. +$AUTO_NAVIGATION = 1; + +# Put a link to the index page in the navigation panel +$INDEX_IN_NAVIGATION = 1; + +# Put a link to the table of contents in the navigation panel +$CONTENTS_IN_NAVIGATION = 1; + +# Put a link to the next logical page in the navigation panel +$NEXT_PAGE_IN_NAVIGATION = 1; + +# Put a link to the previous logical page in the navigation panel +$PREVIOUS_PAGE_IN_NAVIGATION = 1; + +$INFO = 0; # 0 = do not make a "About this document..." section + +# Reuse images generated during previous runs +$REUSE = 2; + +# When this is 1, the section numbers are shown. The section numbers should +# then match those that would have bee produced by LaTeX. +# The correct section numbers are obtained from the $FILE.aux file generated +# by LaTeX. +# Hiding the seciton numbers encourages use of particular sections +# as standalone documents. In this case the cross reference to a section +# is shown using the default symbol rather than the section number. +$SHOW_SECTION_NUMBERS = 0; + +### Other global variables ############################################### +$CHILDLINE = "

\n"; + +# This is the line width measured in pixels and it is used to right justify +# equations and equation arrays; +$LINE_WIDTH = 500; + +# Used in conjunction with AUTO_NAVIGATION +#$WORDS_IN_PAGE = 300; !!! +$WORDS_IN_PAGE = 50; + +# Affects ONLY the way accents are processed +$default_language = 'english'; + +# The value of this variable determines how many words to use in each +# title that is added to the navigation panel (see below) +# +$WORDS_IN_NAVIGATION_PANEL_TITLES = 4; + +# This number will determine the size of the equations, special characters, +# and anything which will be converted into an inlined image +# *except* "image generating environments" such as "figure", "table" +# or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$MATH_SCALE_FACTOR = 1.6; + +# This number will determine the size of +# image generating environments such as "figure", "table" or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$FIGURE_SCALE_FACTOR = 1.6; + + +# If this is set then intermediate files are left for later inspection. +# This includes $$_images.tex and $$_images.log created during image +# conversion. +# Caution: Intermediate files can be *enormous*. +$DEBUG = 0; + +# If both of the following two variables are set then the "Up" button +# of the navigation panel in the first node/page of a converted document +# will point to $EXTERNAL_UP_LINK. $EXTERNAL_UP_TITLE should be set +# to some text which describes this external link. +$EXTERNAL_UP_LINK = ""; +$EXTERNAL_UP_TITLE = ""; + +# If this is set then the resulting HTML will look marginally better if viewed +# with Netscape. +$NETSCAPE_HTML = 0; + +# Valid paper sizes are "letter", "legal", "a4","a3","a2" and "a0" +# Paper sizes has no effect other than in the time it takes to create inlined +# images and in whether large images can be created at all ie +# - larger paper sizes *MAY* help with large image problems +# - smaller paper sizes are quicker to handle +$PAPERSIZE = "a4"; + +# Replace "english" with another language in order to tell LaTeX2HTML that you +# want some generated section titles (eg "Table of Contents" or "References") +# to appear in a different language. Currently only "english" and "french" +# is supported but it is very easy to add your own. See the example in the +# file "latex2html.config" +$TITLES_LANGUAGE = "english"; + +### Navigation Panel ########################################################## +# +# The navigation panel is constructed out of buttons and section titles. +# These can be configured in any combination with arbitrary text and +# HTML tags interspersed between them. +# The buttons available are: +# $PREVIOUS - points to the previous section +# $UP - points up to the "parent" section +# $NEXT - points to the next section +# $NEXT_GROUP - points to the next "group" section +# $PREVIOUS_GROUP - points to the previous "group" section +# $CONTENTS - points to the contents page if there is one +# $INDEX - points to the index page if there is one +# +# If the corresponding section exists the button will contain an +# active link to that section. If the corresponding section does +# not exist the button will be inactive. +# +# Also for each of the $PREVIOUS $UP $NEXT $NEXT_GROUP and $PREVIOUS_GROUP +# buttons there are equivalent $PREVIOUS_TITLE, $UP_TITLE, etc variables +# which contain the titles of their corresponding sections. +# Each title is empty if there is no corresponding section. +# +# The subroutine below constructs the navigation panels in each page. +# Feel free to mix and match buttons, titles, your own text, your logos, +# and arbitrary HTML (the "." is the Perl concatenation operator). + + +@my_icon_tags = (); +$my_icon_tags{'next'} = 'Next Page'; +$my_icon_tags{'next_page'} = 'Next Page'; +$my_icon_tags{'previous'} = 'Previous Page'; +$my_icon_tags{'previous_page'} = 'Previous Page'; +$my_icon_tags{'up'} = 'Up One Level'; +$my_icon_tags{'contents'} = 'Contents'; +$my_icon_tags{'index'} = 'Index'; +$my_icon_tags{'modules'} = 'Module Index'; + +@my_icon_names = (); +$my_icon_names{'previous_page'} = 'prev'; +$my_icon_names{'next_page'} = 'next'; + + +sub get_my_icon($) { + my $icon_file; + my $name = @_[0]; + my $text = $my_icon_tags{$name}; + if ($my_icon_names{$name}) { + $name = $my_icon_names{$name}; + } + if ($text eq '') { + $name = 'blank'; + } + $icon_file = $name . "." . $IMAGE_TYPE; + $used_icons{$icon_file} = 1; + return "\"$text\""; +} + + +sub use_my_icon($) { + my $s = @_[0]; + if ($s =~ /\/) { + my $r = get_my_icon($1); + $s =~ s/\/$r/; + } + return $s; +} + + +sub make_top_nav_panel() { + my $s; + $s = ('' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
$t_title
" + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
" + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
\n" + . "
\n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub make_bot_nav_panel() { + my $s; + $s = ('
' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
$t_title
" + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
" + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
\n" + . "
\n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub top_navigation_panel { + return "\n" + . make_top_nav_panel() + . "
\n"; +} + + +sub bot_navigation_panel { + return "\n

\n" + . make_bot_nav_panel() + . "\n"; +} + + +#$EXTERNAL_STYLESHEET = "../ASIM.css"; + +$ADDRESS = "Sophie BELLOEIL
20051116.1"; + +$LOCAL_ICONS = 0; + +$USING_STYLES = 1; + +$TRANSPARENT_FIGURES = 1; + +$WHITE_BACKGROUND = 0; + +$used_icons{"home." . $IMAGE_TYPE} = 1; + +1; # This must be the last line diff --git a/stratus1/doc/developper/ASIM.css b/stratus1/doc/developper/ASIM.css new file mode 100644 index 00000000..180cadb3 --- /dev/null +++ b/stratus1/doc/developper/ASIM.css @@ -0,0 +1,164 @@ + + html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 { + font-size: 100%; + font-family: verdana, sans-serif; + } + + body { + color: black; + background: white; + background-color: white; + background-position: top left; + background-attachment: fixed; + background-repeat: no-repeat; + margin-top: 2em; + margin-right: 10%; + margin-left: 10%; + } + + hr { + height: 1px; + border: 0; + color: #004400; + background-color: #004400; + } + + + h1, h2, h3, h4, h5, h6 { + font-family: verdana, sans-serif; + } + + h1 { text-align: center; } + h2, h3, h4, h5, h6 { text-align: left; + padding-top: 2em; + } + h1, h2, h3 { font-family: "Trebuchet MS", sans-serif; + color: #09550B; + } + h1 { font-weight: bold; font-size: 170%; } + h2 { font-weight: bold; font-size: 140%; } + h3 { font-weight: bold; font-size: 118%; } + h4 { font-weight: bold; font-size: 100%; } + h5 { font-style: italic; font-size: 100%; } + h6 { font-variant: small-caps; font-size: 100%; } + + .hide { + display: none; + color: white; + } + + + div.navigation { margin-bottom: 1em; } + div.navigation h1 { margin-top: 2em; clear: both; } + div.navigation table { margin-left: 2em; font-size: 90%; } + div.navigation img { color: white; border: none; } + + + p { + margin-top: 0.6em; + margin-bottom: 0.6em; + margin-left: 0.0em; + margin-right: 0.0em; + } + + p.copyright { font-size: 90%; } + p.copyright small { font-size: 80%; } + + p.changed { + padding-left: 0.2em; + border-left: solid; + border-top: none; + border-bottom: none; + border-right: none; + border-left-width: thin; + border-color: red; + } + + + address { + text-align: right; + font-weight: bold; + font-style: italic; + font-size: 80%; + } + + + blockquote { + margin-left: 4em; + margin-right: 4em; + margin-top: 0.8em; + margin-bottom: 0.8em; + font-style: italic; + color: #003300; + } + + blockquote p { + margin-bottom: 0; + } + + blockquote address { + margin: 0; + } + + + table { + border-collapse: collapse; + /* + margin-left: 0em; + margin-right: 0em; + */ + margin-top: 0.8em; + margin-bottom: 0.8em; + } + + dt, dd { margin-top: 0; margin-bottom: 0; } + dt { font-weight: bold; } + + + pre, tt, code { + font-family: "andale mono", monospace; + font-size: 100%; + white-space: pre; + } + + pre { + font-size: 80%; + border: solid; + border-width: thin; + border-color: #003300; + background-color: #EEEEEE; + padding: 0.5em; + margin-left: 2em; + margin-right: 2em + } + + tt { color: green; } + em { font-style: italic; font-weight: bold; } + strong { font-weight: bold; } + + span.textit { font-style: italic; } + span.textbf { font-weight: bold; } + + .small { font-size: 90%; } + .white { color: #FFFFFF; } + + + ul.toc { + list-style: disc; + list-style: none; + } + + + a:link img, a:visited img { border-style: none; } + a img { color: white; } + + a:link, a:active, a:visited { + color: #09550B; + text-decoration: none; + } + + a:hover, a:focus { + color: #FF9900; + text-decoration: underline; + } + diff --git a/stratus1/doc/developper/Makefile b/stratus1/doc/developper/Makefile new file mode 100644 index 00000000..f87d676b --- /dev/null +++ b/stratus1/doc/developper/Makefile @@ -0,0 +1,37 @@ +all : stratus.pdf stratus/index.html ASIM.css stratus/ASIM.css + +stratus.pdf: *.tex + @pdflatex stratus.tex + @pdflatex stratus.tex +# xdvi stratus.dvi + +viewpdf: stratus.pdf + @acroread stratus.pdf & + + +stratus/index.html: *.tex + @latex2html -no_math -html_version 4.0,math -style ./ASIM.css stratus.tex + +stratus/ASIM.css: ASIM.css + @cp -p ASIM.css stratus/ASIM.css + + +orthographe: stratus.tex + aspell -t --lang=fr -c $< + +clean: + @rm -rf *.dvi \ + *.ps \ + *.lof \ + *.log \ + *.out \ + *.toc \ + *.aux \ + *.bak \ + stratus.pdf \ + stratus/*.html \ + stratus/*.css \ + stratus/*.pl \ + stratus/WARNINGS + @rm -rf stratus/* + @rmdir stratus diff --git a/stratus1/doc/developper/Makefile.am b/stratus1/doc/developper/Makefile.am new file mode 100644 index 00000000..cd38979d --- /dev/null +++ b/stratus1/doc/developper/Makefile.am @@ -0,0 +1,70 @@ + +doc_en_latex_stratusdevdir = $(datadir)/doc/en/latex/stratusdev +doc_en_html_stratusdevdir = $(datadir)/doc/en/html/stratusdev +doc_en_pdf_stratusdevdir = $(datadir)/doc/en/pdf/stratusdev + + +doc_en_stratus_EXTRA = stratus.tex \ + man_inst.tex \ + man_net.tex \ + man_model.tex \ + man_stratus.tex \ + html.entry \ + ASIM.css \ + .latex2html-init + + +install-data-hook: + @if [ `which latex2html 2>/dev/null` ]; then \ + for file in `ls $(srcdir)/*.tex`; do \ + filename=`basename $$file`; \ + if [ ! -L $$filename -a ! -f $$filename ]; then \ + ln -sf $(srcdir)/$$filename . ; \ + fi ; \ + done ; \ + if [ ! -L ASIM.css -a ! -f ASIM.css ]; then \ + ln -sf $(srcdir)/*.css . ; \ + ln -sf $(srcdir)/.latex2html-init . ; \ + $(mkinstalldirs) images ; \ + ln -sf $(srcdir)/images/*.png ./images/ ; \ + fi ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_latex_stratusdevdir) ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_latex_stratusdevdir)/images ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_html_stratusdevdir) ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_pdf_stratusdevdir) ; \ + cp -r *.tex $(DESTDIR)$(doc_en_latex_stratusdevdir) ; \ + cp -r *.css $(DESTDIR)$(doc_en_latex_stratusdevdir) ; \ + cp -r .latex2html-init $(DESTDIR)$(doc_en_latex_stratusdevdir) ; \ + cp -r images/*.png $(DESTDIR)$(doc_en_latex_stratusdevdir)/images ; \ + rm -f *.aux *.lof *.log *.out *.toc *.dvi ; \ + latex2html -no_math -html_version 4.0,math -style ./ASIM.css stratus.tex ; \ + cp -pr stratus/* $(DESTDIR)$(doc_en_html_stratusdevdir) ; \ + cp -p ASIM.css $(DESTDIR)$(doc_en_html_stratusdevdir)/ASIM.css ; \ + pdflatex stratus.tex ; \ + pdflatex stratus.tex ; \ + cp stratus.pdf $(DESTDIR)$(doc_en_pdf_stratusdevdir) ; \ + cp $(srcdir)/html.entry $(DESTDIR)$(doc_en_html_stratusdevdir); \ + if [ -x $(datadir)/doc/en/html/generateIndex.sh ]; then \ + $(datadir)/doc/en/html/generateIndex.sh \ + --prefix=${prefix} --destdir=$(DESTDIR) ; \ + fi ; \ + else \ + echo "[WARNING] latex2html not found, skipping doc generation."; \ + fi + + +EXTRA_DIST = $(doc_en_stratus_EXTRA) + +CLEANFILES = *.dvi \ + *.ps \ + *.lof \ + *.log \ + *.out \ + *.toc \ + *.aux \ + *.bak \ + stratus/*.html \ + stratus/*.css \ + stratus/*.pl \ + stratus/WARNINGS + diff --git a/stratus1/doc/developper/html.entry b/stratus1/doc/developper/html.entry new file mode 100644 index 00000000..e6bd336f --- /dev/null +++ b/stratus1/doc/developper/html.entry @@ -0,0 +1 @@ +

  • Stratus Dev
    Stratus Developpers Documentation

    diff --git a/stratus1/doc/developper/man_inst.tex b/stratus1/doc/developper/man_inst.tex new file mode 100644 index 00000000..5a04702e --- /dev/null +++ b/stratus1/doc/developper/man_inst.tex @@ -0,0 +1,50 @@ +\subsection{Synopsys} + +\begin{verbatim} +Inst ( model + , name + , map = myMap + ) +\end{verbatim} + +\subsection{Description} + +Instantiation of an instance. The type of the instance is given by the \verb-model- parameter. The connexions are made thanks to the \verb-map- parameters. + +\subsection{Parameters} + +\begin{itemize} + \item \verb-model- : Name of the mastercell of the instance to create (mandatory argument) + \item \verb-name- : Name of the instance (optional)\\ +When this argument is not defined, the instance has a name created by default. This argument is usefull when one wants to create a layout as well. Indeed, the placement of the instances is much easier when the conceptor has chosen himself the name f the instances. + \item \verb-map- : Dictionnary for connexions in order to make the netlist\\ +\end{itemize} + +\subsection{Attributes} + +\begin{itemize} + \item \verb-_name- : Name of the instance (the name given as parameter if there's one, a name created otherwise) + \item \verb-_model- : Name of the model given as argument + \item \verb-_real_model- : Name of the model created thanks to \verb-_model- and all the parameters + \item \verb-_map- : Dictionnary \verb-map- given at the instanciation + \item \verb-_param- : Dictionnary \verb-param- given at the instanciation + \item \verb-_st_cell- : The stratus cell which the instance is instanciated in + \item \verb-_st_masterCell- : The stratus master cell of the instance\\ +\end{itemize} +\indent For placement : +\begin{itemize} + \item \verb-_plac- : tells if the instance is placed or not (UNPLACED by default) + \item \verb-_x-, \verb-_y- : the coordinates of the instance (only for placed instances) + \item \verb-_sym- : the symetry of the instance (only for placed instances)\\ +\end{itemize} +\indent And, in connection with Hurricane : +\begin{itemize} + \item \verb-_hur_instance- : The hurricane instance (None by default) + \item \verb-_hur_masterCell- : The Hurricane master cell of the instance (None by default) +\end{itemize} + +\subsection{Methods} + +\begin{itemize} + \item Delete : Deletion of the Hurricane instance +\end{itemize} diff --git a/stratus1/doc/developper/man_model.tex b/stratus1/doc/developper/man_model.tex new file mode 100644 index 00000000..212e2f00 --- /dev/null +++ b/stratus1/doc/developper/man_model.tex @@ -0,0 +1,66 @@ +\subsection{Synopsys} + +\begin{verbatim} +class myClass ( Model ) : + ... + +exemple = myClass ( name, param ) +\end{verbatim} + +\subsection{Description} + +Every cell made is a class herited from class \verb-Model-.\\ +\indent Some methods have to be created, like \verb-Interface-, \verb-Netlist- ... Some methods are inherited from the class \verb-Model-. + +\subsection{Parameters} + +\begin{itemize} + \item \verb-name- : The name of the cell (which is the name of the files which will be created) + \item \verb-param- : A dictionnary which gives all the parameters useful in order to create the cell +\end{itemize} + +\subsection{Attributes} + +\begin{itemize} + \item \verb-_name- : Name of the cell + \item \verb-_st_insts- : List of all the instances of the cell + \item \verb-_st_ports- : List of all the external nets of the cell (except for alimentations and clock) + \item \verb-_st_sigs- : List of all the internal nets of the cell + \item \verb-_st_vdds-, \verb-_st_vsss- : Two tabs of the nets which are instancied as \verb-VddIn- and \verb-VssIn- + \item \verb-_st_cks- : List of all the nets which are instancied as \verb-CkIn- + \item \verb-_st_merge- : List of all the internal nets which have to be merged + \item \verb-_param- : The map given as argument at the creation of the cell + \item \verb-_underCells- : List of all the instances which are cells that have to be created + \item \verb-_and-, \verb-_or-, \verb-_xor-, \verb-_not-, \verb-_buff-, \verb-_mux-, \verb-_reg-, \verb-_shift-, \verb-_comp-, \verb-_add-, \verb-_mult-, \verb-_div- : tells which generator to use when using overloard + \item \verb-_NB_INST- : The number of instances of the cell (useful in order to automatically give a name to the instances) + \item \verb-_TAB_NETS_OUT- and \verb-_TAB_NETS_CAT- : Lists of all the nets automatically created + \item \verb-_insref- : The reference instance (for placement)\\ +\end{itemize} + +\indent And, in connection with Hurricane : +\begin{itemize} + \item \verb-_hur_cell- : The hurricane cell (None by default) + \item \verb-_db- : The database + \item \verb-_lib0- : \verb-self._db.Get_CATA_LIB ( 0 )- + \item \verb-_nb_alims_verticales-, \verb-_nb_pins-, \verb-_nb_vdd_pins-, \verb-_nb_vss_pins-, \verb-standard_instances_list-, \verb-pad_north-, \verb-pad_south-, \verb-pad_east-, \verb-pad_west- : all place and route stuffs ... + +\end{itemize} + +\subsection{Methods} + +Methods of class \verb-Model- are listed below : +\begin{itemize} + \item \verb-HurricanePlug- : Creates the Hurricane cell thanks to the stratus cell.\\Before calling this method, only the stratus cell is created, after this method, both cells are created. This method has to be called before View and Save, and before Layout. + \item \verb-View- : Opens/Refreshes the editor in order to see the created layout + \item \verb-Quit- : Finishes a cell without saving + \item \verb-Save- : Saves the created cell\\If several cells have been created, they are all going to be saved in separated files\\ +\end{itemize} + +Some of those methods have to be defined in order to create a new cell : +\begin{itemize} + \item \verb-Interface- : Description of the external ports of the cell + \item \verb-Netlist- : Description of the netlist of the cell + \item \verb-Layout- : Description of the layout of the cell + \item \verb-Vbe- : Description of the behavior of the cell + \item \verb-Pattern- : Description of the patterns in order to test the cell +\end{itemize} diff --git a/stratus1/doc/developper/man_net.tex b/stratus1/doc/developper/man_net.tex new file mode 100644 index 00000000..67717248 --- /dev/null +++ b/stratus1/doc/developper/man_net.tex @@ -0,0 +1,73 @@ +\subsection{Synopsys} + +\begin{verbatim} +netInput = SignalIn ( name, arity ) +\end{verbatim} + +\subsection{Description} + +Instanciation of net. Differents kind of nets are listed below : +\begin{itemize} + \item \verb-SignalIn- : Creation of an input port + \item \verb-SignalOut- : Creation of an output port + \item \verb-SignalInOut- : Creation of an inout port + \item \verb-SignalUnknown- : Creation of an input/output port which direction is not defined + \item \verb-TriState- : Creation of a tristate port + \item \verb-CkIn- : Creation of a clock port + \item \verb-VddIn- : Creation of the vdd alimentation + \item \verb-VssIn- : Creation of the vss alimentation + \item \verb-Signal- : Creation of an internal net +\end{itemize} + +\subsection{Parameters} + +\begin{itemize} + \item \verb-name- : Name of the net (mandatory argument) + \item \verb-arity- : Arity of the net (mandatory argument) + \item \verb-indice- : For buses only : the LSB bit (optional argument : set to 0 by default)\\ +\end{itemize} + +\indent Only \verb-CkIn, -\verb-VddIn- and \verb-VssIn- do not have the same parameters : there is only the \verb-name- parameter (they are 1 bit nets). + +\subsection{Attributes} + +\begin{itemize} + \item \verb-_name- : Name of the net + \item \verb-_arity- : Arity of the net (by default set to 0) + \item \verb-_ind- : LSB of the net + \item \verb-_ext- : Tells if the net is external or not (True/False) + \item \verb-_direct- : If the net is external, tells the direction ("IN", "OUT", "INOUT", "TRISTATE", "UNKNOWN") + \item \verb-_h_type- : If the net is an alimentation or a clock, tells the type ("POWER", "GROUND", "CLOCK") + \item \verb-_type- : The arithmetic type of the net ( "nr" ) + \item \verb-_st_cell- : The stratus cell which the net is instanciated in + \item \verb-_real_net- : If the net is a part of a net (Sig) it is the real net corresponding + \item \verb-_alias- : [] by default. When the net has an alias, it's a tab. Each element of the tab correspond to a bit of the net (from the LSB to the MSB), it'a a dictionnary : the only key is the net which this net is an alias from, the value is the bit of the net + \item \verb-_to_merge- : [] by default. The same as \_alias + \item \verb-_to_cat- : [] by default. The same as \_alias\\ +\end{itemize} + +\indent And, in connection with Hurricane : +\begin{itemize} + \item \verb-_hur_net- : A tab with all the hurricane nets corresponding to the stratus net ; From the LSB to the MSB (for example, with a 1 bit net, one gets the hurricane net by doing : \verb-net._hur_net[0]- ). +\end{itemize} + +\subsection{Methods} + +\begin{itemize} + \item \verb-Buffer- : Instanciation of a Buffer + \item \verb-Shift- : Instanciation of a shifter + \item \verb-Mux- : Instanciation of a multiplexor + \item \verb-Reg- : Instanciation of a register + \item \verb-Eq/Ne- : Instanciation of comparison generator + \item \verb-Extend- : A net is extended + \item \verb-Alias- : A net is an alias of another net + \item \verb-Delete- : Deletion of the Hurricane nets\\ +\end{itemize} +\indent And the overloards : +\begin{itemize} + \item \_\_init\_\_ : Initialisation of nets + \item \_\_le\_\_ : initialisation of a net thanks to <= notation + \item \_\_getitem\_\_, \_\_geslice\_\_ : Creation of "Sig" nets : which are part of nets (use of \verb-[]- and \verb-[:]-) + \item \_\_and\_\_, \_\_or\_\_, \_\_xor\_\_, \_\_invert\_\_ : boolean operation with \&, |, \^ , ~ + \item \_\_add\_\_, \_\_mul\_\_, \_\_div\_\_ : arithmetic operators with +, * and / +\end{itemize} diff --git a/stratus1/doc/developper/man_stratus.tex b/stratus1/doc/developper/man_stratus.tex new file mode 100644 index 00000000..840123c7 --- /dev/null +++ b/stratus1/doc/developper/man_stratus.tex @@ -0,0 +1,119 @@ +\subsubsection{Name} + +Stratus -- Procedural design language based upon \emph{Python} + +\subsubsection{Description} + +\emph{Stratus} is a set of \emph{Python} methods/functions dedicated to procedural generation purposes. From a user point of view, \emph{Stratus} is a circuit's description language that allows \emph{Python} programming flow control, variable use, and specialized functions in order to handle vlsi objects.\\ + +\indent Based upon the \emph{Hurricane} data structures, the \emph{Stratus} language gives the user the ability to describe netlist and layout views. + +\subsubsection{Creation of a cell} + +A cell is a hierachical structural description of a circuit in terms of ports (I/Os), signals (nets) and instances : + +\begin{itemize} +\item Method \verb-Interface- + \begin{itemize} + \item LogicIn + \item LogicOut + \item LogicInOut + \item TriState + \item VddIn + \item VssIn + \end{itemize} +\item Method \verb-Netlist- + \begin{itemize} + \item Signal + \item Inst + \item Facilities : \&, |, +, Mux, Shift, Eq/Ne ... + \end{itemize} +\item Method \verb-Layout- + \begin{itemize} + \item Place, PlaceTop, PlaceBottom, PlaceRight, PlaceLeft + \item SetRefIns + \item DefAb, ResizeAb + \item PlaceCentric + \item PlaceGlue, FillCell + \item PadNorth, PadSouth, PadEast, PadWest + \item AlimVerticalRail, AlimHorizontalRail + \item AlimConnectors + \item PowerRing + \item RouteCk + \end{itemize} + \item Method \verb-Pattern- + \item Method \verb-View- + \item Method \verb-Save- +\end{itemize} + +\subsubsection{Syntax highlighting} + +This chapter describes what to do to have the right syntax highlighting when using vi. + +\begin{itemize} + \item Commands to do when you want to change once the coloration of your file : +\end{itemize} +\begin{small} +\begin{verbatim} +:syntax off +:source /asim/coriolis/share/etc/stratus.vim +\end{verbatim} +\end{small} +\begin{itemize} + \item Modification of your .vimrc in order to have the syntax highlighting each time you open a file : +\end{itemize} +\begin{small} +\begin{verbatim} +syntax off +autocmd BufRead,BufNewfile *.py so /asim/coriolis/share/etc/stratus.vim +syntax on +\end{verbatim} +\end{small} + +\subsubsection{Environment variables} + +\begin{itemize} + \item CRL\_IN\_LO, default value : \verb-def- + \item CRL\_OUT\_LO, default value : \verb-def- + \item CRL\_IN\_PH, default value : \verb-def- + \item CRL\_OUT\_PH, default value : \verb-def- + \item CRL\_CATA\_LIB, default value : \verb-.- + \item CRL\_CATAL\_NAME, default value : \verb-CATAL- +\end{itemize} + +\subsubsection{Syntax} + +A \emph{Stratus} file must have a .py extension and must begin as follow : +\begin{verbatim} +#!/usr/bin/python + +from stratus import * +\end{verbatim} + +\indent In order to execute a \emph{Stratus} file (named \verb-file- for example), one has two choices : +\begin{verbatim} +python file.py +\end{verbatim} +\indent Or : +\begin{verbatim} +chmod u+x file.py +./file.py +\end{verbatim} + +\indent The names used in \emph{Stratus}, as arguments to \emph{Stratus} functions, should be alphanumerical, including the underscore. The arguments of \emph{Stratus} are case sensitive, so \textsc{VDD} is not equivalent to \textsc{vdd}.\\ + +\indent Vectorized connectors or signal can be used using the \textsc{[n:m]} construct.\\ + +\subsubsection{Example} + +You can see a concrete example at : \hyperref[ref]{\emph{A concrete example}}{}{Example}{secexample} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Model}}{}{Model}{secmodel} +\hyperref[ref]{\emph{Param}}{}{Param}{secparam} +\hyperref[ref]{\emph{Example}}{}{Example}{secexample} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{Place and Route}}{}{Place and Route}{secroute} +\hyperref[ref]{\emph{Facilities}}{}{Facilities}{secfacilities} diff --git a/stratus1/doc/developper/see_also.tex b/stratus1/doc/developper/see_also.tex new file mode 100644 index 00000000..32299cf7 --- /dev/null +++ b/stratus1/doc/developper/see_also.tex @@ -0,0 +1,3 @@ +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} diff --git a/stratus1/doc/developper/stratus.out b/stratus1/doc/developper/stratus.out new file mode 100644 index 00000000..fa61b7db --- /dev/null +++ b/stratus1/doc/developper/stratus.out @@ -0,0 +1,18 @@ +\BOOKMARK [1][-]{section.1}{Class Model}{} +\BOOKMARK [2][-]{subsection.1.1}{Synopsys}{section.1} +\BOOKMARK [2][-]{subsection.1.2}{Description}{section.1} +\BOOKMARK [2][-]{subsection.1.3}{Parameters}{section.1} +\BOOKMARK [2][-]{subsection.1.4}{Attributes}{section.1} +\BOOKMARK [2][-]{subsection.1.5}{Methods}{section.1} +\BOOKMARK [1][-]{section.2}{Nets}{} +\BOOKMARK [2][-]{subsection.2.1}{Synopsys}{section.2} +\BOOKMARK [2][-]{subsection.2.2}{Description}{section.2} +\BOOKMARK [2][-]{subsection.2.3}{Parameters}{section.2} +\BOOKMARK [2][-]{subsection.2.4}{Attributes}{section.2} +\BOOKMARK [2][-]{subsection.2.5}{Methods}{section.2} +\BOOKMARK [1][-]{section.3}{Instances}{} +\BOOKMARK [2][-]{subsection.3.1}{Synopsys}{section.3} +\BOOKMARK [2][-]{subsection.3.2}{Description}{section.3} +\BOOKMARK [2][-]{subsection.3.3}{Parameters}{section.3} +\BOOKMARK [2][-]{subsection.3.4}{Attributes}{section.3} +\BOOKMARK [2][-]{subsection.3.5}{Methods}{section.3} diff --git a/stratus1/doc/developper/stratus.tex b/stratus1/doc/developper/stratus.tex new file mode 100644 index 00000000..2b331604 --- /dev/null +++ b/stratus1/doc/developper/stratus.tex @@ -0,0 +1,90 @@ +\documentclass[12pt]{article} +\usepackage[latin1]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{palatino} +\usepackage{fancyhdr} +\usepackage{float} +\usepackage{subfigure} +\usepackage{wrapfig} +\usepackage[dvips]{graphics} +\usepackage{graphicx} +\usepackage[french]{babel} +\usepackage{epsfig} +\usepackage{multicol} +\usepackage{color} +\usepackage{url} +\usepackage{html} + +\setlength{\topmargin}{0cm} +\setlength{\headheight}{1cm} +\setlength{\textheight}{21cm} +\setlength{\textwidth}{16cm} +\setlength{\oddsidemargin}{0cm} +\setlength{\evensidemargin}{0cm} +\setlength{\columnsep}{0.125in} +\setlength{\columnseprule}{0.5pt} +\setlength{\footskip}{1cm} +%\setlength{\hoffset}{-18pt} +%\setlength{\oddsidemargin}{0pt} % Marge gauche sur pages impaires +%\setlength{\evensidemargin}{9pt} % Marge gauche sur pages paires +%\setlength{\marginparwidth}{54pt} % Largeur de note dans la marge +%\setlength{\textwidth}{481pt} % Largeur de la zone de texte (17cm) +%\setlength{\voffset}{-18pt} % Bon pour DOS +%\setlength{\marginparsep}{7pt} % Séparation de la marge +%\setlength{\topmargin}{0pt} % Pas de marge en haut +%\setlength{\headheight}{13pt} % Haut de page +%\setlength{\headsep}{10pt} % Entre le haut de page et le texte +%\setlength{\footskip}{27pt} % Bas de page + séparation +%\setlength{\textheight}{708pt} % Hauteur de la zone de texte (25cm) +\sloppy + +\newcommand{\image}[4] +% {\begin{figure}[htbp] + {\begin{figure}[h!] + \includegraphics[width=#2\textwidth]{#1} + \end{figure} + } +% \image{fig.eps}{scale} + +%--------------------------------- page style -------------------------------- +\pagestyle{fancy} +\rhead{} +\lhead{} +\rfoot{\thepage} +\lfoot{} +\cfoot{} +%---------------------------------- document --------------------------------- +\date {} +\title {Stratus Developper's Manual} +\author {Sophie Belloeil} + +\begin{document} + +\setlength{\footrulewidth}{0.6pt} +\maketitle + +%%\begin{htmlonly} +%% \htmlrule +%% \noindent La version imprimable de ce document est disponible ici~: \\ +%% \begin{center} +%% \hyperref[hyper]{http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf}{}{} +%% {http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf} +%% \end{center} +%%\end{htmlonly} + +\tableofchildlinks +\htmlrule + +\section{Class Model} +\label{secmodel} +\input{man_model} + +\section{Nets} +\label{secnet} +\input{man_net} + +\section{Instances} +\label{secinst} +\input{man_inst} + +\end{document} diff --git a/stratus1/doc/developper/stratus/ASIM.css b/stratus1/doc/developper/stratus/ASIM.css new file mode 100644 index 00000000..180cadb3 --- /dev/null +++ b/stratus1/doc/developper/stratus/ASIM.css @@ -0,0 +1,164 @@ + + html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 { + font-size: 100%; + font-family: verdana, sans-serif; + } + + body { + color: black; + background: white; + background-color: white; + background-position: top left; + background-attachment: fixed; + background-repeat: no-repeat; + margin-top: 2em; + margin-right: 10%; + margin-left: 10%; + } + + hr { + height: 1px; + border: 0; + color: #004400; + background-color: #004400; + } + + + h1, h2, h3, h4, h5, h6 { + font-family: verdana, sans-serif; + } + + h1 { text-align: center; } + h2, h3, h4, h5, h6 { text-align: left; + padding-top: 2em; + } + h1, h2, h3 { font-family: "Trebuchet MS", sans-serif; + color: #09550B; + } + h1 { font-weight: bold; font-size: 170%; } + h2 { font-weight: bold; font-size: 140%; } + h3 { font-weight: bold; font-size: 118%; } + h4 { font-weight: bold; font-size: 100%; } + h5 { font-style: italic; font-size: 100%; } + h6 { font-variant: small-caps; font-size: 100%; } + + .hide { + display: none; + color: white; + } + + + div.navigation { margin-bottom: 1em; } + div.navigation h1 { margin-top: 2em; clear: both; } + div.navigation table { margin-left: 2em; font-size: 90%; } + div.navigation img { color: white; border: none; } + + + p { + margin-top: 0.6em; + margin-bottom: 0.6em; + margin-left: 0.0em; + margin-right: 0.0em; + } + + p.copyright { font-size: 90%; } + p.copyright small { font-size: 80%; } + + p.changed { + padding-left: 0.2em; + border-left: solid; + border-top: none; + border-bottom: none; + border-right: none; + border-left-width: thin; + border-color: red; + } + + + address { + text-align: right; + font-weight: bold; + font-style: italic; + font-size: 80%; + } + + + blockquote { + margin-left: 4em; + margin-right: 4em; + margin-top: 0.8em; + margin-bottom: 0.8em; + font-style: italic; + color: #003300; + } + + blockquote p { + margin-bottom: 0; + } + + blockquote address { + margin: 0; + } + + + table { + border-collapse: collapse; + /* + margin-left: 0em; + margin-right: 0em; + */ + margin-top: 0.8em; + margin-bottom: 0.8em; + } + + dt, dd { margin-top: 0; margin-bottom: 0; } + dt { font-weight: bold; } + + + pre, tt, code { + font-family: "andale mono", monospace; + font-size: 100%; + white-space: pre; + } + + pre { + font-size: 80%; + border: solid; + border-width: thin; + border-color: #003300; + background-color: #EEEEEE; + padding: 0.5em; + margin-left: 2em; + margin-right: 2em + } + + tt { color: green; } + em { font-style: italic; font-weight: bold; } + strong { font-weight: bold; } + + span.textit { font-style: italic; } + span.textbf { font-weight: bold; } + + .small { font-size: 90%; } + .white { color: #FFFFFF; } + + + ul.toc { + list-style: disc; + list-style: none; + } + + + a:link img, a:visited img { border-style: none; } + a img { color: white; } + + a:link, a:active, a:visited { + color: #09550B; + text-decoration: none; + } + + a:hover, a:focus { + color: #FF9900; + text-decoration: underline; + } + diff --git a/stratus1/doc/developper/stratus/WARNINGS b/stratus1/doc/developper/stratus/WARNINGS new file mode 100644 index 00000000..90f53c20 --- /dev/null +++ b/stratus1/doc/developper/stratus/WARNINGS @@ -0,0 +1,9 @@ +No implementation found for style `fontenc' +No implementation found for style `palatino' +No implementation found for style `fancyheadings' +No implementation found for style `subfigure' +No implementation found for style `graphicx' +No implementation found for style `url' +couldn't convert character ,circ into available encodings + + ...set $ACCENT_IMAGES to get an image diff --git a/stratus1/doc/developper/stratus/index.html b/stratus1/doc/developper/stratus/index.html new file mode 100644 index 00000000..cf04f88b --- /dev/null +++ b/stratus1/doc/developper/stratus/index.html @@ -0,0 +1,130 @@ + + + + + +Stratus Developper's Manual + + + + + + + + + + + + + + + + +
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      Next
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    Stratus Developper's Manual

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    Sophie Belloeil

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      Next
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    +Sophie BELLOEIL
    20051116.1 +
    + + diff --git a/stratus1/doc/developper/stratus/internals.pl b/stratus1/doc/developper/stratus/internals.pl new file mode 100644 index 00000000..d67a73ff --- /dev/null +++ b/stratus1/doc/developper/stratus/internals.pl @@ -0,0 +1,18 @@ +# LaTeX2HTML 2002-2-1 (1.70) +# Associate internals original text with physical files. + + +$key = q/secmodel/; +$ref_files{$key} = "$dir".q|node1.html|; +$noresave{$key} = "$nosave"; + +$key = q/secnet/; +$ref_files{$key} = "$dir".q|node2.html|; +$noresave{$key} = "$nosave"; + +$key = q/secinst/; +$ref_files{$key} = "$dir".q|node3.html|; +$noresave{$key} = "$nosave"; + +1; + diff --git a/stratus1/doc/developper/stratus/labels.pl b/stratus1/doc/developper/stratus/labels.pl new file mode 100644 index 00000000..1948454f --- /dev/null +++ b/stratus1/doc/developper/stratus/labels.pl @@ -0,0 +1,25 @@ +# LaTeX2HTML 2002-2-1 (1.70) +# Associate labels original text with physical files. + + +$key = q/secmodel/; +$external_labels{$key} = "$URL/" . q|node1.html|; +$noresave{$key} = "$nosave"; + +$key = q/secnet/; +$external_labels{$key} = "$URL/" . q|node2.html|; +$noresave{$key} = "$nosave"; + +$key = q/secinst/; +$external_labels{$key} = "$URL/" . q|node3.html|; +$noresave{$key} = "$nosave"; + +1; + + +# LaTeX2HTML 2002-2-1 (1.70) +# labels from external_latex_labels array. + + +1; + diff --git a/stratus1/doc/developper/stratus/node1.html b/stratus1/doc/developper/stratus/node1.html new file mode 100644 index 00000000..3581a5d6 --- /dev/null +++ b/stratus1/doc/developper/stratus/node1.html @@ -0,0 +1,227 @@ + + + + + +Class Model + + + + + + + + + + + + + + + + + + + +
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    PreviousUpNext
    Stratus Developper's ManualStratus Developper's ManualNets
    +
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    + + +Sous-sections + + + +
    + +

    + +
    +Class Model +

    + +

    +Synopsys +

    + +

    +

    +class myClass ( Model ) :
+    ...
+    
+exemple = myClass ( name, param )
+
    + +

    + +

    +Description +

    + +

    +Every cell made is a class herited from class Model. +
    +Some methods have to be created, like Interface, Netlist ... Some methods are inherited from the class Model. + +

    + +

    +Parameters +

    + +

    + +

      +
    • name : The name of the cell (which is the name of the files which will be created) +
      • +
    • param : A dictionnary which gives all the parameters useful in order to create the cell +
      • +
    + +

    + +

    +Attributes +

    + +

    + +

      +
    • _name : Name of the cell +
      • +
    • _st_insts : List of all the instances of the cell +
      • +
    • _st_ports : List of all the external nets of the cell (except for alimentations and clock) +
      • +
    • _st_sigs : List of all the internal nets of the cell +
      • +
    • _st_vdds, _st_vsss : Two tabs of the nets which are instancied as VddIn and VssIn +
      • +
    • _st_cks : List of all the nets which are instancied as CkIn +
      • +
    • _st_merge : List of all the internal nets which have to be merged +
      • +
    • _param : The map given as argument at the creation of the cell +
      • +
    • _underCells : List of all the instances which are cells that have to be created +
      • +
    • _and, _or, _xor, _not, _buff, _mux, _reg, _shift, _comp, _add, _mult, _div : tells which generator to use when using overloard +
      • +
    • _NB_INST : The number of instances of the cell (useful in order to automatically give a name to the instances) +
      • +
    • _TAB_NETS_OUT and _TAB_NETS_CAT : Lists of all the nets automatically created +
      • +
    • _insref : The reference instance (for placement) +
      • +
    + +

    +And, in connection with Hurricane : + +

      +
    • _hur_cell : The hurricane cell (None by default) +
      • +
    • _db : The database +
      • +
    • _lib0 : self._db.Get_CATA_LIB ( 0 ) +
      • +
    • _nb_alims_verticales, _nb_pins, _nb_vdd_pins, _nb_vss_pins, standard_instances_list, pad_north, pad_south, pad_east, pad_west : all place and route stuffs ... + +

      +

      • +
    + +

    + +

    +Methods +

    + +

    +Methods of class Model are listed below : + +

      +
    • HurricanePlug : Creates the Hurricane cell thanks to the stratus cell. +
      +Before calling this method, only the stratus cell is created, after this method, both cells are created. This method has to be called before View and Save, and before Layout. +
      • +
    • View : Opens/Refreshes the editor in order to see the created layout +
      • +
    • Quit : Finishes a cell without saving +
      • +
    • Save : Saves the created cell +
      +If several cells have been created, they are all going to be saved in separated files +
      • +
    + +

    +Some of those methods have to be defined in order to create a new cell : + +

      +
    • Interface : Description of the external ports of the cell +
      • +
    • Netlist : Description of the netlist of the cell +
      • +
    • Layout : Description of the layout of the cell +
      • +
    • Vbe : Description of the behavior of the cell +
      • +
    • Pattern : Description of the patterns in order to test the cell +
      • +
    + +

    + +

    +

    +

    + + + + + + + + + +
    PreviousUpNext
    Stratus Developper's ManualStratus Developper's ManualNets
    +
    + +
    + +
    +Sophie BELLOEIL
    20051116.1 +
    + + diff --git a/stratus1/doc/developper/stratus/node2.html b/stratus1/doc/developper/stratus/node2.html new file mode 100644 index 00000000..04124489 --- /dev/null +++ b/stratus1/doc/developper/stratus/node2.html @@ -0,0 +1,239 @@ + + + + + +Nets + + + + + + + + + + + + + + + + + + + +
    + + + + + + + + + + +
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    +
    +
    +
    + + +Sous-sections + + + +
    + +

    + +
    +Nets +

    + +

    +Synopsys +

    + +

    +

    +netInput = LogicIn ( name, arity )
+
    + +

    + +

    +Description +

    + +

    +Instanciation of net. Differents kind of nets are listed below : + +

      +
    • LogicIn : Creation of an input port +
      • +
    • LogicOut : Creation of an output port +
      • +
    • LogicInOut : Creation of an inout port +
      • +
    • LogicUnknown : Creation of an input/output port which direction is not defined +
      • +
    • TriState : Creation of a tristate port +
      • +
    • CkIn : Creation of a clock port +
      • +
    • VddIn : Creation of the vdd alimentation +
      • +
    • VssIn : Creation of the vss alimentation +
      • +
    • Signal : Creation of an internal net +
      • +
    + +

    + +

    +Parameters +

    + +

    + +

      +
    • name : Name of the net (mandatory argument) +
      • +
    • arity : Arity of the net (mandatory argument) +
      • +
    • indice : For buses only : the LSB bit (optional argument : set to 0 by default) +
      • +
    + +

    +Only CkIn, VddIn and VssIn do not have the same parameters : there is only the name parameter (they are 1 bit nets). + +

    + +

    +Attributes +

    + +

    + +

      +
    • _name : Name of the net +
      • +
    • _arity : Arity of the net (by default set to 0) +
      • +
    • _ind : LSB of the net +
      • +
    • _ext : Tells if the net is external or not (True/False) +
      • +
    • _direct : If the net is external, tells the direction ("IN", "OUT", "INOUT", "TRISTATE", "UNKNOWN") +
      • +
    • _h_type : If the net is an alimentation or a clock, tells the type ("POWER", "GROUND", "CLOCK") +
      • +
    • _type : The arithmetic type of the net ( "nr" ) +
      • +
    • _st_cell : The stratus cell which the net is instanciated in +
      • +
    • _real_net : If the net is a part of a net (Sig) it is the real net corresponding +
      • +
    • _alias : [] by default. When the net has an alias, it's a tab. Each element of the tab correspond to a bit of the net (from the LSB to the MSB), it'a a dictionnary : the only key is the net which this net is an alias from, the value is the bit of the net +
      • +
    • _to_merge : [] by default. The same as _alias +
      • +
    • _to_cat : [] by default. The same as _alias +
      • +
    + +

    +And, in connection with Hurricane : + +

      +
    • _hur_net : A tab with all the hurricane nets corresponding to the stratus net ; From the LSB to the MSB (for example, with a 1 bit net, one gets the hurricane net by doing : net._hur_net[0] ). +
      • +
    + +

    + +

    +Methods +

    + +

    + +

      +
    • Buffer : Instanciation of a Buffer +
      • +
    • Shift : Instanciation of a shifter +
      • +
    • Mux : Instanciation of a multiplexor +
      • +
    • Reg : Instanciation of a register +
      • +
    • Eq/Ne : Instanciation of comparison generator +
      • +
    • Extend : A net is extended +
      • +
    • Alias : A net is an alias of another net +
      • +
    • Delete : Deletion of the Hurricane nets +
      • +
    +And the overloards : + +
      +
    • __init__ : Initialisation of nets +
      • +
    • __le__ : initialisation of a net thanks to <= notation +
      • +
    • __getitem__, __geslice__ : Creation of "Sig" nets : which are part of nets (use of [] and [:]) +
      • +
    • __and__, __or__, __xor__, __invert__ : boolean operation with &, |, ,  +
      • +
    • __add__, __mul__, __div__ : arithmetic operators with +, * and / +
      • +
    + +

    + +

    +

    +

    + + + + + + + + + +
    PreviousUpNext
    Class ModelStratus Developper's ManualInstances
    +
    + +
    + +
    +Sophie BELLOEIL
    20051116.1 +
    + + diff --git a/stratus1/doc/developper/stratus/node3.html b/stratus1/doc/developper/stratus/node3.html new file mode 100644 index 00000000..2acdd748 --- /dev/null +++ b/stratus1/doc/developper/stratus/node3.html @@ -0,0 +1,193 @@ + + + + + +Instances + + + + + + + + + + + + + + + + + +
    + + + + + + + + + + +
    PreviousUp 
    NetsStratus Developper's Manual 
    +
    +
    +
    + + +Sous-sections + + + +
    + +

    + +
    +Instances +

    + +

    +Synopsys +

    + +

    +

    +Inst ( model
+     , name
+     , param = myParam
+     , map = myMap
+     )
+
    + +

    + +

    +Description +

    + +

    +Instantiation of an instance. The type of the instance is given by the model parameter. The connexions are made thanks to the map parameters. + +

    + +

    +Parameters +

    + +

    + +

      +
    • model : Name of the mastercell of the instance to create (mandatory argument) +
      • +
    • name : Name of the instance (optional) +
      +When this argument is not defined, the instance has a name created by default. This argument is usefull when one wants to create a layout as well. Indeed, the placement of the instances is much easier when the conceptor has chosen himself the name f the instances. +
      • +
    • param : Dictionnary for parameters of the mastercell (optional : only for mastercells which require it) +
      • +
    • map : Dictionnary for connexions in order to make the netlist +
      • +
    + +

    + +

    +Attributes +

    + +

    + +

      +
    • _name : Name of the instance (the name given as parameter if there's one, a name created otherwise) +
      • +
    • _model : Name of the model given as argument +
      • +
    • _real_model : Name of the model created thanks to _model and all the parameters +
      • +
    • _map : Dictionnary map given at the instanciation +
      • +
    • _param : Dictionnary param given at the instanciation +
      • +
    • _st_cell : The stratus cell which the instance is instanciated in +
      • +
    • _st_masterCell : The stratus master cell of the instance +
      • +
    +For placement : + +
      +
    • _plac : tells if the instance is placed or not (UNPLACED by default) +
      • +
    • _x, _y : the coordinates of the instance (only for placed instances) +
      • +
    • _sym : the symetry of the instance (only for placed instances) +
      • +
    +And, in connection with Hurricane : + +
      +
    • _hur_instance : The hurricane instance (None by default) +
      • +
    • _hur_masterCell : The Hurricane master cell of the instance (None by default) +
      • +
    + +

    + +

    +Methods +

    + +

    + +

      +
    • Delete : Deletion of the Hurricane instance +
      • +
    + +

    + +

    +

    +

    + + + + + + + + + +
    PreviousUp 
    NetsStratus Developper's Manual 
    +
    + +
    + +
    +Sophie BELLOEIL
    20051116.1 +
    + + diff --git a/stratus1/doc/developper/stratus/stratus.css b/stratus1/doc/developper/stratus/stratus.css new file mode 100644 index 00000000..83b8aa7d --- /dev/null +++ b/stratus1/doc/developper/stratus/stratus.css @@ -0,0 +1,33 @@ +/* Century Schoolbook font is very similar to Computer Modern Math: cmmi */ +.MATH { font-family: "Century Schoolbook", serif; } +.MATH I { font-family: "Century Schoolbook", serif; font-style: italic } +.BOLDMATH { font-family: "Century Schoolbook", serif; font-weight: bold } + +/* implement both fixed-size and relative sizes */ +SMALL.XTINY { font-size : xx-small } +SMALL.TINY { font-size : x-small } +SMALL.SCRIPTSIZE { font-size : smaller } +SMALL.FOOTNOTESIZE { font-size : small } +SMALL.SMALL { } +BIG.LARGE { } +BIG.XLARGE { font-size : large } +BIG.XXLARGE { font-size : x-large } +BIG.HUGE { font-size : larger } +BIG.XHUGE { font-size : xx-large } + +/* heading styles */ +H1 { } +H2 { } +H3 { } +H4 { } +H5 { } + +/* mathematics styles */ +DIV.displaymath { } /* math displays */ +TD.eqno { } /* equation-number cells */ + + +/* document-specific styles come next */ +DIV.navigation { } +PRE.preform { } +SPAN.arabic { } diff --git a/stratus1/doc/developper/stratus/stratus.html b/stratus1/doc/developper/stratus/stratus.html new file mode 100644 index 00000000..cf04f88b --- /dev/null +++ b/stratus1/doc/developper/stratus/stratus.html @@ -0,0 +1,130 @@ + + + + + +Stratus Developper's Manual + + + + + + + + + + + + + + + + +
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      Next
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    Sophie Belloeil

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    20051116.1 +
    + + diff --git a/stratus1/doc/dpgen/.latex2html-init b/stratus1/doc/dpgen/.latex2html-init new file mode 100644 index 00000000..df1398eb --- /dev/null +++ b/stratus1/doc/dpgen/.latex2html-init @@ -0,0 +1,308 @@ + +# -*- Perl -*- +# +#LaTeX2HTML Version 96.1 : dot.latex2html-init +# +### Command Line Argument Defaults ####################################### + +$MAX_SPLIT_DEPTH = 5; # Stop making separate files at this depth + +$MAX_LINK_DEPTH = 2; # Stop showing child nodes at this depth + +$NOLATEX = 0; # 1 = do not pass unknown environments to Latex + +$EXTERNAL_IMAGES = 0; # 1 = leave the images outside the document + +$ASCII_MODE = 0; # 1 = do not use any icons or internal images + +# 1 = use links to external postscript images rather than inlined bitmap +# images. +$PS_IMAGES = 0; + +#$TITLE = "Titre"; # The default is "No Title" + +$DESTDIR = ''; # Put the result in this directory + +# When this is set, the generated HTML files will be placed in the +# current directory. If set to 0 the default behaviour is to create (or reuse) +# another file directory. +$NO_SUBDIR = 0; + + +# Supply your own string if you don't like the default +$ADDRESS = "$address_data[0]
    \n$address_data[1]    "; + +$NO_NAVIGATION = 0; # 1 = do not put a navigation panel at the top of each page + +# Put navigation links at the top of each page. +# If the page exceeds $WORDS_IN_PAGE number of words then put one at the bottom of the page. +$AUTO_NAVIGATION = 1; + +# Put a link to the index page in the navigation panel +$INDEX_IN_NAVIGATION = 1; + +# Put a link to the table of contents in the navigation panel +$CONTENTS_IN_NAVIGATION = 1; + +# Put a link to the next logical page in the navigation panel +$NEXT_PAGE_IN_NAVIGATION = 1; + +# Put a link to the previous logical page in the navigation panel +$PREVIOUS_PAGE_IN_NAVIGATION = 1; + +$INFO = 0; # 0 = do not make a "About this document..." section + +# Reuse images generated during previous runs +$REUSE = 2; + +# When this is 1, the section numbers are shown. The section numbers should +# then match those that would have bee produced by LaTeX. +# The correct section numbers are obtained from the $FILE.aux file generated +# by LaTeX. +# Hiding the seciton numbers encourages use of particular sections +# as standalone documents. In this case the cross reference to a section +# is shown using the default symbol rather than the section number. +$SHOW_SECTION_NUMBERS = 0; + +### Other global variables ############################################### +$CHILDLINE = "
    \n"; + +# This is the line width measured in pixels and it is used to right justify +# equations and equation arrays; +$LINE_WIDTH = 500; + +# Used in conjunction with AUTO_NAVIGATION +#$WORDS_IN_PAGE = 300; !!! +$WORDS_IN_PAGE = 50; + +# Affects ONLY the way accents are processed +$default_language = 'english'; + +# The value of this variable determines how many words to use in each +# title that is added to the navigation panel (see below) +# +$WORDS_IN_NAVIGATION_PANEL_TITLES = 4; + +# This number will determine the size of the equations, special characters, +# and anything which will be converted into an inlined image +# *except* "image generating environments" such as "figure", "table" +# or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$MATH_SCALE_FACTOR = 1.6; + +# This number will determine the size of +# image generating environments such as "figure", "table" or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$FIGURE_SCALE_FACTOR = 1.6; + + +# If this is set then intermediate files are left for later inspection. +# This includes $$_images.tex and $$_images.log created during image +# conversion. +# Caution: Intermediate files can be *enormous*. +$DEBUG = 0; + +# If both of the following two variables are set then the "Up" button +# of the navigation panel in the first node/page of a converted document +# will point to $EXTERNAL_UP_LINK. $EXTERNAL_UP_TITLE should be set +# to some text which describes this external link. +$EXTERNAL_UP_LINK = ""; +$EXTERNAL_UP_TITLE = ""; + +# If this is set then the resulting HTML will look marginally better if viewed +# with Netscape. +$NETSCAPE_HTML = 0; + +# Valid paper sizes are "letter", "legal", "a4","a3","a2" and "a0" +# Paper sizes has no effect other than in the time it takes to create inlined +# images and in whether large images can be created at all ie +# - larger paper sizes *MAY* help with large image problems +# - smaller paper sizes are quicker to handle +$PAPERSIZE = "a4"; + +# Replace "english" with another language in order to tell LaTeX2HTML that you +# want some generated section titles (eg "Table of Contents" or "References") +# to appear in a different language. Currently only "english" and "french" +# is supported but it is very easy to add your own. See the example in the +# file "latex2html.config" +$TITLES_LANGUAGE = "english"; + +### Navigation Panel ########################################################## +# +# The navigation panel is constructed out of buttons and section titles. +# These can be configured in any combination with arbitrary text and +# HTML tags interspersed between them. +# The buttons available are: +# $PREVIOUS - points to the previous section +# $UP - points up to the "parent" section +# $NEXT - points to the next section +# $NEXT_GROUP - points to the next "group" section +# $PREVIOUS_GROUP - points to the previous "group" section +# $CONTENTS - points to the contents page if there is one +# $INDEX - points to the index page if there is one +# +# If the corresponding section exists the button will contain an +# active link to that section. If the corresponding section does +# not exist the button will be inactive. +# +# Also for each of the $PREVIOUS $UP $NEXT $NEXT_GROUP and $PREVIOUS_GROUP +# buttons there are equivalent $PREVIOUS_TITLE, $UP_TITLE, etc variables +# which contain the titles of their corresponding sections. +# Each title is empty if there is no corresponding section. +# +# The subroutine below constructs the navigation panels in each page. +# Feel free to mix and match buttons, titles, your own text, your logos, +# and arbitrary HTML (the "." is the Perl concatenation operator). + + +@my_icon_tags = (); +$my_icon_tags{'next'} = 'Next Page'; +$my_icon_tags{'next_page'} = 'Next Page'; +$my_icon_tags{'previous'} = 'Previous Page'; +$my_icon_tags{'previous_page'} = 'Previous Page'; +$my_icon_tags{'up'} = 'Up One Level'; +$my_icon_tags{'contents'} = 'Contents'; +$my_icon_tags{'index'} = 'Index'; +$my_icon_tags{'modules'} = 'Module Index'; + +@my_icon_names = (); +$my_icon_names{'previous_page'} = 'prev'; +$my_icon_names{'next_page'} = 'next'; + + +sub get_my_icon($) { + my $icon_file; + my $name = @_[0]; + my $text = $my_icon_tags{$name}; + if ($my_icon_names{$name}) { + $name = $my_icon_names{$name}; + } + if ($text eq '') { + $name = 'blank'; + } + $icon_file = $name . "." . $IMAGE_TYPE; + $used_icons{$icon_file} = 1; + return "\"$text\""; +} + + +sub use_my_icon($) { + my $s = @_[0]; + if ($s =~ /\/) { + my $r = get_my_icon($1); + $s =~ s/\/$r/; + } + return $s; +} + + +sub make_top_nav_panel() { + my $s; + $s = ('' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
    $t_title
    " + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
    " + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
    \n" + . "
    \n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub make_bot_nav_panel() { + my $s; + $s = ('
    ' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
    $t_title
    " + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
    " + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
    \n" + . "
    \n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub top_navigation_panel { + return "\n" + . make_top_nav_panel() + . "
    \n"; +} + + +sub bot_navigation_panel { + return "\n

    \n" + . make_bot_nav_panel() + . "\n"; +} + + +#$EXTERNAL_STYLESHEET = "../ASIM.css"; + +$ADDRESS = "Sophie BELLOEIL
    20051116.1"; + +$LOCAL_ICONS = 0; + +$USING_STYLES = 1; + +$TRANSPARENT_FIGURES = 1; + +$WHITE_BACKGROUND = 0; + +$used_icons{"home." . $IMAGE_TYPE} = 1; + +1; # This must be the last line diff --git a/stratus1/doc/dpgen/ASIM.css b/stratus1/doc/dpgen/ASIM.css new file mode 100644 index 00000000..180cadb3 --- /dev/null +++ b/stratus1/doc/dpgen/ASIM.css @@ -0,0 +1,164 @@ + + html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 { + font-size: 100%; + font-family: verdana, sans-serif; + } + + body { + color: black; + background: white; + background-color: white; + background-position: top left; + background-attachment: fixed; + background-repeat: no-repeat; + margin-top: 2em; + margin-right: 10%; + margin-left: 10%; + } + + hr { + height: 1px; + border: 0; + color: #004400; + background-color: #004400; + } + + + h1, h2, h3, h4, h5, h6 { + font-family: verdana, sans-serif; + } + + h1 { text-align: center; } + h2, h3, h4, h5, h6 { text-align: left; + padding-top: 2em; + } + h1, h2, h3 { font-family: "Trebuchet MS", sans-serif; + color: #09550B; + } + h1 { font-weight: bold; font-size: 170%; } + h2 { font-weight: bold; font-size: 140%; } + h3 { font-weight: bold; font-size: 118%; } + h4 { font-weight: bold; font-size: 100%; } + h5 { font-style: italic; font-size: 100%; } + h6 { font-variant: small-caps; font-size: 100%; } + + .hide { + display: none; + color: white; + } + + + div.navigation { margin-bottom: 1em; } + div.navigation h1 { margin-top: 2em; clear: both; } + div.navigation table { margin-left: 2em; font-size: 90%; } + div.navigation img { color: white; border: none; } + + + p { + margin-top: 0.6em; + margin-bottom: 0.6em; + margin-left: 0.0em; + margin-right: 0.0em; + } + + p.copyright { font-size: 90%; } + p.copyright small { font-size: 80%; } + + p.changed { + padding-left: 0.2em; + border-left: solid; + border-top: none; + border-bottom: none; + border-right: none; + border-left-width: thin; + border-color: red; + } + + + address { + text-align: right; + font-weight: bold; + font-style: italic; + font-size: 80%; + } + + + blockquote { + margin-left: 4em; + margin-right: 4em; + margin-top: 0.8em; + margin-bottom: 0.8em; + font-style: italic; + color: #003300; + } + + blockquote p { + margin-bottom: 0; + } + + blockquote address { + margin: 0; + } + + + table { + border-collapse: collapse; + /* + margin-left: 0em; + margin-right: 0em; + */ + margin-top: 0.8em; + margin-bottom: 0.8em; + } + + dt, dd { margin-top: 0; margin-bottom: 0; } + dt { font-weight: bold; } + + + pre, tt, code { + font-family: "andale mono", monospace; + font-size: 100%; + white-space: pre; + } + + pre { + font-size: 80%; + border: solid; + border-width: thin; + border-color: #003300; + background-color: #EEEEEE; + padding: 0.5em; + margin-left: 2em; + margin-right: 2em + } + + tt { color: green; } + em { font-style: italic; font-weight: bold; } + strong { font-weight: bold; } + + span.textit { font-style: italic; } + span.textbf { font-weight: bold; } + + .small { font-size: 90%; } + .white { color: #FFFFFF; } + + + ul.toc { + list-style: disc; + list-style: none; + } + + + a:link img, a:visited img { border-style: none; } + a img { color: white; } + + a:link, a:active, a:visited { + color: #09550B; + text-decoration: none; + } + + a:hover, a:focus { + color: #FF9900; + text-decoration: underline; + } + diff --git a/stratus1/doc/dpgen/Makefile.am b/stratus1/doc/dpgen/Makefile.am new file mode 100644 index 00000000..2930b867 --- /dev/null +++ b/stratus1/doc/dpgen/Makefile.am @@ -0,0 +1,98 @@ + +doc_en_latex_stratusdir = $(datadir)/doc/en/latex/dpgen +doc_en_html_stratusdir = $(datadir)/doc/en/html/dpgen +doc_en_pdf_stratusdir = $(datadir)/doc/en/pdf/dpgen + + +doc_en_stratus_EXTRA = dpgen.tex \ + man_dpgenadsb2f.tex \ + man_dpgenand2.tex \ + man_dpgenand3.tex \ + man_dpgenand4.tex \ + man_dpgenbuff.tex \ + man_dpgenbuse.tex \ + man_dpgenconst.tex \ + man_dpgendff.tex \ + man_dpgendfft.tex \ + man_dpgenfifo.tex \ + man_dpgeninv.tex \ + man_dpgenmux2.tex \ + man_dpgennand2mask.tex \ + man_dpgennand2.tex \ + man_dpgennand3.tex \ + man_dpgennand4.tex \ + man_dpgennbuse.tex \ + man_dpgennmux2.tex \ + man_dpgennor2mask.tex \ + man_dpgennor2.tex \ + man_dpgennor3.tex \ + man_dpgennor4.tex \ + man_dpgennul.tex \ + man_dpgenor2.tex \ + man_dpgenor3.tex \ + man_dpgenor4.tex \ + man_dpgenram.tex \ + man_dpgenrf1d.tex \ + man_dpgenrf1.tex \ + man_dpgenrom2.tex \ + man_dpgenrom4.tex \ + man_dpgensff.tex \ + man_dpgensfft.tex \ + man_dpgenshift.tex \ + man_dpgenshrot.tex \ + man_dpgenxnor2mask.tex \ + man_dpgenxnor2.tex \ + man_dpgenxor2.tex \ + html.entry \ + ASIM.css \ + .latex2html-init + +install-data-hook: + @if [ `which latex2html 2>/dev/null` ]; then \ + for file in `ls $(srcdir)/*.tex`; do \ + filename=`basename $$file`; \ + if [ ! -L $$filename -a ! -f $$filename ]; then \ + ln -sf $(srcdir)/$$filename . ; \ + fi ; \ + done ; \ + if [ ! -L ASIM.css -a ! -f ASIM.css ]; then \ + ln -sf $(srcdir)/*.css . ; \ + ln -sf $(srcdir)/.latex2html-init . ; \ + fi ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_latex_stratusdir) ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_html_stratusdir) ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_pdf_stratusdir) ; \ + cp -r *.tex $(DESTDIR)$(doc_en_latex_stratusdir) ; \ + cp -r *.css $(DESTDIR)$(doc_en_latex_stratusdir) ; \ + cp -r .latex2html-init $(DESTDIR)$(doc_en_latex_stratusdir) ; \ + rm -f *.aux *.lof *.log *.out *.toc *.dvi ; \ + latex2html -no_math -html_version 4.0,math -style ./ASIM.css dpgen.tex ; \ + cp -pr dpgen/* $(DESTDIR)$(doc_en_html_stratusdir) ; \ + cp -p ASIM.css $(DESTDIR)$(doc_en_html_stratusdir)/ASIM.css ; \ + pdflatex dpgen.tex ; \ + pdflatex dpgen.tex ; \ + cp dpgen.pdf $(DESTDIR)$(doc_en_pdf_stratusdir) ; \ + cp $(srcdir)/html.entry $(DESTDIR)$(doc_en_html_stratusdir); \ + if [ -x $(datadir)/doc/en/html/generateIndex.sh ]; then \ + $(datadir)/doc/en/html/generateIndex.sh \ + --prefix=${prefix} --destdir=$(DESTDIR) ; \ + fi ; \ + else \ + echo "[WARNING] latex2html not found, skipping doc generation."; \ + fi + + +EXTRA_DIST = $(doc_en_stratus_EXTRA) + +CLEANFILES = *.dvi \ + *.ps \ + *.lof \ + *.log \ + *.out \ + *.toc \ + *.aux \ + *.bak \ + stratus/*.html \ + stratus/*.css \ + stratus/*.pl \ + stratus/WARNINGS diff --git a/stratus1/doc/dpgen/dpgen.tex b/stratus1/doc/dpgen/dpgen.tex new file mode 100644 index 00000000..4271928a --- /dev/null +++ b/stratus1/doc/dpgen/dpgen.tex @@ -0,0 +1,142 @@ +\documentclass[12pt]{article} +\usepackage[latin1]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{palatino} +\usepackage{fancyhdr} +\usepackage{float} +\usepackage{subfigure} +\usepackage{wrapfig} +\usepackage[dvips]{graphics} +\usepackage{graphicx} +\usepackage{epsfig} +\usepackage{multicol} +\usepackage{color} +\usepackage{url} +\usepackage{html} + +\setlength{\topmargin}{0cm} +\setlength{\headheight}{1cm} +\setlength{\textheight}{21cm} +\setlength{\textwidth}{16cm} +\setlength{\oddsidemargin}{0cm} +\setlength{\evensidemargin}{0cm} +\setlength{\columnsep}{0.125in} +\setlength{\columnseprule}{0.5pt} +\setlength{\footskip}{1cm} +\sloppy + +\newcommand{\image}[4] +% {\begin{figure}[htbp] + {\begin{figure}[h!] + \includegraphics[width=#2\textwidth]{#1} + \end{figure} + } +% \image{fig.eps}{scale} + +%--------------------------------- page style -------------------------------- +\pagestyle{fancy} +\rhead{} +\lhead{} +\rfoot{\thepage} +\lfoot{} +\cfoot{} +%---------------------------------- document --------------------------------- +\date {} +\title {Dpgen generators User's Manual} +\author {Sophie Belloeil} + +\begin{document} + +\setlength{\footrulewidth}{0.6pt} +\maketitle + +%%\begin{htmlonly} +%% \htmlrule +%% \noindent La version imprimable de ce document est disponible ici~: \\ +%% \begin{center} +%% \hyperref[hyper]{http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf}{}{} +%% {http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf} +%% \end{center} +%%\end{htmlonly} + +\tableofchildlinks +\htmlrule + +\section{DpgenInv} +\input{man_dpgeninv} +\section{DpgenBuff} +\input{man_dpgenbuff} +\section{DpgenNand2} +\input{man_dpgennand2} +\section{DpgenNand3} +\input{man_dpgennand3} +\section{Dpgennand4} +\input{man_dpgennand4} +\section{DpgenAnd2} +\input{man_dpgenand2} +\section{DpgenAnd3} +\input{man_dpgenand3} +\section{DpgenAnd4} +\input{man_dpgenand4} +\section{DpgenNor2} +\input{man_dpgennor2} +\section{DpgenNor3} +\input{man_dpgennor3} +\section{DpgenNor4} +\input{man_dpgennor4} +\section{DpgenOr2} +\input{man_dpgenor2} +\section{DpgenOr3} +\input{man_dpgenor3} +\section{DpgenOr4} +\input{man_dpgenor4} +\section{DpgenXor2} +\input{man_dpgenxor2} +\section{DpgenXnor2} +\input{man_dpgenxnor2} +\section{DpgenNmux2} +\input{man_dpgennmux2} +\section{DpgenMux2} +\input{man_dpgenmux2} +\section{DpgenNbuse} +\input{man_dpgennbuse} +\section{DpgenBuse} +\input{man_dpgenbuse} +\section{DpgenNand2mask} +\input{man_dpgennand2mask} +\section{DpgenNor2mask} +\input{man_dpgennor2mask} +\section{DpgenXnor2mask} +\input{man_dpgenxnor2mask} +\section{DpgenAdsb2f} +\input{man_dpgenadsb2f} +\section{DpgenShift} +\input{man_dpgenshift} +\section{DpgenShrot} +\input{man_dpgenshrot} +\section{DpgenNul} +\input{man_dpgennul} +\section{DpgenConst} +\input{man_dpgenconst} +\section{DpgenRom2} +\input{man_dpgenrom2} +\section{DpgenRom4} +\input{man_dpgenrom4} +\section{DpgenRam} +\input{man_dpgenram} +\section{DpgenRf1} +\input{man_dpgenrf1} +\section{DpgenRf1d} +\input{man_dpgenrf1d} +\section{DpgenFifo} +\input{man_dpgenfifo} +\section{DpgenDff} +\input{man_dpgendff} +\section{DpgenDfft} +\input{man_dpgendfft} +\section{DpgenSff} +\input{man_dpgensff} +\section{DpgenSfft} +\input{man_dpgensfft} + +\end{document} diff --git a/stratus1/doc/dpgen/html.entry b/stratus1/doc/dpgen/html.entry new file mode 100644 index 00000000..3fd44ded --- /dev/null +++ b/stratus1/doc/dpgen/html.entry @@ -0,0 +1 @@ +

  • DpGen
    Data-Path Macro-Blocs Generators

    diff --git a/stratus1/doc/dpgen/man_dpgenadsb2f.tex b/stratus1/doc/dpgen/man_dpgenadsb2f.tex new file mode 100644 index 00000000..01edd455 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenadsb2f.tex @@ -0,0 +1,76 @@ +\begin{itemize} + \item \textbf{Name} : DpgenAdsb2f -- Adder/Substractor Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenAdsb2f', modelname + , param = { 'nbit' : n + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits adder/substractor named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : First operand (input, \verb-n- bits) + \item \textbf{i1} : Second operand (input, \verb-n- bits) + \item \textbf{q} : Output operand (ouput, \verb-n- bits) + \item \textbf{add\_sub} : Select addition or substraction (input, 1 bit) + \item \textbf{c31} : Sarry out. In unsigned mode, this is the overflow (output, 1 bit) + \item \textbf{c30} : Used to compute overflow in signed mode : \verb-overflow = c31 xor c30- (output, 1 bit) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item If the \verb-add_sub- signal is set to \verb-zero-, an addition is performed, otherwise it's a substraction. + \item Operation can be either signed or unsigned. In unsigned mode \verb-c31- is the overflow ; in signed mode you have to compute overflow by \emph{XORing} \verb-c31- and \verb-c30- + \end{itemize} +% \item \textbf{Behavior} : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_ADSB2F ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 8 ) + self.in2 = SignalIn ( "in2", 8 ) + self.out = SignalOut ( "o", 8 ) + self.as = SignalIn ( "as", 1 ) + self.c0 = SignalOut ( "c0", 1 ) + self.c1 = SignalOut ( "c1", 1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenAdsb2f', 'adder_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'adder_8', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'add_sub' : self.as + , 'q' : self.out + , 'c30' : self.c0 + , 'c31' : self.c1 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenand2.tex b/stratus1/doc/dpgen/man_dpgenand2.tex new file mode 100644 index 00000000..061a3ddc --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenand2.tex @@ -0,0 +1,69 @@ +\begin{itemize} + \item \textbf{Name} : DpgenAnd2 -- And2 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenAnd2', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits two inputs AND with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= i0 and i1 +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_and2 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 8 ) + self.in2 = SignalIn ( "in2", 8 ) + self.out = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenAnd2', 'and2_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'and2_8', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'q' : self.out + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenand3.tex b/stratus1/doc/dpgen/man_dpgenand3.tex new file mode 100644 index 00000000..cce8abf4 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenand3.tex @@ -0,0 +1,72 @@ +\begin{itemize} + \item \textbf{Name} : DpgenAnd3 -- And3 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenAnd3', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits three inputs AND with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{i2} : input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional): Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False): In order to generate a layout + \item \textbf{behavioral} (optional, default value : False): In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= i0 and i1 and i2 +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_and3 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 16 ) + self.in2 = SignalIn ( "in2", 16 ) + self.in3 = SignalIn ( "in3", 16 ) + self.out = SignalOut ( "o", 16 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenAnd3', "and3_16" + , param = { 'nbit' : 16 + , 'physical' : True + } + ) + self.I = Inst ( 'and3_16', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'i2' : self.in3 + , 'q' : self.out + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref (0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenand4.tex b/stratus1/doc/dpgen/man_dpgenand4.tex new file mode 100644 index 00000000..2a45dc69 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenand4.tex @@ -0,0 +1,75 @@ +\begin{itemize} + \item \textbf{Name} : DpgenAnd4 -- And4 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenAnd4', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits four inputs AND with an output power of \verb-d- named \verb-modelname-. + \item Terminal Names : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{i2} : input (\verb-n- bits) + \item \textbf{i3} : input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= i0 and i1 and i2 and i3 +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_and4 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 2 ) + self.in2 = SignalIn ( "in2", 2 ) + self.in3 = SignalIn ( "in3", 2 ) + self.in4 = SignalIn ( "in4", 2 ) + self.out = SignalOut ( "o", 2 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenAnd4', 'and4_2' + , param = { 'nbit' : 2 + , 'physical' : True + } + ) + self.I = Inst ( 'and4_2', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'i2' : self.in3 + , 'i3' : self.in4 + , 'q' : self.out + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenbuff.tex b/stratus1/doc/dpgen/man_dpgenbuff.tex new file mode 100644 index 00000000..9d5314e4 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenbuff.tex @@ -0,0 +1,66 @@ +\begin{itemize} + \item \textbf{Name} : DpgenBuff -- Buffer Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenBuff', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits inverter with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2, 4 or 8 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= i0 +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_buff ( Model ) : + + def Interface ( self ) : + self.i = SignalIn ( "i", 32 ) + self.o = SignalOut ( "o", 32 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenBuff', 'buff_32' + , param = { 'nbit' : 32 + , 'physical' : True + } + ) + self.I = Inst ( 'buff_32', 'inst' + , map = { 'i0' : self.i + , 'q' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenbuse.tex b/stratus1/doc/dpgen/man_dpgenbuse.tex new file mode 100644 index 00000000..5473691e --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenbuse.tex @@ -0,0 +1,65 @@ +\begin{itemize} + \item \textbf{Name} : DpgenBuse -- Tristate Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenBuse', modelname + , param = { 'nbit' : n + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits tristate named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{cmd} : select ( 1 bit ) + \item \textbf{i0} : input ( \verb-n- bits ) + \item \textbf{q} : output ( \verb-n- bits ) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nts:BLOCK(cmd = '1') BEGIN + q <= GUARDED i0; +END +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_buse ( Model ) : + + def Interface ( self ) : + self.i = SignalIn ( "i", 8 ) + self.cmd = SignalIn ( "cmd", 1 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenBuse', 'buse_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'buse_8', 'inst' + , map = { 'i0' : self.i + , 'cmd' : self.cmd + , 'q' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenconst.tex b/stratus1/doc/dpgen/man_dpgenconst.tex new file mode 100644 index 00000000..458497b0 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenconst.tex @@ -0,0 +1,60 @@ +\begin{itemize} + \item \textbf{Name} : DpgenConst -- Constant Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenConst', modelname + , param = { 'nbit' : n + , 'const' : constVal + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits constant named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{q} : the constant (output, \verb-n- bit) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit } (mandatory) : Defines the size of the generator + \item \textbf{const} (mandatory) : Defines the constant (string beginning with 0b, 0x or 0o functions of the basis) + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +q <= constVal +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_const ( Model ) : + + def Interface ( self ) : + self.o = SignalOut ( "o", 32 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenConst', 'const_0x0000ffff' + , param = { 'nbit' : 32 + , 'const' : "0x0000FFFF" + , 'physical' : True + } + ) + self.I = Inst ( 'const_0x0000ffff', 'inst' + , map = { 'q' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgendff.tex b/stratus1/doc/dpgen/man_dpgendff.tex new file mode 100644 index 00000000..b6671e0b --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgendff.tex @@ -0,0 +1,69 @@ +\begin{itemize} + \item \textbf{Name} : DpgenDff -- Dynamic Flip-Flop Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenDff', modelname + , param = { 'nbit' : n + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a n bits dynamic flip-flop named \verb-modelname-. The two latches of this flip-flop are dynamic, i.e. the data is stored in a capacitor. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{wen} : write enable (1 bit) + \item \textbf{ck} : clock signal (1 bit) + \item \textbf{i0} : data input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item When wen is set to \verb-one-, enables the writing of the flip-flop + \end{itemize} +% \item \textbf{Behavior} : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_dff ( Model ) : + + def Interface ( self ) : + self.ck = SignalIn ( "ck", 1 ) + self.wen = SignalIn ( "wen", 1 ) + self.i = SignalIn ( "i", 4 ) + self.o = SignalOut ( "o", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenDff', 'dff_4' + , param = { 'nbit' : 4 + , 'physical' : True + } + ) + self.I = Inst ( 'dff_4', 'inst' + , map = { "wen" : self.wen + , "ck" : self.ck + , "i0" : self.i + , "q" : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgendfft.tex b/stratus1/doc/dpgen/man_dpgendfft.tex new file mode 100644 index 00000000..0ecb7001 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgendfft.tex @@ -0,0 +1,77 @@ +\begin{itemize} + \item \textbf{Name} : DpgenDfft -- Dynamic Flip-Flop with Scan-Path Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenDfft', modelname + , param = { 'nbit' : n + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a n bits dynamic flip-flop with scan-path named \verb-modelname-. The two latches of this flip-flop are dynamic, i.e. the data is stored in a capacitor. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{scan} : scan-path mode (input, 1 bit) + \item \textbf{scin} : scan path in (input, 1 bit) + \item \textbf{wen} : write enable (1 bit) + \item \textbf{ck} : clock signal (1 bit) + \item \textbf{i0} : data input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item When scan is set to \verb-one-, it enables the scan-path mode. Note that in scan-path mode, the wen signal is not effective + \item scin is the input of the scan-path. This terminal is different from \verb-i0[0]-. The scout is q[N-1] (in the following example this is \verb-q[31]-) + \item When wen is set to \verb-one- enables the writing of the flip-flop + \end{itemize} +% \item \textbf{Behavior} : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_dfft ( Model ) : + + def Interface ( self ) : + self.scan = SignalIn ( "scin", 1 ) + self.scin = SignalIn ( "scan", 1 ) + self.ck = SignalIn ( "ck", 1 ) + self.wen = SignalIn ( "wen", 1 ) + self.i = SignalIn ( "i", 4 ) + self.o = SignalOut ( "o", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenDfft', 'dfft_4' + , param = { 'nbit' : 4 + , 'physical' : True + } + ) + self.I = Inst ( 'dfft_4', 'inst' + , map = { "wen" : self.wen + , "ck" : self.ck + , "scan" : self.scan + , "scin" : self.scin + , "i0" : self.i + , "q" : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenfifo.tex b/stratus1/doc/dpgen/man_dpgenfifo.tex new file mode 100644 index 00000000..9d5b8ff2 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenfifo.tex @@ -0,0 +1,91 @@ +\begin{itemize} + \item \textbf{Name} : DpgenFifo -- Fifo Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenFifo', modelname + , param = { 'nbit' : n + , 'nword' : regNumber + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a FIFO of \verb-regNumber- words of \verb-n- bits named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{ck} : clock signal (input, 1 bit) + \item \textbf{reset} : reset signal (input, 1 bit) + \item \textbf{r} : read requested (input, 1 bit) + \item \textbf{w} : write requested (input, 1 bit) + \item \textbf{rok} : read acknowledge (output, 1 bit) + \item \textbf{wok} : write acknowledge (output, 1 bit) + \item \textbf{sel} : select the write bus (input, 1 bit) + \item \textbf{datain0} : first write bus (input, \verb-n- bits) + \item \textbf{datain1} : second write bus (input, \verb-n- bits) + \item \textbf{dataout} : read bus (output, \verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the words (even, between 2 and 64) + \item \textbf{nword} (mandatory) : Defines the number of words (even, between 4 and 32) + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item datain0 and datain1 : the two write busses. Only one is used to actually write the FIFO, it is selected by the sel signal. + \item sel : when set to \verb-zero- the datain0 is used to write the register word, otherwise it will be datain1. + \item r, rok : set r when a word is requested, rok tells that a word has effectively been popped (rok == not empty). + \item w, wok : set w when a word is pushed, wok tells that the word has effectively been pushed (wok == not full). + \end{itemize} +% \item \textbf{Behavior} : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_fifo ( Model ) : + + def Interface ( self ) : + self.ck = SignalIn ( "ck", 1 ) + self.reset = SignalIn ( "reset", 1 ) + self.r = SignalIn ( "r", 1 ) + self.w = SignalIn ( "w", 1 ) + self.rok = SignalInOut ( "rok", 1 ) + self.wok = SignalInOut ( "wok", 1 ) + self.sel = SignalIn ( "sel", 1 ) + self.datain0 = SignalIn ( "datain0", 4 ) + self.datain1 = SignalIn ( "datain1", 4 ) + self.dataout = SignalOut ( "dataout", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenFifo', 'fifo_4_16' + , param = { 'nbit' : 4 + , 'nword' : 16 + , 'physical' : True + } + ) + self.I = Inst ( 'fifo_4_16', 'inst' + , map = { 'ck' : self.ck + , 'reset' : self.reset + , 'r' : self.r + , 'w' : self.w + , 'rok' : self.rok + , 'wok' : self.wok + , 'sel' : self.sel + , 'datain0' : self.datain0 + , 'datain1' : self.datain1 + , 'dataout' : self.dataout + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgeninv.tex b/stratus1/doc/dpgen/man_dpgeninv.tex new file mode 100644 index 00000000..b95e3f57 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgeninv.tex @@ -0,0 +1,66 @@ +\begin{itemize} + \item \textbf{Name} : DpgenInv -- Inverter Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenInv', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits inverter with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{nq} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 1, 2, 4 or 8 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= not ( i0 ) +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_inv ( Model ) : + + def Interface ( self ) : + self.i = SignalIn ( "i", 54 ) + self.o = SignalOut ( "o", 54 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenInv', 'inv_54' + , param = { 'nbit' : 54 + , 'physical' : True + } + ) + self.I = Inst ( 'inv_54', 'inst' + , map = { 'i0' : self.i + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenmux2.tex b/stratus1/doc/dpgen/man_dpgenmux2.tex new file mode 100644 index 00000000..c9c94920 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenmux2.tex @@ -0,0 +1,74 @@ +\begin{itemize} + \item \textbf{Name} : DpgenMux2 -- Multiplexer Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenMux2', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits two inputs multiplexer with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{cmd} : select ( 1 bit ) + \item \textbf{i0} : input ( \verb-n- bits ) + \item \textbf{i1} : input ( \verb-n- bits ) + \item \textbf{q} : output ( \verb-n- bits ) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{nbit\_cmd} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= WITH cmd SELECT i0 WHEN '0', + i1 WHEN '1'; +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_mux2 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 8 ) + self.in2 = SignalIn ( "in2", 8 ) + self.cmd = SignalIn ( "cmd", 1 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenMux2', 'mux2_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'mux2_8', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'cmd' : self.cmd + , 'q' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennand2.tex b/stratus1/doc/dpgen/man_dpgennand2.tex new file mode 100644 index 00000000..e34dc41f --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennand2.tex @@ -0,0 +1,69 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNand2 -- Nand2 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNand2', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits two inputs NAND with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{nq} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 1 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= not ( i0 and i1 ) +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nand2 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 8 ) + self.in2 = SignalIn ( "in2", 8 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNand2', 'nand2_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'nand2_8', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennand2mask.tex b/stratus1/doc/dpgen/man_dpgennand2mask.tex new file mode 100644 index 00000000..0b9c616f --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennand2mask.tex @@ -0,0 +1,74 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNand2mask -- Programmable Mask Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNand2mask', modelname + , param = { 'nbit' : n + , 'const' : constVal + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits conditionnal NAND mask named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{cmd} : mask control ( 1 bit ) + \item \textbf{i0} : input ( \verb-n- bits ) + \item \textbf{nq} : output ( \verb-n- bits ) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{const} (mandatory) : Defines the constant (string beginning with 0b, 0x or 0o functions of the basis) + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item If the \verb-cmd- signal is set to \verb-zero-, the mask is NOT applied, so the whole operator behaves like an inverter. + \item If the \verb-cmd- signal is set to \verb-one-, the mask is applied, the output is the \emph{complemented} result of the input value \emph{ANDed} with the mask (suplied by \verb-constVal-). + \item The constant \verb-constVal- is given to the macro-generator call, therefore the value cannot be changed afterward : it's hard wired in the operator. + \item A common error is to give a real constant for the \verb-constVal- argument. Be aware that it is a character string. + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= WITH cmd SELECT not(i0) WHEN '0', + not(i0 and constVal) WHEN '1'; +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nand2mask ( Model ) : + + def Interface ( self ) : + self.i = SignalIn ( "i", 32 ) + self.cmd = SignalIn ( "cmd", 1 ) + self.o = SignalOut ( "o", 32 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNand2mask', 'nand2mask_0x0000ffff' + , param = { 'nbit' : 32 + , 'const' : "0x0000FFFF" + , 'physical' : True + } + ) + self.I = Inst ( 'nand2mask_0x0000ffff', 'inst' + , map = { 'i0' : self.i + , 'cmd' : self.cmd + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennand3.tex b/stratus1/doc/dpgen/man_dpgennand3.tex new file mode 100644 index 00000000..1dfef887 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennand3.tex @@ -0,0 +1,72 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNand3 -- Nand3 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNand3', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits three inputs NAND with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{i2} : input (\verb-n- bits) + \item \textbf{nq} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 1 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= not ( i0 and i1 and i2 ) +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nand3 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 20 ) + self.in2 = SignalIn ( "in2", 20 ) + self.in3 = SignalIn ( "in3", 20 ) + self.o = SignalOut ( "o", 20 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNand3', 'nand3_20' + , param = { 'nbit' : 20 + , 'physical' : True + } + ) + self.I = Inst ( 'nand3_20', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'i2' : self.in3 + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennand4.tex b/stratus1/doc/dpgen/man_dpgennand4.tex new file mode 100644 index 00000000..a1057b73 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennand4.tex @@ -0,0 +1,75 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNand4 -- Nand4 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNand4', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits four inputs NAND with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{i2} : input (\verb-n- bits) + \item \textbf{i3} : input (\verb-n- bits) + \item \textbf{nq} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 1 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= not ( i0 and i1 and i2 and i3 ) +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nand4 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 9 ) + self.in2 = SignalIn ( "in2", 9 ) + self.in3 = SignalIn ( "in3", 9 ) + self.in4 = SignalIn ( "in4", 9 ) + self.o = SignalOut ( "o", 9 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNand4', 'nand4_9' + , param = { 'nbit' : 9 + , 'physical' : True + } + ) + self.I = Inst ( 'nand4_9', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'i2' : self.in3 + , 'i3' : self.in4 + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennbuse.tex b/stratus1/doc/dpgen/man_dpgennbuse.tex new file mode 100644 index 00000000..e5da167d --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennbuse.tex @@ -0,0 +1,65 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNbuse -- Tristate Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNbuse', modelname + , param = { 'nbit' : n + , 'physical' : true + , 'behavioral' : true + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits tristate with an complemented output named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{cmd} : select ( 1 bit ) + \item \textbf{i0} : input ( \verb-n- bits ) + \item \textbf{nq} : output ( \verb-n- bits ) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nts:BLOCK(cmd = '1') BEGIN + nq <= GUARDED not(i0); +END +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nbuse ( Model ) : + + def Interface ( self ) : + self.i = SignalIn ( "i", 29 ) + self.cmd = SignalIn ( "cmd", 1 ) + self.o = SignalOut ( "o", 29 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNbuse', 'nbuse29' + , param = { 'nbit' : 29 + , 'physical' : True + } + ) + self.I = Inst ( 'nbuse29', 'inst' + , map = { 'i0' : self.i + , 'cmd' : self.cmd + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennmux2.tex b/stratus1/doc/dpgen/man_dpgennmux2.tex new file mode 100644 index 00000000..e7300a0d --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennmux2.tex @@ -0,0 +1,67 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNmux2 -- Multiplexer Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNmux2', modelname + , param = { 'nbit' : n + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits two inputs multiplexer named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{cmd} : select ( 1 bit ) + \item \textbf{i0} : input ( \verb-n- bits ) + \item \textbf{i1} : input ( \verb-n- bits ) + \item \textbf{nq} : output ( \verb-n- bits ) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= WITH cmd SELECT not i0 WHEN '0', + not i1 WHEN '1'; +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nmux2 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 5 ) + self.in2 = SignalIn ( "in2", 5 ) + self.cmd = SignalIn ( "cmd", 1 ) + self.o = SignalOut ( "o", 5 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNmux2', 'nmux2_5' + , param = { 'nbit' : 5 + , 'physical' : True + } + ) + self.I = Inst ( 'nmux2_5', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'cmd' : self.cmd + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennor2.tex b/stratus1/doc/dpgen/man_dpgennor2.tex new file mode 100644 index 00000000..7c79468d --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennor2.tex @@ -0,0 +1,69 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNor2 -- Nor2 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNor2', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits two inputs NOR with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{nq} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 1 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= not ( i0 or i1 ) +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nor2 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 8 ) + self.in2 = SignalIn ( "in2", 8 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNor2', 'nor2_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'nor2_8', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennor2mask.tex b/stratus1/doc/dpgen/man_dpgennor2mask.tex new file mode 100644 index 00000000..4327f164 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennor2mask.tex @@ -0,0 +1,74 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNor2mask -- Programmable Mask Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNor2mask', modelname + , param = { 'nbit' : n + , 'const' : constVal + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits conditionnal NOR mask named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{cmd} : mask control ( 1 bit ) + \item \textbf{i0} : input ( \verb-n- bits ) + \item \textbf{nq} : output ( \verb-n- bits ) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{const} (mandatory) : Defines the constant (string beginning with 0b, 0x or 0o functions of the basis) + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item If the \verb-cmd- signal is set to \verb-zero-, the mask is NOT applied, so the whole operator behaves like an inverter. + \item If the \verb-cmd- signal is set to \verb-one-, the mask is applied, the output is the \emph{complemented} result of the input value \emph{ORed} with the mask (suplied by \verb-constVal-). + \item The constant \verb-constVal- is given to the macro-generator call, therefore the value cannot be changed afterward : it's hard wired in the operator. + \item A common error is to give a real constant for the \verb-constVal- argument. Be aware that it is a character string. + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= WITH cmd SELECT not(i0) WHEN '0', + not(i0 or constVal) WHEN '1'; +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nor2mask ( Model ) : + + def Interface ( self ) : + self.i = SignalIn ( "i", 8 ) + self.cmd = SignalIn ( "cmd", 1 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNor2mask', 'nor2mask_000111' + , param = { 'nbit' : 8 + , 'const' : "0b000111" + , 'physical' : True + } + ) + self.I = Inst ( 'nor2mask_000111', 'inst' + , map = { 'i0' : self.i + , 'cmd' : self.cmd + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennor3.tex b/stratus1/doc/dpgen/man_dpgennor3.tex new file mode 100644 index 00000000..33cdcd41 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennor3.tex @@ -0,0 +1,72 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNor3 -- Nor3 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNor3', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits three inputs NOR with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{i2} : input (\verb-n- bits) + \item \textbf{nq} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 1 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= not ( i0 or i1 or i2 ) +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nor3 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 3 ) + self.in2 = SignalIn ( "in2", 3 ) + self.in3 = SignalIn ( "in3", 3 ) + self.o = SignalOut ( "out", 3 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNor3', 'nor3_3' + , param = { 'nbit' : 3 + , 'physical' : True + } + ) + self.I = Inst ( 'nor3_3', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'i2' : self.in3 + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennor4.tex b/stratus1/doc/dpgen/man_dpgennor4.tex new file mode 100644 index 00000000..cb45bc99 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennor4.tex @@ -0,0 +1,76 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNor4 -- Nor4 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNor4', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits four inputs NOR with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{i2} : input (\verb-n- bits) + \item \textbf{i3} : input (\verb-n- bits) + \item \textbf{nq} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 1 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= not ( i0 or i1 or i2 or i3 ) +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nor4 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 15 ) + self.in2 = SignalIn ( "in2", 15 ) + self.in3 = SignalIn ( "in3", 15 ) + self.in4 = SignalIn ( "in4", 15 ) + self.out = SignalOut ( "o", 15 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNor4', 'nor4_15' + , param = { 'nbit' : 15 + , 'physical' : True + } + ) + self.I = Inst ( 'nor4_15', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'i2' : self.in3 + , 'i3' : self.in4 + , 'nq' : self.out + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgennul.tex b/stratus1/doc/dpgen/man_dpgennul.tex new file mode 100644 index 00000000..4a60747b --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgennul.tex @@ -0,0 +1,58 @@ +\begin{itemize} + \item \textbf{Name} : DpgenNul -- Zero Detector Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenNul', modelname + , param = { 'nbit' : n + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits zero detector named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : value to check (input, \verb-n- bits) + \item \textbf{q} : null flag (1 bit) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +q <= '1' WHEN ( i0 = X"00000000" ) ELSE '0'; +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_nul ( Model ) : + + def Interface ( self ) : + self.i = SignalIn ( "i", 4 ) + self.o = SignalOut ( "o", 1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenNul', 'nul_4' + , param = { 'nbit' : 4 + , 'physical' : True + } + ) + self.I = Inst ( 'nul_4', 'inst' + , map = { 'i0' : self.i + , 'nul' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenor2.tex b/stratus1/doc/dpgen/man_dpgenor2.tex new file mode 100644 index 00000000..690082f7 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenor2.tex @@ -0,0 +1,70 @@ +\begin{itemize} + \item \textbf{Name} : DpgenOr2 -- Or2 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenOr2', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits two inputs OR with an output power of \verb-drive- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the a map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2 or 4 + \item If this parameter is not defined, the \verb-drive- is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= i0 or i1 +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_or2 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 8 ) + self.in2 = SignalIn ( "in2", 8 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenOr2', 'or2_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'or2_8', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'q' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenor3.tex b/stratus1/doc/dpgen/man_dpgenor3.tex new file mode 100644 index 00000000..f557ac75 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenor3.tex @@ -0,0 +1,72 @@ +\begin{itemize} + \item \textbf{Name} : DpgenOr3 -- Or3 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenOr3', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits three inputs OR with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{i2} : input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= i0 or i1 or i2 +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_or3 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 5 ) + self.in2 = SignalIn ( "in2", 5 ) + self.in3 = SignalIn ( "in3", 5 ) + self.o = SignalOut ( "o", 5 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenOr3', 'or3_5' + , param = { 'nbit' : 5 + , 'physical' : True + } + ) + self.I = Inst ( 'or3_5', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'i2' : self.in3 + , 'q' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenor4.tex b/stratus1/doc/dpgen/man_dpgenor4.tex new file mode 100644 index 00000000..0b31576a --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenor4.tex @@ -0,0 +1,75 @@ +\begin{itemize} + \item \textbf{Name} : DpgenOr4 -- Or4 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenOr4', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits four inputs OR with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{i2} : input (\verb-n- bits) + \item \textbf{i3} : input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= i0 or i1 or i2 or i3 +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_or4 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 16 ) + self.in2 = SignalIn ( "in2", 16 ) + self.in3 = SignalIn ( "in3", 16 ) + self.in4 = SignalIn ( "in4", 16 ) + self.out = SignalOut ( "o", 16 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenOr4', 'or4_16' + , param = { 'nbit' : 16 + , 'physical' : True + } + ) + self.I = Inst ( 'or4_16', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'i2' : self.in3 + , 'i3' : self.in4 + , 'q' : self.out + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenram.tex b/stratus1/doc/dpgen/man_dpgenram.tex new file mode 100644 index 00000000..bdb25865 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenram.tex @@ -0,0 +1,72 @@ +\begin{itemize} + \item \textbf{Name} : DpgenRam -- RAM Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenRam', modelname + , param = { 'nbit' : n + , 'nword' : regNumber + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a RAM of \verb-regNumber- words of \verb-n- bits named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{ck} : clock signal (input, 1 bit) + \item \textbf{w} : write requested (input, 1 bit) + \item \textbf{selram} : select the write bus (input, 1 bit) + \item \textbf{ad} : the address (input, \verb-Y- bits) + \item \textbf{datain} : write bus (input, \verb-n- bits) + \item \textbf{dataout} : read bus (output, \verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{nword} (mandatory) : Defines the size of the words + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_ram ( Model ) : + + def Interface ( self ) : + self.ck = SignalIn ( "ck", 1 ) + self.w = SignalIn ( "w", 1 ) + self.selram = SignalIn ( "selram", 1 ) + self.ad = SignalIn ( "ad", 5 ) + self.datain = SignalIn ( "datain", 32 ) + self.dataout = TriState ( "dataout", 32 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenRam', 'ram_32_32' + , param = { 'nbit' : 32 + , 'nword' : 32 + , 'physical' : True + } + ) + self.I = Inst ( 'ram_32_32', 'inst' + , map = { 'ck' : self.ck + , 'w' : self.w + , 'selram' : self.selram + , 'ad' : self.ad + , 'datain' : self.datain + , 'dataout' : self.dataout + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenrf1.tex b/stratus1/doc/dpgen/man_dpgenrf1.tex new file mode 100644 index 00000000..a96f8f91 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenrf1.tex @@ -0,0 +1,82 @@ +\begin{itemize} + \item \textbf{Name} : DpgenRf1, DpgenRf1r0 -- Register File Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenRf1', modelname + , param = { 'nbit' : n + , 'nword' : regNumber + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a register file of \verb-regNumber- words of \verb-n- bits without decoder named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{ckok} : clock signal (input, 1 bit) + \item \textbf{sel} : select the write bus (input, 1 bit) + \item \textbf{selr} : the decoded read address (input, \verb-regNumber- bits) + \item \textbf{selw} : the decoded write address (input, \verb-regNumber- bits) + \item \textbf{datain0} : first write bus (input, \verb-n- bits) + \item \textbf{datain1} : second write bus (input, \verb-n- bits) + \item \textbf{dataout} : read bus (output, \verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the words (even, between 2 and 64) + \item \textbf{nword} (mandatory) : Defines the number of the words (even, between 4 and 32) + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item datain0 and datain1 are the two write busses. Only one is used to actually write the register word, it is selected by the sel signal. + \item When sel is set to zero datain0 is used to write the register word, otherwise it will be datain1 + \item selr, selw : this register file have no decoder, so selr have a bus width equal to \verb-regNumber-. One bit for each word + \item The DpgenRf1r0 variant differs from the DpgenRf1 in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_rf1 ( Model ) : + + def Interface ( self ) : + self.ck = SignalIn ( "ck", 1 ) + self.sel = SignalIn ( "sel", 1 ) + self.selr = SignalIn ( "selr", 16 ) + self.selw = SignalIn ( "selw", 16 ) + self.datain0 = SignalIn ( "datain0", 4 ) + self.datain1 = SignalIn ( "datain1", 4 ) + self.dataout = SignalOut ( "dataout", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenRf1', 'rf1_4_16' + , param = { 'nbit' : 4 + , 'nword' : 16 + , 'physical' : True + } + ) + self.I = Inst ( 'rf1_4_16', 'inst' + , map = { 'ck' : self.ck + , 'sel' : self.sel + , 'selr' : self.selr + , 'selw' : self.selw + , 'datain0' : self.datain0 + , 'datain1' : self.datain1 + , 'dataout' : self.dataout + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenrf1d.tex b/stratus1/doc/dpgen/man_dpgenrf1d.tex new file mode 100644 index 00000000..67a207d7 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenrf1d.tex @@ -0,0 +1,89 @@ +\begin{itemize} + \item \textbf{Name} : DpgenRf1d, DpgenRf1dr0 -- Register File with Decoder Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenRf1d', modelname + , param = { 'nbit' : n + , 'nword' : regNumber + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a register file of \verb-regNumber- words of \verb-n- bits with decoder named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{ck} : clock signal (input, 1 bit) + \item \textbf{sel} : select the write bus (input, 1 bit) + \item \textbf{wen} : write enable (input, 1 bit) + \item \textbf{ren} : read enable (input, 1 bit) + \item \textbf{adr} : the read address (input, \verb-Y- bits) + \item \textbf{adw} : the write address (input, \verb-Y- bits) + \item \textbf{datain0} : first write bus (input, \verb-n- bits) + \item \textbf{datain1} : second write bus (input, \verb-n- bits) + \item \textbf{dataout} : read bus (output, \verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the words (even, between 2 and 64) + \item \textbf{nword} (mandatory) : Defines the number of the words (even, between 6 and 32) + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item datain0 and datain1 are the two write busses. Only one is used to actually write the register word, it is selected by the sel signal. + \item When sel is set to zero datain0 is used to write the register word, otherwise it will be datain1 + \item adr, adw : the width (Y) of those signals is computed from regNumber : \verb-Y = log2(regNumber)- + \item wen and ren : write enable and read enable, allows reading and writing when sets to \verb-one- + \item The DpgenRf1dr0 variant differs from the DpgenRf1d in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero + \end{itemize} +% \item \textbf{Behavior} : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_rf1d ( Model ) : + + def Interface ( self ) : + self.ck = SignalIn ( "ck", 1 ) + self.sel = SignalIn ( "sel", 1 ) + self.wen = SignalIn ( "wen", 1 ) + self.ren = SignalIn ( "ren", 1 ) + self.adr = SignalIn ( "adr", 4 ) + self.adw = SignalIn ( "adw", 4 ) + self.datain0 = SignalIn ( "datain0", 4 ) + self.datain1 = SignalIn ( "datain1", 4 ) + self.dataout = SignalOut ( "dataout", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenRf1d', 'rf1d_4_16' + , param = { 'nbit' : 4 + , 'nword' : 16 + , 'physical' : True + } + ) + self.I = Inst ( 'rf1d_4_16', 'inst' + , map = { 'ck' : self.ck + , 'sel' : self.sel + , 'wen' : self.wen + , 'ren' : self.ren + , 'adr' : self.adr + , 'adw' : self.adw + , 'datain0' : self.datain0 + , 'datain1' : self.datain1 + , 'dataout' : self.dataout + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenrom2.tex b/stratus1/doc/dpgen/man_dpgenrom2.tex new file mode 100644 index 00000000..b6bb432b --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenrom2.tex @@ -0,0 +1,66 @@ +\begin{itemize} + \item \textbf{Name} : DpgenRom2 -- 2 words ROM Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenRom2', modelname + , param = { 'nbit' : n + , 'val0' : constVal0 + , 'val1' : constVal1 + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits 2 words optimized ROM named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{sel0} : address of the value (input, 1 bit) + \item \textbf{q} : the selected word (output, \verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{val0} (mandatory) : Defines the first word + \item \textbf{val1} (mandatory) : Defines the second word + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +q <= WITH sel0 SELECT + constVal0 WHEN B"0", + constVal1 WHEN B"1"; +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_rom2 ( Model ) : + + def Interface ( self ) : + self.sel0 = SignalIn ( "sel0", 1 ) + self.q = SignalOut ( "dataout", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenRom2', 'rom2_0b1010_0b1100' + , param = { 'nbit' : 4 + , 'val0' : "0b1010" + , 'val1' : "0b1100" + , 'physical' : True + } + ) + self.I = Inst ( 'rom2_0b1010_0b1100', 'inst' + , map = { 'sel0' : self.sel0 + , 'q' : self.q + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenrom4.tex b/stratus1/doc/dpgen/man_dpgenrom4.tex new file mode 100644 index 00000000..2347ad11 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenrom4.tex @@ -0,0 +1,76 @@ +\begin{itemize} + \item \textbf{Name} : DpgenRom4 -- 4 words ROM Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenRom4', modelname + , param = { 'nbit' : n + , 'val0' : constVal0 + , 'val1' : constVal1 + , 'val2' : constVal2 + , 'val3' : constVal3 + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits 4 words optimized ROM named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{sel1} : upper bit of the address of the value (input, 1 bit) + \item \textbf{sel0} : lower bit of the address of the value (input, 1 bit) + \item \textbf{q} : the selected word (output, \verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{val0} (mandatory) : Defines the first word + \item \textbf{val1} (mandatory) : Defines the second word + \item \textbf{val2} (mandatory) : Defines the third word + \item \textbf{val3} (mandatory) : Defines the fourth word + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +q <= WITH sel1 & sel0 SELECT constVal0 WHEN B"00", + constVal1 WHEN B"01", + constVal2 WHEN B"10", + constVal3 WHEN B"11"; +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_rom4 ( Model ) : + + def Interface ( self ) : + self.sel0 = SignalIn ( "sel0", 1 ) + self.sel1 = SignalIn ( "sel1", 1 ) + self.q = SignalOut ( "dataout", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenRom4', 'rom4_0b1010_0b1100_0b1111_0b0001' + , param = { 'nbit' : 4 + , 'val0' : "0b1010" + , 'val1' : "0b1100" + , 'val2' : "0b1111" + , 'val3' : "0b0001" + , 'physical' : True + } + ) + self.I = Inst ( 'rom4_0b1010_0b1100_0b1111_0b0001', 'inst' + , map = { 'sel0' : self.sel0 + , 'sel1' : self.sel1 + , 'q' : self.q + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgensff.tex b/stratus1/doc/dpgen/man_dpgensff.tex new file mode 100644 index 00000000..5f311107 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgensff.tex @@ -0,0 +1,69 @@ +\begin{itemize} + \item \textbf{Name} : DpgenSff -- Static Flip-Flop Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenSff', modelname + , param = { 'nbit' : n + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a n bits static flip-flop named \verb-modelname-. The two latches of this flip-flop are static, i.e. each one is made of two interters looped together. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{wen} : write enable (1 bit) + \item \textbf{ck} : clock signal (1 bit) + \item \textbf{i0} : data input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item When wen is set to \verb-one-, enables the writing of the flip-flop + \end{itemize} +% \item \textbf{Behavior} : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_sff ( Model ) : + + def Interface ( self ) : + self.ck = SignalIn ( "ck", 1 ) + self.wen = SignalIn ( "wen", 1 ) + self.i = SignalIn ( "i", 4 ) + self.o = SignalOut ( "o", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenSff', 'sff_4' + , param = { 'nbit' : 4 + , 'physical' : True + } + ) + self.I = Inst ( 'sff_4', 'inst' + , map = { "wen" : self.wen + , "ck" : self.ck + , "i0" : self.i + , "q" : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgensfft.tex b/stratus1/doc/dpgen/man_dpgensfft.tex new file mode 100644 index 00000000..90db45dd --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgensfft.tex @@ -0,0 +1,77 @@ +\begin{itemize} + \item \textbf{Name} : DpgenSfft -- Static Flip-Flop with Scan-Path Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenSfft', modelname + , param = { 'nbit' : n + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a n bits static flip-flop with scan-path named \verb-modelname-. The two latches of this flip-flop are static i.e. each one is made of two interters looped togethers. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{scan} : scan-path mode (input, 1 bit) + \item \textbf{scin} : scan path in (input, 1 bit) + \item \textbf{wen} : write enable (1 bit) + \item \textbf{ck} : clock signal (1 bit) + \item \textbf{i0} : data input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the a map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item When scan is set to \verb-one-, it enables the scan-path mode. Note that in scan-path mode, the wen signal is not effective + \item scin : the input of the scan-path. This terminal is different from \verb-i0[0]-. The scout is \verb-q[N--\verb-1]- (in the following example this is \verb-q[3]-) + \item When wen is set to \verb-one-, it enables the writing of the flip-flop + \end{itemize} +% \item \textbf{Behavior} : +% \begin{verbatim} +% \end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_sfft ( Model ) : + + def Interface ( self ) : + self.scan = SignalIn ( "scin", 1 ) + self.scin = SignalIn ( "scan", 1 ) + self.ck = SignalIn ( "ck", 1 ) + self.wen = SignalIn ( "wen", 1 ) + self.i = SignalIn ( "in", 4 ) + self.o = SignalOut ( "out", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenSfft', 'sfft_4' + , param = { 'nbit' : 4 + , 'physical' : True + } + ) + self.I = Inst ( 'sfft_4', 'inst' + , map = { "wen" : self.wen + , "ck" : self.ck + , "scan" : self.scan + , "scin" : self.scin + , "i0" : self.i + , "q" : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenshift.tex b/stratus1/doc/dpgen/man_dpgenshift.tex new file mode 100644 index 00000000..a965068e --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenshift.tex @@ -0,0 +1,69 @@ +\begin{itemize} + \item \textbf{Name} : DpgenShift -- Shifter Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenShift', modelname + , param = { 'nbit' : n + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits shifter named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{op} : select the kind of shift (input, 2 bits) + \item \textbf{shamt} : the shift amount (input, \verb-Y- bits) + \item \textbf{i} : value to shift (input, \verb-n- bits) + \item \textbf{o} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item If the \verb-op[0]- signal is set to \verb-one-, performs a right shift, performs a left shift otherwise. + \item If the \verb-op[1]- signal is set to \verb-one-, performs an arithmetic shift (only meaningful in case of a right shift). + \item shamt : specifies the shift amount. The width of this signal (\verb-Y-) is computed from the operator's width : \verb-Y = ceil(log2(n)) -- 1 + \end{itemize} +% \item \textbf{Behavior} : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_shifter ( Model ) : + + def Interface ( self ) : + self.instop = SignalIn ( "instop", 2 ) + self.instshamt = SignalIn ( "instshamt", 2 ) + self.insti = SignalIn ( "insti", 4 ) + self.insto = SignalOut ( "insto", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenShifter', 'shifter_4' + , param = { 'nbit' : 4 + , 'physical' : True + } + ) + self.I = Inst ( 'shifter_4', 'inst' + , map = { 'op' : self.instop + , 'shamt' : self.instshamt + , 'i' : self.insti + , 'o' : self.insto + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenshrot.tex b/stratus1/doc/dpgen/man_dpgenshrot.tex new file mode 100644 index 00000000..0781929c --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenshrot.tex @@ -0,0 +1,70 @@ +\begin{itemize} + \item \textbf{Name} : DpgenShrot -- Shift/Rotation Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenShrot', modelname + , param = { 'nbit' : n + , 'physical' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits shift/rotation operator named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{op} : select the kind of shift/rotation (input, 3 bits) + \item \textbf{shamt} : the shift amount (input, \verb-Y- bits) + \item \textbf{i} : value to shift (input, \verb-n- bits) + \item \textbf{o} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item If the \verb-op[0]- signal is set to \verb-one-, performs a right shift/rotation , otherwise left shift/rotation occurs. + \item If the \verb-op[1]- signal is set to \verb-one-, performs an arithmetic shift (only meaningful in case of a right shift). + \item If the \verb-op[2]- signal is set to \verb-one-, performs a rotation, otherwise performs a shift.. + \item \verb-shamt- specifies the shift amount. The width of this signal (\verb-Y-) is computed from the operator's width : \verb-Y = ceil(log2(n))- - 1 + \end{itemize} +% \item \textbf{Behavior} : +%\begin{verbatim} +%\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_shrot ( Model ) : + + def Interface ( self ) : + self.rotop = SignalIn ( "rotop", 3 ) + self.instshamt = SignalIn ( "instshamt", 2 ) + self.insti = SignalIn ( "insti", 4 ) + self.insto = SignalOut ( "insto", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenShrot', 'shrot_4' + , param = { 'nbit' : 4 + , 'physical' : True + } + ) + self.I = Inst ( 'shrot_4', 'inst' + , map = { 'op' : self.rotop + , 'shamt' : self.instshamt + , 'i' : self.insti + , 'o' : self.insto + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenxnor2.tex b/stratus1/doc/dpgen/man_dpgenxnor2.tex new file mode 100644 index 00000000..485414b8 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenxnor2.tex @@ -0,0 +1,69 @@ +\begin{itemize} + \item \textbf{Name} : DpgenXnor2 -- Xnor2 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenXnor2', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits two inputs XNOR with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{nq} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 1 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= not ( i0 xor i1 ) +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_xnor2 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 8 ) + self.in2 = SignalIn ( "in2", 8 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenXnor2', 'xnor2_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'xnor2_8', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenxnor2mask.tex b/stratus1/doc/dpgen/man_dpgenxnor2mask.tex new file mode 100644 index 00000000..257e34fd --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenxnor2mask.tex @@ -0,0 +1,74 @@ +\begin{itemize} + \item \textbf{Name} : DpgenXnor2mask -- Programmable Mask Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenXnor2mask', modelname + , param = { 'nbit' : n + , 'const' : constVal + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits conditionnal XNOR mask named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{cmd} : mask control ( 1 bit ) + \item \textbf{i0} : input ( \verb-n- bits ) + \item \textbf{nq} : output ( \verb-n- bits ) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{const} (mandatory) : Defines the constant (string beginning with 0b, 0x or 0o functions of the basis) + \item \textbf{physical} (optional, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{How it works} : + \begin{itemize} + \item If the \verb-cmd- signal is set to \verb-zero-, the mask is NOT applied, so the whole operator behaves like an inverter. + \item If the \verb-cmd- signal is set to \verb-one-, the mask is applied, the output is the \emph{complemented} result of the input value \emph{XORed} with the mask (suplied by \verb-constVal-). + \item The constant \verb-constVal- is given to the macro-generator call, therefore the value cannot be changed afterward : it's hard wired in the operator. + \item A common error is to give a real constant for the \verb-constVal- argument. Be aware that it is a character string. + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= WITH cmd SELECT not(i0) WHEN '0', + not(i0 xor constVal) WHEN '1'; +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_xnor2mask ( Model ) : + + def Interface ( self ) : + self.i = SignalIn ( "i", 8 ) + self.cmd = SignalIn ( "cmd", 1 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenXnor2mask', 'xnor2mask_0b000111' + , param = { 'nbit' : 8 + , 'const' : "0b000111" + , 'physical' : True + } + ) + self.I = Inst ( 'xnor2mask_0b000111', 'inst' + , map = { 'i0' : self.i + , 'cmd' : self.cmd + , 'nq' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/dpgen/man_dpgenxor2.tex b/stratus1/doc/dpgen/man_dpgenxor2.tex new file mode 100644 index 00000000..dab83383 --- /dev/null +++ b/stratus1/doc/dpgen/man_dpgenxor2.tex @@ -0,0 +1,69 @@ +\begin{itemize} + \item \textbf{Name} : DpgenXor2 -- Xor2 Macro-Generator + \item \textbf{Synopsys} : +\begin{verbatim} +Generate ( 'DpgenXor2', modelname + , param = { 'nbit' : n + , 'drive' : d + , 'physical' : True + , 'behavioral' : True + } + ) +\end{verbatim} + \item \textbf{Description} : Generates a \verb-n- bits two inputs XOR with an output power of \verb-d- named \verb-modelname-. + \item \textbf{Terminal Names} : + \begin{itemize} + \item \textbf{i0} : input (\verb-n- bits) + \item \textbf{i1} : input (\verb-n- bits) + \item \textbf{q} : output (\verb-n- bits) + \item \textbf{vdd} : power + \item \textbf{vss} : ground + \end{itemize} + \item \textbf{Parameters} : Parameters are given in the map \verb-param-. + \begin{itemize} + \item \textbf{nbit} (mandatory) : Defines the size of the generator + \item \textbf{drive} (optional) : Defines the output power of the gates + \begin{itemize} + \item Valid drive are : 2 or 4 + \item If this parameter is not defined, it's value is the smallest one permitted + \end{itemize} + \item \textbf{physical} (optionnal, default value : False) : In order to generate a layout + \item \textbf{behavioral} (optionnal, default value : False) : In order to generate a behavior + \end{itemize} + \item \textbf{Behavior} : +\begin{verbatim} +nq <= i0 xor i1 +\end{verbatim} + \item \textbf{Example} : +\begin{verbatim} +from stratus import * + +class inst_xor2 ( Model ) : + + def Interface ( self ) : + self.in1 = SignalIn ( "in1", 8 ) + self.in2 = SignalIn ( "in2", 8 ) + self.o = SignalOut ( "o", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Generate ( 'DpgenXor2', 'xor2_8' + , param = { 'nbit' : 8 + , 'physical' : True + } + ) + self.I = Inst ( 'xor2_8', 'inst' + , map = { 'i0' : self.in1 + , 'i1' : self.in2 + , 'q' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.I, NOSYM, Ref(0, 0) ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/html.entry b/stratus1/doc/html.entry new file mode 100644 index 00000000..239ad936 --- /dev/null +++ b/stratus1/doc/html.entry @@ -0,0 +1 @@ +
  • Stratus
    Netlist / Layout description language

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+\verb-myNet.Alias ( net )- + +\subsubsection{Description} + +This method is applied to a net. This net has an "alias name". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-net- : a net which is going to be an alias for the net which this method is applied to +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class myripple ( Model ) : + + def Interface ( self ) : + self.a = LogicIn ( "a", 4 ) + self.b = LogicIn ( "b", 4 ) + + self.cin = LogicIn ( "cin", 1 ) + + self.sout = LogicOut ( "sout", 4 ) + + self.cout = LogicOut ( "cout", 1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VddIn ( "vss" ) + + def Netlist ( self ) : + c_temp = Signal ( "c_temp", 5 ) + + self.cin.Alias ( c_temp[0] ) + self.cout.Alias ( c_temp[4] ) + + for i in range ( 4 ) : + Inst ( "Fulladder" + , map = { 'a' : self.a[i] + , 'b' : self.b[i] + , 'cin' : c_temp[i] + , 'sout' : self.sout[i] + , 'cout' : c_temp[i+1] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) +\end{verbatim} + +\indent The net \verb-cin- has the alias \verb-c_temp[0]- and the net cout has the alias \verb-c_temp[4]-. Thanks to this method, all the instanciations can be done in one unique \verb-for- loop. + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Nets}}{}{Nets}{secnet} +\hyperref[ref]{\emph{Extend}}{}{Extend}{secextend} +\hyperref[ref]{\emph{Cat}}{}{Cat}{seccat} diff --git a/stratus1/doc/man_alim_connectors.tex b/stratus1/doc/man_alim_connectors.tex new file mode 100644 index 00000000..6830d9c2 --- /dev/null +++ b/stratus1/doc/man_alim_connectors.tex @@ -0,0 +1,23 @@ +\subsubsection{Name} + +AlimConnectors -- Creation of connectors at the periphery of the core of a circuit + +\subsubsection{Synopsys} + +\begin{verbatim} +AlimConnectors() +\end{verbatim} + +\subsubsection{Description} + +This function creates the connectors in Alu 1 at the periphery of the core. + + +%\subsubsection{Errors} + +%Some errors may occur : +%\begin{itemize} + %\item \verb-[Stratus ERROR] AlimConnectors : can't get net ...- +%\end{itemize} + +\input{see_also} diff --git a/stratus1/doc/man_alim_rail.tex b/stratus1/doc/man_alim_rail.tex new file mode 100644 index 00000000..9204883f --- /dev/null +++ b/stratus1/doc/man_alim_rail.tex @@ -0,0 +1,52 @@ +\subsubsection{Name} + +AlimVerticalRail, AlimHorizontalRail -- Placement of a vertical/horizontal alimentation call back + +\subsubsection{Synopsys} + +\begin{verbatim} +AlimVerticalRail ( nb ) +\end{verbatim} + +\subsubsection{Description} + +These functions place a vertical/horizontal alimentation call back. It's position is given by the parameter given. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-nb- : coordinate of the rail + \begin{itemize} + \item For AlimVerticalRail, \verb-nb- is in pitches i.e. 5 lambdas + \item For AlimHorizontalRail, \verb-nb- is in slices i.e. 50 lambdas + \end{itemize} +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +AlimVerticalRail ( 50 ) +AlimVerticalRail ( 150 ) + +AlimHorizontalRail ( 10 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] AlimHorizontalRail :-\\\verb-Illegal argument y, y must be between ... and ...-\\The argument given is wrong : the call back would not be in the abutment box. + \item \verb-[Stratus ERROR] Placement of cells :-\\\verb-please check your file of layout with DRUC.-\\The placement of the cell needs to be correct in order to place a call back. Check the errors of placement. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} diff --git a/stratus1/doc/man_arithmetic.tex b/stratus1/doc/man_arithmetic.tex new file mode 100644 index 00000000..d6a9dba6 --- /dev/null +++ b/stratus1/doc/man_arithmetic.tex @@ -0,0 +1,73 @@ + \subsubsection{Description} + +Most common arithmetic operators can be instantiated without the \verb-Inst- constructor. + +\subsubsection{List} + +Arithmetical operators are listed below : +\begin{itemize} + \item \verb-Addition- : \verb-q <= i0 + i1- + \item \verb-Substraction- : \verb-q <= i0- - \verb-i1- + \item \verb-Multiplication- : \verb-q <= i0 * i1- + \item \verb-Division- : \verb-q <= i0 / i1- +\end{itemize} + +\subsubsection{Generators to instantiate} + +One can choose the generator to be used. Some methods are applied to the cell and set the generator used when using overloard. +\indent Methods are : +\begin{itemize} + \item \verb-SetAdd- (for addition and substraction) + \item \verb-SetMult- + \item \verb-SetDiv- +\end{itemize} + +\indent The generators used by default are : +\begin{itemize} + \item \verb-Addition- : Slansky adder + \item \verb-Substraction- : Slansky adder + inversor + cin = '1' + \item \verb-Multiplication- : CA2 multiplier (signed, modified booth/Wallace tree) + \item \verb-Division- : not available yet +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = LogicIn ( "a", 4 ) + self.B = LogicIn ( "b", 4 ) + + self.S = LogicOut ( "s", 4 ) + + self.T = LogicOut ( "t", 8 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S <= self.A + self.B + + self.T <= self.A * self.B +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] + : the nets must have the same lenght.-\\When one uses arithmetic expressions, one has to check that the sizes of both nets are equivalent. + \item \verb-[Stratus ERROR] : there is no alim.-\\The cell being created does not have the alimentation nets. The instanciation is impossible. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multiplexor}{secmux} +\hyperref[ref]{\emph{Instanciation of a shifter}}{}{Shifter}{secshift} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} diff --git a/stratus1/doc/man_boolean.tex b/stratus1/doc/man_boolean.tex new file mode 100644 index 00000000..25086cca --- /dev/null +++ b/stratus1/doc/man_boolean.tex @@ -0,0 +1,65 @@ +\subsubsection{Description} + +Most common boolean operators can be instantiated without the \verb-Inst- constructor. + +\subsubsection{List} + +Boolean operators are listed below : +\begin{itemize} + \item \verb-And2- : \verb-q <= i0 & i1- + \item \verb-Or2- : \verb-q <= i0 | i1- + \item \verb-Xor2- : \verb-q <= i0 ^ i1- + \item \verb-Inv- : \verb-q <= ~i0- +\end{itemize} + + +\subsubsection{Generators to instantiate} + +One can choose the generator to be used. Some methods are applied to the cell and set the generator used when using \verb-&-, \verb-|-, \verb-^- and \verb-~-. The generators used by default are the ones from the virtual library.\\ + +\indent Methods are : +\begin{itemize} + \item \verb-SetAnd- + \item \verb-SetOr- + \item \verb-SetXor- + \item \verb-SetNot- +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = LogicIn ( "a", 4 ) + self.B = LogicIn ( "b", 4 ) + self.B = LogicIn ( "c", 4 ) + + self.S = LogicOut ( "s", 4 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S <= ( ~self.A & self.B ) | self.C +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] & : the nets must have the same lenght.-\\When one uses boolean expressions, one has to check that the sizes of both nets are equivalent. + \item \verb-[Stratus ERROR] : there is no alim.-\\The cell being created does not have the alimentation nets. The instanciation is impossible. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multiplexor}{secmux} +\hyperref[ref]{\emph{Instanciation of a shifter}}{}{Shifter}{secshift} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} diff --git a/stratus1/doc/man_buff.tex b/stratus1/doc/man_buff.tex new file mode 100644 index 00000000..c5ecebbe --- /dev/null +++ b/stratus1/doc/man_buff.tex @@ -0,0 +1,44 @@ +\subsubsection{Name} + +Buffer -- Easy way to instantiate a buffer + +\subsubsection{Synopsys} + +\begin{verbatim} +netOut <= netIn.Buffer() +\end{verbatim} + +\subsubsection{Description} + +This method is a method of net. The net which this method is applied to is the input net of the buffer. The method returns a net : the output net.\\ +\indent Note that it is possible to change the generator instanciated with the \verb-SetBuff- method. + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = LogicIn ( "a", 4 ) + + self.S = LogicOut ( "s", 4 ) + + self.Vdd = VddIn ( "vdd" ) + self.Vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S <= self.A.Buffer() +\end{verbatim} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multiplexor}{secmux} +\hyperref[ref]{\emph{Instanciation of a shifter}}{}{Shifter}{secshift} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} diff --git a/stratus1/doc/man_cat.tex b/stratus1/doc/man_cat.tex new file mode 100644 index 00000000..bf1ab5a1 --- /dev/null +++ b/stratus1/doc/man_cat.tex @@ -0,0 +1,47 @@ +\subsubsection{Name} + +Cat -- Concatenation of nets + +\subsubsection{Synopsys} + +\begin{verbatim} +Cat ( net1, net2 ) +\end{verbatim} + +\subsubsection{Description} + +Concatenation of nets. The nets are given as parameters, the concatenation starts with the MSB. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-nets- : list of nets to be concatened (tuple or array) +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +myNet <= Cat ( A, B ) +\end{verbatim} +\indent Or : +\begin{verbatim} +tab = [] +tab.append ( A ) +tab.append ( B ) +myNet <= Cat ( tab ) +\end{verbatim} + +\indent If A and B are 2 bits nets, the net \verb-myNet- will be such as : +\begin{verbatim} +myNet[3] = A[1] +myNet[2] = A[0] +myNet[1] = B[1] +myNet[0] = B[0] +\end{verbatim} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Nets}}{}{Nets}{secnet} +\hyperref[ref]{\emph{Alias}}{}{Alias}{secalias} +\hyperref[ref]{\emph{Extend}}{}{Extend}{secextend} diff --git a/stratus1/doc/man_comp.tex b/stratus1/doc/man_comp.tex new file mode 100644 index 00000000..c38777be --- /dev/null +++ b/stratus1/doc/man_comp.tex @@ -0,0 +1,67 @@ +\subsubsection{Name} + +Eq/Ne : Easy way to test the value of the nets + +\subsubsection{Synopsys} + +\begin{verbatim} +netOut <= net.Eq ( "n" ) +\end{verbatim} + +\subsubsection{Description} + +Comparaison functions are listed below : +\begin{itemize} + \item \verb-Eq- : returns \verb-true- if the value of the net is equal to \verb-n-. + \item \verb-Ne- : returns \verb-true- if the value of the net is different from \verb-n-. +\end{itemize} +\indent Note that it is possible to change the generator instanciated with the \verb-SetComp- method. + +\subsubsection{Parameters} + +The constant given as argument must be a string representing : +\begin{itemize} + \item A decimal number + \item A binary number : the string must begin with "0b" + \item An hexadecimal number : the string must begin with "0x" +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = LogicIn ( "a", 4 ) + + self.S = LogicOut ( "s", 1 ) + self.T = LogicOut ( "t", 1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S <= self.A.Eq ( "4" ) + + self.T <= self.A.Ne ( "1" ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Eq : the number does not match with the net's lenght.-\\When one uses comparaison functions on one net, one has to check that the number corresponds to the size of the net. + \item \verb-[Stratus ERROR] Eq :-\\\verb-the argument must be a string representing a number in decimal, binary (0b) or hexa (0x).-\\The string given as argument does not have the right form. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multipliexor}{secmux} +\hyperref[ref]{\emph{Instanciation of a shifter}}{Shifter}{}{secshift} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Instanciation of constants}}{Constant}{}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} diff --git a/stratus1/doc/man_const.tex b/stratus1/doc/man_const.tex new file mode 100644 index 00000000..c16a5b30 --- /dev/null +++ b/stratus1/doc/man_const.tex @@ -0,0 +1,81 @@ +\subsubsection{Name} + +Constant -- Easy way to instantiate constants + +\subsubsection{Synopsys} + +\begin{verbatim} +netOne <= One ( 2 ) + +net8 <= "8" +\end{verbatim} + +\subsubsection{Description} + +These functions simplify the way to instanciate constants. +\begin{itemize} + \item The functions \verb-One- and\verb-Zero- permits to initialise all the bits of a net to 'one' or 'zero'. + \item The instanciation of a constant thanks to a string can be done in decimal, hecadecimal or binary. +\end{itemize} + +\subsubsection{Parameters} + +\begin{itemize} + \item For \verb-One- and \verb-Zero- : + \begin{itemize} + \item \verb-n- : the arity of the net + \end{itemize} + \item For the instanciation of a constant : + \begin{itemize} + \item the constant given must be a string representing : + \begin{itemize} + \item A decimal number + \item A binary number : the string must begin with "0b" + \item An hexadecimal number : the string must begin with "0x" + \end{itemize} + \end{itemize} +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.Ones = LogicOut ( "ones", 2 ) + self.Zeros = LogicOut ( "zeros", 4 ) + + self.Eight = LogicOut ( "eight", 4 ) + self.Twentu = LogicOut ( "twenty", 5 ) + self.Two = LogicOut ( "two", 5 ) + + self.Vdd = VddIn ( "vdd" ) + self.Vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.Ones <= One ( 2 ) + self.Zero <= Zero ( 4 ) + + self.Eight <= "8" + self.Twenty <= "0x14" + self.Two <= "0b10" +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Const :-\\\verb-the argument must be a string representing a number in decimal, binary (0b) or hexa (0x).-\\The string given as argument does not have the right form. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multiplexor}{secmux} +\hyperref[ref]{\emph{Instanciation of a shifter}}{}{Shifter}{secshift} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} diff --git a/stratus1/doc/man_def_ab.tex b/stratus1/doc/man_def_ab.tex new file mode 100644 index 00000000..b92e81b1 --- /dev/null +++ b/stratus1/doc/man_def_ab.tex @@ -0,0 +1,49 @@ +\subsubsection{Name} + +DefAb -- Creates the abutment box of the current cell + +\subsubsection{Synopsys} + +\begin{verbatim} +DefAb ( x1, y1, x2, y2 ) +\end{verbatim} + +\subsubsection{Description} + +This function creates the abutment box of the current cell.\\ + +\indent Note that one does not have to call this function before saving in order to create the abutment box. The abutment box is created nevertheless (given to placed instances). This function is usefull if one wants to create an abutment before placing the instances. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-( x1, y1)- : coordinates of the bottom left corner of the created abutment box. + \item \verb-( x2, y2)- : coordinates of the top right corner of the created abutment box. +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +DefAb ( 0, 0, 500, 100 ) + +Place ( Inv, NOSYM, 0, 0 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] DefAb : an abutment box already exists.-\\\verb- Maybe you should use ResizeAb function.-\\One has called DefAb but the current cell already has an abutment box.\\In order to modify the current abutment box, the function to call is ResizeAb. + \item \verb-[Stratus ERROR] DefAb :-\\\verb-Coordinates of an abutment Box in y must be multiple of the slice.-\\\verb-Coordinates of an abutment Box in x must be multiple of the pitch.-\\One has called DefAb with non authorized values. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} diff --git a/stratus1/doc/man_dpgenadsb2f.tex b/stratus1/doc/man_dpgenadsb2f.tex new file mode 100644 index 00000000..a43041df --- /dev/null +++ b/stratus1/doc/man_dpgenadsb2f.tex @@ -0,0 +1,58 @@ +\begin{itemize} + \item Name : DpgenAdsb2f -- Adder/Substractor Macro-Generator + \item Description : Generates a \verb-n- bits adder/substractor named \verb-modelname-. + \item How it works : + \begin{itemize} + \item if the \verb-add_sub- signal is set to \verb-zero- an addition is performed, otherwise it's a substraction. + \item Operation can be either signed or unsigned. In unsigned mode \verb-c31- is the overflow. in signed mode you have to compute overflow by \emph{XORing} \verb-c31- and \verb-c30- + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item add\_sub : select addition or substraction (input, 1 bit) + \item c31 : carry out. In unsigned mode, this is the overflow (output, 1 bit) + \item c30 : used to compute overflow in signed mode : \verb-overflow = c31 xor c30- (output, 1 bit) + \item i0 : first operand (input, \verb-n- bits) + \item i1 : second operand (input, \verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 8 ) + self._in2 = LogicIn ( "in2", 8 ) + + self._out = LogicOut ( "out", 8 ) + + self._as = LogicIn ( "as", 1 ) + self._c0 = LogicOut ( "c0", 1 ) + self._c1 = LogicOut ( "c1", 1 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenAdsb2f' + , param = { 'nbit' : 8 } + , map = { 'i0' : self._in + , 'i1' : self._in2 + , 'add_sub' : self._as + , 'q' : self._out + , 'c30' : self._c0 + , 'c31' : self._c1 + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenand2.tex b/stratus1/doc/man_dpgenand2.tex new file mode 100644 index 00000000..83dc5a11 --- /dev/null +++ b/stratus1/doc/man_dpgenand2.tex @@ -0,0 +1,48 @@ +\begin{itemize} + \item Name : DpgenAnd2 -- And2 Macro-Generator + \item Description : Generates a \verb-n- bits two inputs AND with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 2 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= i0 and i1 +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenAnd2' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenand3.tex b/stratus1/doc/man_dpgenand3.tex new file mode 100644 index 00000000..2c008f75 --- /dev/null +++ b/stratus1/doc/man_dpgenand3.tex @@ -0,0 +1,51 @@ +\begin{itemize} + \item Name : DpgenAnd3 -- And3 Macro-Generator + \item Description : Generates a \verb-n- bits three inputs AND with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 2 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item i2 : input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= i0 and i1 and i2 +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + self._in2 = LogicIn ( "in2", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenAnd3' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'i2' : self._in2 + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenand4.tex b/stratus1/doc/man_dpgenand4.tex new file mode 100644 index 00000000..2fc00f09 --- /dev/null +++ b/stratus1/doc/man_dpgenand4.tex @@ -0,0 +1,54 @@ +\begin{itemize} + \item Name : DpgenAnd4 -- And4 Macro-Generator + \item Description : Generates a \verb-n- bits four inputs AND with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 2 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item i2 : input (\verb-n- bits) + \item i3 : input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= i0 and i1 and i2 and i3 +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + self._in2 = LogicIn ( "in2", 32 ) + self._in3 = LogicIn ( "in3", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenAnd4' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'i2' : self._in2 + , 'i3' : self._in3 + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenbuff.tex b/stratus1/doc/man_dpgenbuff.tex new file mode 100644 index 00000000..78e1ed04 --- /dev/null +++ b/stratus1/doc/man_dpgenbuff.tex @@ -0,0 +1,45 @@ +\begin{itemize} + \item Name : DpgenBuff -- Buffer Macro-Generator + \item Description : Generates a \verb-n- bits inverter with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 2, 4 or 8 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= i0 +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenBuff' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenbuse.tex b/stratus1/doc/man_dpgenbuse.tex new file mode 100644 index 00000000..54eb3a71 --- /dev/null +++ b/stratus1/doc/man_dpgenbuse.tex @@ -0,0 +1,49 @@ +\begin{itemize} + \item Name : DpgenBuse -- Tristate Macro-Generator + \item Description : Generates a \verb-n- bits tristate with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 4 or 8 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item cmd : select ( 1 bit ) + \item i0 : input ( \verb-n- bits ) + \item q : output ( \verb-n- bits ) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} + \item Behavior : +\begin{verbatim} +nts:BLOCK(cmd = '1') BEGIN + q <= GUARDED i0; +END +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 32 ) + self._cmd = LogicIn ( "cmd", 1 ) + + self._out = TriState ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenBuse' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in + , 'cmd' : self._cmd + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenconst.tex b/stratus1/doc/man_dpgenconst.tex new file mode 100644 index 00000000..c2658547 --- /dev/null +++ b/stratus1/doc/man_dpgenconst.tex @@ -0,0 +1,38 @@ +\begin{itemize} + \item Name : DpgenConst -- Constant Macro-Generator + \item Description : Generates a \verb-n- bits constant named \verb-modelname-. + \item Terminal Names : + \begin{itemize} + \item q : the constant (output, \verb-n- bit) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item const : Defines the constant + \item nbit : Defines the size of the generator + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._out = LogicOut ( "out", 8 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + Inst ( 'DpgenConst' + , param = { 'nbit' : 8 + , 'const' : "0xA1" + } + , map = { 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgendff.tex b/stratus1/doc/man_dpgendff.tex new file mode 100644 index 00000000..f8483c22 --- /dev/null +++ b/stratus1/doc/man_dpgendff.tex @@ -0,0 +1,50 @@ +\begin{itemize} + \item Name : DpgenDff -- Dynamic Flip-Flop Macro-Generator + \item Description : Generates a n bits dynamic flip-flop named \verb-modelname-. The two latches of this flip-flop are dynamic, i.e. the data is stored in a capacitor. + \item How it works : + \begin{itemize} + \item when wen is set to \verb-one-, enables the writing of the flip-flop + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item wen : write enable (1 bit) + \item ck : clock signal (1 bit) + \item i0 : data input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._ck = LogicIn ( "ck", 1 ) + self._wen = LogicIn ( "wen", 1 ) + self._in = LogicIn ( "in", 4 ) + + self._out = LogicOut ( "out", 4 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenDff' + , param = { 'nbit' : 4 } + , map = { "wen" : self._wen + , "ck" : self._ck + , "i0" : self._in + , "q" : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgendfft.tex b/stratus1/doc/man_dpgendfft.tex new file mode 100644 index 00000000..65d3de90 --- /dev/null +++ b/stratus1/doc/man_dpgendfft.tex @@ -0,0 +1,58 @@ +\begin{itemize} + \item Name : DpgenDfft -- Dynamic Flip-Flop with Scan-Path Macro-Generator + \item Description : Generates a n bits dynamic flip-flop with scan-path named \verb-modelname-. The two latches of this flip-flop are dynamic, i.e. the data is stored in a capacitor. + \item How it works : + \begin{itemize} + \item scan : when set to \verb-one- enables the scan-path mode. Note that in scan-path mode, the wen signal is not effective + \item scin : the input of the scan-path. This terminal is different from \verb-i0[0]-. The scout is q[N-1] (in the following example this is \verb-q[31]-) + \item when wen is set to \verb-one- enables the writing of the flip-flop + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item scan : scan-path mode (input, 1 bit) + \item scin : scan path in (input, 1 bit) + \item wen : write enable (1 bit) + \item ck : clock signal (1 bit) + \item i0 : data input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._scan = LogicIn ( "scin", 1 ) + self._scin = LogicIn ( "scan", 1 ) + self._ck = LogicIn ( "ck", 1 ) + self._wen = LogicIn ( "wen", 1 ) + self._in = LogicIn ( "in", 4 ) + + self._out = LogicOut ( "out", 4 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenDfft' + , param = { 'nbit' : 4 } + , map = { "wen" : self._wen + , "ck" : self._ck + , "scan" : self._scan + , "scin" : self._scin + , "i0" : self._in + , "q" : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenfifo.tex b/stratus1/doc/man_dpgenfifo.tex new file mode 100644 index 00000000..8da737fd --- /dev/null +++ b/stratus1/doc/man_dpgenfifo.tex @@ -0,0 +1,79 @@ +\begin{itemize} + \item Name : DpgenFifo -- Fifo Macro-Generator + \item Description : Generates a FIFO pf \verb-ergNumber- words of \verb-n- bits named \verb-modelname-. + \item How it works : + \begin{itemize} + \item datain0 and datain1 : the two write busses. Only one is used to actually write the FIFO, it is selected by the sel signal. + \item sel : when set to \verb-zero- the datain0 is used to write the register word, otherwise it will be datain1. + \item r, rok : set r when a word is requested, rok tells that a word has effectively been popped (rok == not empty). + \item w, wok : set w when a word is pushed, wok tells that the word has effectively been pushed (wok == not full). + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item ck : clock signal (input, 1 bit) + \item reset : reset signal (input, 1 bit) + \item r : read requested (input, 1 bit) + \item w : write requested (input, 1 bit) + \item rok : read acknowledge (output, 1 bit) + \item wok : write acknowledge (output, 1 bit) + \item sel : select the write bus (input, 1 bit) + \item datain0 : first write bus (input, \verb-n- bits) + \item datain1 : second write bus (input, \verb-n- bits) + \item dataout : read bus (output, \verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the words (even, between 2 and 64) + \item nword : Defines the number of words (even, between 4 and 32) + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + global nbit, nword + nbit = 4 + nword = 16 + + def Interface ( self ) : + + self._ck = LogicIn ( "ck", 1 ) + self._reset = LogicIn ( "reset", 1 ) + self._r = LogicIn ( "r", 1 ) + self._w = LogicIn ( "w", 1 ) + self._rok = LogicInOut ( "rok", 1 ) + self._wok = LogicInOut ( "wok", 1 ) + self._sel = LogicIn ( "sel", 1 ) + + self._datain0 = LogicIn ( "datain0", nbit ) + self._datain1 = LogicIn ( "datain1", nbit ) + self._dataout = LogicOut ( "dataout", nbit ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenFifo' + , param = { 'nword' : nword + , 'nbit' : nbit + } + , map = { 'ck' : self._ck + , 'reset' : self._reset + , 'r' : self._r + , 'w' : self._w + , 'rok' : self._rok + , 'wok' : self._wok + , 'sel' : self._sel + , 'datain0' : self._datain0 + , 'datain1' : self._datain1 + , 'dataout' : self._dataout + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgeninv.tex b/stratus1/doc/man_dpgeninv.tex new file mode 100644 index 00000000..5198b454 --- /dev/null +++ b/stratus1/doc/man_dpgeninv.tex @@ -0,0 +1,45 @@ +\begin{itemize} + \item Name : DpgenInv -- Inverter Macro-Generator + \item Description : Generates a \verb-n- bits inverter with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1, 2, 4 or 8 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item \verb-i0- : input (\verb-n- bits) + \item \verb-nq- : output (\verb-n- bits) + \item \verb-vdd- : power + \item \verb-vss- : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= not ( i0 ) +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenInv' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenmux2.tex b/stratus1/doc/man_dpgenmux2.tex new file mode 100644 index 00000000..1f0f6cf1 --- /dev/null +++ b/stratus1/doc/man_dpgenmux2.tex @@ -0,0 +1,54 @@ +\begin{itemize} + \item Name : DpgenMux2 -- Multiplexer Macro-Generator + \item Description : Generates a \verb-n- bits two inputs multiplexer with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 2 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item cmd : select ( 1 bit ) + \item i0 : input ( \verb-n- bits ) + \item i1 : input ( \verb-n- bits ) + \item q : output ( \verb-n- bits ) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item nbit\_cmd : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= WITH cmd SELECT i0 WHEN '0', + i1 WHEN '1'; +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + + self._cmd = LogicIn ( "cmd", 1 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenMux2' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'cmd' : self._cmd + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennand2.tex b/stratus1/doc/man_dpgennand2.tex new file mode 100644 index 00000000..2dfaf8fd --- /dev/null +++ b/stratus1/doc/man_dpgennand2.tex @@ -0,0 +1,48 @@ +\begin{itemize} + \item Name : DpgenNand2 -- Nand2 Macro-Generator + \item Description : Generates a \verb-n- bits two inputs NAND with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item nq : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= not ( i0 and i1 ) +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNand2' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennand2mask.tex b/stratus1/doc/man_dpgennand2mask.tex new file mode 100644 index 00000000..5a228ae3 --- /dev/null +++ b/stratus1/doc/man_dpgennand2mask.tex @@ -0,0 +1,55 @@ +\begin{itemize} + \item Name : DpgenNand2mask -- Programmable Mask Macro-Generator + \item Description : Generates a \verb-n- bits conditionnal NAND mask named \verb-modelname-. + \item How it works : + \begin{itemize} + \item if the \verb-cmd- signal is set to \verb-zero-, the mask is NOT applied, so the whole operator behaves like an inverter. + \item if the \verb-cmd- signal is set to \verb-one-, the mask is applied, the output is the \emph{complemented} result of the input value \emph{ANDed} with the mask (suplied by \verb-constVal-). + \item The constant \verb-constVal- is given to the macro-generator call, therefore the value cannot be changed afterward : it's hard wired in the operator. + \item A common error is to give a real constant for the \verb-constVal- argument. Be aware that it is a character string. + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item cmd : mask control ( 1 bit ) + \item i0 : input ( \verb-n- bits ) + \item nq : output ( \verb-n- bits ) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item const : Defines the constant + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= WITH cmd SELECT not(i0) WHEN '0', + not(i0 and X"0000FFFF") WHEN '1'; +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 8 ) + self._cmd = LogicIn ( "cmd", 1 ) + + self._out = LogicOut ( "out", 8 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNand2mask' + , param = { 'nbit' : 8 + , 'const' : "0b000111" + } + , map = { 'i0' : self._in + , 'cmd' : self._cmd + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennand3.tex b/stratus1/doc/man_dpgennand3.tex new file mode 100644 index 00000000..c8fa1fd1 --- /dev/null +++ b/stratus1/doc/man_dpgennand3.tex @@ -0,0 +1,51 @@ +\begin{itemize} + \item Name : DpgenNand3 -- Nand3 Macro-Generator + \item Description : Generates a \verb-n- bits three inputs NAND with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item i2 : input (\verb-n- bits) + \item nq : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= not ( i0 and i1 and i2 ) +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + self._in2 = LogicIn ( "in2", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNand3' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'i2' : self._in2 + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennand4.tex b/stratus1/doc/man_dpgennand4.tex new file mode 100644 index 00000000..3880243a --- /dev/null +++ b/stratus1/doc/man_dpgennand4.tex @@ -0,0 +1,54 @@ +\begin{itemize} + \item Name : DpgenNand4 -- Nand4 Macro-Generator + \item Description : Generates a \verb-n- bits four inputs NAND with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item i2 : input (\verb-n- bits) + \item i3 : input (\verb-n- bits) + \item nq : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= not ( i0 and i1 and i2 and i3 ) +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + self._in2 = LogicIn ( "in2", 32 ) + self._in3 = LogicIn ( "in3", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNand4' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'i2' : self._in2 + , 'i3' : self._in3 + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennbuse.tex b/stratus1/doc/man_dpgennbuse.tex new file mode 100644 index 00000000..f2882a14 --- /dev/null +++ b/stratus1/doc/man_dpgennbuse.tex @@ -0,0 +1,46 @@ +\begin{itemize} + \item Name : DpgenNbuse -- Tristate Macro-Generator + \item Description : Generates a \verb-n- bits tristate with an complemented output named \verb-modelname-. + \item Terminal Names : + \begin{itemize} + \item cmd : select ( 1 bit ) + \item i0 : input ( \verb-n- bits ) + \item nq : output ( \verb-n- bits ) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} + \item Behavior : +\begin{verbatim} +nts:BLOCK(cmd = '1') BEGIN + nq <= GUARDED not(i0); +END +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 32 ) + self._cmd = LogicIn ( "cmd", 1 ) + + self._out = TriState ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNbuse' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in + , 'cmd' : self._cmd + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennmux2.tex b/stratus1/doc/man_dpgennmux2.tex new file mode 100644 index 00000000..bb7ddd76 --- /dev/null +++ b/stratus1/doc/man_dpgennmux2.tex @@ -0,0 +1,55 @@ +\begin{itemize} + \item Name : DpgenNmux2 -- Multiplexer Macro-Generator +% \item Description : Generates a \verb-n- bits two inputs multiplexer with an output power of \verb-drive- named \verb-modelname-. + \item Description : Generates a \verb-n- bits two inputs multiplexer named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item cmd : select ( 1 bit ) + \item i0 : input ( \verb-n- bits ) + \item i1 : input ( \verb-n- bits ) + \item nq : output ( \verb-n- bits ) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item nbit\_cmd : Defines the size of the generator +% \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= WITH cmd SELECT not i0 WHEN '0', + not i1 WHEN '1'; +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + + self._cmd = LogicIn ( "cmd", 1 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNmux2' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'cmd' : self._cmd + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennor2.tex b/stratus1/doc/man_dpgennor2.tex new file mode 100644 index 00000000..f9501895 --- /dev/null +++ b/stratus1/doc/man_dpgennor2.tex @@ -0,0 +1,48 @@ +\begin{itemize} + \item Name : DpgenNor2 -- Nor2 Macro-Generator + \item Description : Generates a \verb-n- bits two inputs NOR with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item nq : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= not ( i0 or i1 ) +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNor2' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennor2mask.tex b/stratus1/doc/man_dpgennor2mask.tex new file mode 100644 index 00000000..34394014 --- /dev/null +++ b/stratus1/doc/man_dpgennor2mask.tex @@ -0,0 +1,55 @@ +\begin{itemize} + \item Name : DpgenNor2mask -- Programmable Mask Macro-Generator + \item Description : Generates a \verb-n- bits conditionnal NOR mask named \verb-modelname-. + \item How it works : + \begin{itemize} + \item if the \verb-cmd- signal is set to \verb-zero-, the mask is NOT applied, so the whole operator behaves like an inverter. + \item if the \verb-cmd- signal is set to \verb-one-, the mask is applied, the output is the \emph{complemented} result of the input value \emph{ORed} with the mask (suplied by \verb-constVal-). + \item The constant \verb-constVal- is given to the macro-generator call, therefore the value cannot be changed afterward : it's hard wired in the operator. + \item A common error is to give a real constant for the \verb-constVal- argument. Be aware that it is a character string. + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item cmd : mask control ( 1 bit ) + \item i0 : input ( \verb-n- bits ) + \item nq : output ( \verb-n- bits ) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item const : Defines the constant + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= WITH cmd SELECT not(i0) WHEN '0', + not(i0 or X"0000FFFF") WHEN '1'; +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 8 ) + self._cmd = LogicIn ( "cmd", 1 ) + + self._out = LogicOut ( "out", 8 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNor2mask' + , param = { 'nbit' : 8 + , 'const' : "0b000111" + } + , map = { 'i0' : self._in + , 'cmd' : self._cmd + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennor3.tex b/stratus1/doc/man_dpgennor3.tex new file mode 100644 index 00000000..caa845a0 --- /dev/null +++ b/stratus1/doc/man_dpgennor3.tex @@ -0,0 +1,51 @@ +\begin{itemize} + \item Name : DpgenNor3 -- Nor3 Macro-Generator + \item Description : Generates a \verb-n- bits three inputs NOR with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item i2 : input (\verb-n- bits) + \item nq : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= not ( i0 or i1 or i2 ) +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + self._in2 = LogicIn ( "in2", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNor3' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'i2' : self._in2 + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennor4.tex b/stratus1/doc/man_dpgennor4.tex new file mode 100644 index 00000000..a7a3f0bb --- /dev/null +++ b/stratus1/doc/man_dpgennor4.tex @@ -0,0 +1,54 @@ +\begin{itemize} + \item Name : DpgenNor4 -- Nor4 Macro-Generator + \item Description : Generates a \verb-n- bits four inputs NOR with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item i2 : input (\verb-n- bits) + \item i3 : input (\verb-n- bits) + \item nq : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= not ( i0 or i1 or i2 or i3 ) +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + self._in2 = LogicIn ( "in2", 32 ) + self._in3 = LogicIn ( "in3", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNor4' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'i2' : self._in2 + , 'i3' : self._in3 + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgennul.tex b/stratus1/doc/man_dpgennul.tex new file mode 100644 index 00000000..be68a6b6 --- /dev/null +++ b/stratus1/doc/man_dpgennul.tex @@ -0,0 +1,41 @@ +\begin{itemize} + \item Name : DpgenNul -- Zero Detector Macro-Generator + \item Description : Generates a \verb-n- bits zero detector named \verb-modelname-. + \item Terminal Names : + \begin{itemize} + \item i0 : value to check (input, \verb-n- bits) + \item q : null flag (1 bit) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} + \item Behavior : +\begin{verbatim} +q <= '1' WHEN ( i0 = X"00000000" ) ELSE '0'; +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 32 ) + + self._out = LogicOut ( "out", 1 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenNul' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in + , 'nul' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenor2.tex b/stratus1/doc/man_dpgenor2.tex new file mode 100644 index 00000000..5fbe5bef --- /dev/null +++ b/stratus1/doc/man_dpgenor2.tex @@ -0,0 +1,48 @@ +\begin{itemize} + \item Name : DpgenOr2 -- Or2 Macro-Generator + \item Description : Generates a \verb-n- bits two inputs OR with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 2 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= i0 or i1 +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenOr2' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenor3.tex b/stratus1/doc/man_dpgenor3.tex new file mode 100644 index 00000000..6c99bfd6 --- /dev/null +++ b/stratus1/doc/man_dpgenor3.tex @@ -0,0 +1,51 @@ +\begin{itemize} + \item Name : DpgenOr3 -- Or3 Macro-Generator + \item Description : Generates a \verb-n- bits three inputs OR with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 2 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item i2 : input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= i0 or i1 or i2 +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + self._in2 = LogicIn ( "in2", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenOr3' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'i2' : self._in2 + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenor4.tex b/stratus1/doc/man_dpgenor4.tex new file mode 100644 index 00000000..ceb6e381 --- /dev/null +++ b/stratus1/doc/man_dpgenor4.tex @@ -0,0 +1,54 @@ +\begin{itemize} + \item Name : DpgenOr4 -- Or4 Macro-Generator + \item Description : Generates a \verb-n- bits four inputs OR with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 2 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item i2 : input (\verb-n- bits) + \item i3 : input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= i0 or i1 or i2 or i3 +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + self._in2 = LogicIn ( "in2", 32 ) + self._in3 = LogicIn ( "in3", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenOr4' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'i2' : self._in2 + , 'i3' : self._in3 + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenram.tex b/stratus1/doc/man_dpgenram.tex new file mode 100644 index 00000000..45b7c58d --- /dev/null +++ b/stratus1/doc/man_dpgenram.tex @@ -0,0 +1,56 @@ +\begin{itemize} + \item Name : DpgenRam -- RAM Macro-Generator + \item Description : Generates a RAM of \verb-regNumber- words of \verb-n- bits named \verb-modelname-. + \item Terminal Names : + \begin{itemize} + \item ck : clock signal (input, 1 bit) + \item w : write requested (input, 1 bit) + \item selram : select the write bus (input, 1 bit) + \item ad : the address (input, \verb-Y- bits) + \item datain : write bus (input, \verb-n- bits) + \item dataout : read bus (output, \verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item nword : Defines the size of the words + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._ck = LogicIn ( "ck", 1 ) + self._w = LogicIn ( "w", 1 ) + self._selram = LogicIn ( "selram", 1 ) + + self._ad = LogicIn ( "ad", 5 ) + self._datain = LogicIn ( "datain", 32 ) + + self._dataout = TriState ( "dataout", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenRam' + , param = { 'nword' : 32 + , 'nbit' : 32 + } + , map = { 'ck' : self._ck + , 'w' : self._w + , 'selram' : self._selram + , 'ad' : self._ad + , 'datain' : self._datain + , 'dataout' : self._dataout + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenrf1.tex b/stratus1/doc/man_dpgenrf1.tex new file mode 100644 index 00000000..7b332c1d --- /dev/null +++ b/stratus1/doc/man_dpgenrf1.tex @@ -0,0 +1,70 @@ +\begin{itemize} + \item Name : DpgenRf1, DpgenRf1r0 -- Register File Macro-Generator + \item Description : Generates a register file of \verb-regNumber- words of \verb-n- bits without decoder named \verb-modelname-. + \item How it works : + \begin{itemize} + \item datain0 and datain1 are the two write busses. Only one is used to actually write the register word, it is selected by the sel signal. + \item when sel is set to zero datain0 is used to write the register word, otherwise it will be datain1 + \item selr, selw : this register file have no decoder, so selr have a bus width equal to \verb-regNumber-. One bit for each word + \item The DpgenRf1r0 variant differs from the DpgenRf1 in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item ckok : clock signal (input, 1 bit) + \item sel : select the write bus (input, 1 bit) + \item selr : the decoded read address (input, \verb-regNumber- bits) + \item selw : the decoded write address (input, \verb-regNumber- bits) + \item datain0 : first write bus (input, \verb-n- bits) + \item datain1 : second write bus (input, \verb-n- bits) + \item dataout : read bus (output, \verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the words (even, between 2 and 64) + \item nword : Defines the number of the words (even, between 4 and 32) + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + + def Interface ( self ) : + + self.nbit = self._param['nbit'] + self.nword = self._param['nword'] + + self._ck = LogicIn ( "ck", 1 ) + self._sel = LogicIn ( "sel", 1 ) + + self._selr = LogicIn ( "selr", self.nword ) + self._selw = LogicIn ( "selw", self.nword ) + self._datain0 = LogicIn ( "datain0", self.nbit ) + self._datain1 = LogicIn ( "datain1", self.nbit ) + self._dataout = LogicOut ( "dataout", self.nbit ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenRf1' + , param = { 'nword' : self.nword + , 'nbit' : self.nbit + } + , map = { 'ck' : self._ck + , 'sel' : self._sel + , 'selr' : self._selr + , 'selw' : self._selw + , 'datain0' : self._datain0 + , 'datain1' : self._datain1 + , 'dataout' : self._dataout + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenrf1d.tex b/stratus1/doc/man_dpgenrf1d.tex new file mode 100644 index 00000000..705cdd9b --- /dev/null +++ b/stratus1/doc/man_dpgenrf1d.tex @@ -0,0 +1,81 @@ +\begin{itemize} + \item Name : DpgenRf1d, DpgenRf1dr0 -- Register File with Decoder Macro-Generator + \item Description : Generates a register file of \verb-regNumber- words of \verb-n- bits with decoder named \verb-modelname-. + \item How it works : + \begin{itemize} + \item datain0 and datain1 are the two write busses. Only one is used to actually write the register word, it is selected by the sel signal. + \item when sel is set to zero datain0 is used to write the register word, otherwise it will be datain1 + \item adr, adw : the width (Y) of those signals is computed from regNumber : \verb-Y = log2(regNumber)- + \item wen and ren : write enable and read enable, allows reading and writing when sets to \verb-one- + \item The DpgenRf1dr0 variant differs from the DpgenRf1d in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item ck : clock signal (input, 1 bit) + \item sel : select the write bus (input, 1 bit) + \item wen : write enable (input, 1 bit) + \item ren : read enable (input, 1 bit) + \item adr : the read address (input, \verb-Y- bits) + \item adw : the write address (input, \verb-Y- bits) + \item datain0 : first write bus (input, \verb-n- bits) + \item datain1 : second write bus (input, \verb-n- bits) + \item dataout : read bus (output, \verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the words (even, between 2 and 64) + \item nword : Defines the number of the words (even, between 6 and 32) + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + + def Interface ( self ) : + self.nbit = self._param['nbit'] + self.nword = self._param['nword'] + + adrange = 2 + if self.nword > 4 : adrange = 3 + if self.nword > 8 : adrange = 4 + if self.nword > 16 : adrange = 5 + + self._ck = LogicIn ( "ck", 1 ) + self._sel = LogicIn ( "sel", 1 ) + self._wen = LogicIn ( "wen", 1 ) + self._ren = LogicIn ( "ren", 1 ) + + self._adr = LogicIn ( "adr", adrange ) + self._adw = LogicIn ( "adw", adrange ) + self._datain0 = LogicIn ( "datain0", self.nbit ) + self._datain1 = LogicIn ( "datain1", self.nbit ) + self._dataout = LogicOut ( "dataout", self.nbit ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenRf1d' + , param = { 'nword' : self.nword + , 'nbit' : self.nbit + } + , map = { 'ck' : self._ck + , 'sel' : self._sel + , 'wen' : self._wen + , 'ren' : self._ren + , 'adr' : self._adr + , 'adw' : self._adw + , 'datain0' : self._datain0 + , 'datain1' : self._datain1 + , 'dataout' : self._dataout + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenrom2.tex b/stratus1/doc/man_dpgenrom2.tex new file mode 100644 index 00000000..15c9d746 --- /dev/null +++ b/stratus1/doc/man_dpgenrom2.tex @@ -0,0 +1,48 @@ +\begin{itemize} + \item Name : DpgenRom2 -- 2 words ROM Macro-Generator + \item Description : Generates a \verb-n- bits 2 words optimized ROM named \verb-modelname-. + \item Terminal Names : + \begin{itemize} + \item sel0 : address of the value (input, 1 bit) + \item q : the selected word (output, \verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item val0 : Defines the first word + \item val1 : Defines the second word + \end{itemize} + \item Behavior : +\begin{verbatim} +q <= WITH sel0 SELECT + contsVal0 WHEN B"0", + constVal1 WHEN B"1"; +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._sel0 = LogicIn ( "sel0", 1 ) + + self._q = LogicOut ( "dataout", 4 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenRom2' + , param = { 'val0' : "0b1010" + , 'val1' : "0b1100" + , 'nbit' : 4 + } + , map = { 'sel0' : self._sel0 + , 'q' : self._q + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenrom4.tex b/stratus1/doc/man_dpgenrom4.tex new file mode 100644 index 00000000..ddec0d67 --- /dev/null +++ b/stratus1/doc/man_dpgenrom4.tex @@ -0,0 +1,56 @@ +\begin{itemize} + \item Name : DpgenRom4 -- 4 words ROM Macro-Generator + \item Description : Generates a \verb-n- bits 4 words optimized ROM named \verb-modelname-. + \item Terminal Names : + \begin{itemize} + \item sel1 : upper bit of the address of the value (input, 1 bit) + \item sel0 : lower bit of the address of the value (input, 1 bit) + \item q : the selected word (output, \verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item val0 : Defines the first word + \item val1 : Defines the second word + \item val0 : Defines the third word + \item val1 : Defines the fourth word + \end{itemize} + \item Behavior : +\begin{verbatim} +q <= WITH sel1 & sel0 SELECT contsVal0 WHEN B"00", + contsVal1 WHEN B"01", + contsVal2 WHEN B"10", + constVal3 WHEN B"11"; +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._sel0 = LogicIn ( "sel0", 1 ) + self._sel1 = LogicIn ( "sel1", 1 ) + + self._q = LogicOut ( "dataout", 4 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenRom4' + , param = { 'val0' : "0b1010" + , 'val1' : "0b1100" + , 'val2' : "0b1111" + , 'val3' : "0b0001" + , 'nbit' : 4 + } + , map = { 'sel0' : self._sel0 + , 'sel1' : self._sel1 + , 'q' : self._q + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgensff.tex b/stratus1/doc/man_dpgensff.tex new file mode 100644 index 00000000..5e229161 --- /dev/null +++ b/stratus1/doc/man_dpgensff.tex @@ -0,0 +1,50 @@ +\begin{itemize} + \item Name : DpgenSff -- Static Flip-Flop Macro-Generator + \item Description : Generates a n bits static flip-flop named \verb-modelname-. The two latches of this flip-flop are static, i.e. each one is made of two interters looped together. + \item How it works : + \begin{itemize} + \item when wen is set to \verb-one-, enables the writing of the flip-flop + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item wen : write enable (1 bit) + \item ck : clock signal (1 bit) + \item i0 : data input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._ck = LogicIn ( "ck", 1 ) + self._wen = LogicIn ( "wen", 1 ) + self._in = LogicIn ( "in", 4 ) + + self._out = LogicOut ( "out", 4 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenSff' + , param = { 'nbit' : 4 } + , map = { "wen" : self._wen + , "ck" : self._ck + , "i0" : self._in + , "q" : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgensfft.tex b/stratus1/doc/man_dpgensfft.tex new file mode 100644 index 00000000..c87cce5f --- /dev/null +++ b/stratus1/doc/man_dpgensfft.tex @@ -0,0 +1,58 @@ +\begin{itemize} + \item Name : DpgenSfft -- Static Flip-Flop with Scan-Path Macro-Generator + \item Description : Generates a n bits static flip-flop with scan-path named \verb-modelname-. The two latches of this flip-flop are static i.e. each one is made of two interters looped togethers. + \item How it works : + \begin{itemize} + \item scan : when set to \verb-one- enables the scan-path mode. Note that in scan-path mode, the wen signal is not effective + \item scin : the input of the scan-path. This terminal is different from \verb-i0[0]-. The scout is verb-q[N-i1] (in the following example this is \verb-q[31]-) + \item when wen is set to \verb-one- enables the writing of the flip-flop + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item scan : scan-path mode (input, 1 bit) + \item scin : scan path in (input, 1 bit) + \item wen : write enable (1 bit) + \item ck : clock signal (1 bit) + \item i0 : data input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} +% \item Behavior : +% \begin{verbatim} +% \end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._scan = LogicIn ( "scin", 1 ) + self._scin = LogicIn ( "scan", 1 ) + self._ck = LogicIn ( "ck", 1 ) + self._wen = LogicIn ( "wen", 1 ) + self._in = LogicIn ( "in", 4 ) + + self._out = LogicOut ( "out", 4 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenSfft' + , param = { 'nbit' : 4 } + , map = { "wen" : self._wen + , "ck" : self._ck + , "scan" : self._scan + , "scin" : self._scin + , "i0" : self._in + , "q" : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenshift.tex b/stratus1/doc/man_dpgenshift.tex new file mode 100644 index 00000000..22d67640 --- /dev/null +++ b/stratus1/doc/man_dpgenshift.tex @@ -0,0 +1,54 @@ +\begin{itemize} + \item Name : DpgenShift -- Shifter Macro-Generator + \item Description : Generates a \verb-n- bits shifter named \verb-modelname-. + \item How it works : + \begin{itemize} + \item if the \verb-op[0]- signal is set to \verb-one-, performs a right shift, performs a left shift otherwise. + \item if the \verb-op[1]- signal is set to \verb-one-, performs an arithmetic shift (only meaningful in case of a right shift). + \item \verb-shamt- specifies the shift amount. The width of this signal (\verb-Y-) is computed from the operator's width : \verb-Y = ceil(log2(n)) -- 1 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item op : select the kind of shift (input, 2 bits) + \item shamt : the shift amount (input, \verb-Y- bits) + \item i : value to shift (input, \verb-n- bits) + \item o : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._instop = LogicIn ( "instop", 2 ) + + self._instshamt = LogicIn ( "instshamt", 2 ) + + self._insti = LogicIn ( "insti", 4 ) + + self._insto = LogicOut ( "insto", 4 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenShifter' + , param = { 'nbit' : 4 } + , map = { 'op' : self._instop + , 'shamt' : self._instshamt + , 'i' : self._insti + , 'o' : self._insto + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenshrot.tex b/stratus1/doc/man_dpgenshrot.tex new file mode 100644 index 00000000..5d6a8f7a --- /dev/null +++ b/stratus1/doc/man_dpgenshrot.tex @@ -0,0 +1,55 @@ +\begin{itemize} + \item Name : DpgenShrot -- Shift/Rotation Macro-Generator + \item Description : Generates a \verb-n- bits shift/rotation operator named \verb-modelname-. + \item How it works : + \begin{itemize} + \item if the \verb-op[0]- signal is set to \verb-one-, performs a right shift/rotation , otherwise left shift/rotation occurs. + \item if the \verb-op[1]- signal is set to \verb-one-, performs an arithmetic shift (only meaningful in case of a right shift). + \item if the \verb-op[2]- signal is set to \verb-one-, performs a rotation, otherwise performs a shift.. + \item \verb-shamt- specifies the shift amount. The width of this signal (\verb-Y-) is computed from the operator's width : \verb-Y = ceil(log2(n)) -- 1 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item op : select the kind of shift/rotation (input, 3 bits) + \item shamt : the shift amount (input, \verb-Y- bits) + \item i : value to shift (input, \verb-n- bits) + \item o : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \end{itemize} +% \item Behavior : +%\begin{verbatim} +%\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._rotop = LogicIn ( "rotop", 3 ) + + self._instshamt = LogicIn ( "instshamt", 3 ) + + self._insti = LogicIn ( "insti", 8 ) + + self._insto = LogicOut ( "insto", 8 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenShrot' + , param = { 'nbit' : 8 } + , map = { 'op' : self._rotop + , 'shamt' : self._instshamt + , 'i' : self._insti + , 'o' : self._insto + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenxnor2.tex b/stratus1/doc/man_dpgenxnor2.tex new file mode 100644 index 00000000..318d56ae --- /dev/null +++ b/stratus1/doc/man_dpgenxnor2.tex @@ -0,0 +1,48 @@ +\begin{itemize} + \item Name : DpgenXnor2 -- Xnor2 Macro-Generator + \item Description : Generates a \verb-n- bits two inputs XNOR with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item nq : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= not ( i0 xor i1 ) +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenXnor2' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenxnor2mask.tex b/stratus1/doc/man_dpgenxnor2mask.tex new file mode 100644 index 00000000..f884e9f3 --- /dev/null +++ b/stratus1/doc/man_dpgenxnor2mask.tex @@ -0,0 +1,55 @@ +\begin{itemize} + \item Name : DpgenXnor2mask -- Programmable Mask Macro-Generator + \item Description : Generates a \verb-n- bits conditionnal XNOR mask named \verb-modelname-. + \item How it works : + \begin{itemize} + \item if the \verb-cmd- signal is set to \verb-zero-, the mask is NOT applied, so the whole operator behaves like an inverter. + \item if the \verb-cmd- signal is set to \verb-one-, the mask is applied, the output is the \emph{complemented} result of the input value \emph{XORed} with the mask (suplied by \verb-constVal-). + \item The constant \verb-constVal- is given to the macro-generator call, therefore the value cannot be changed afterward : it's hard wired in the operator. + \item A common error is to give a real constant for the \verb-constVal- argument. Be aware that it is a character string. + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item cmd : mask control ( 1 bit ) + \item i0 : input ( \verb-n- bits ) + \item nq : output ( \verb-n- bits ) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item const : Defines the constant + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= WITH cmd SELECT not(i0) WHEN '0', + not(i0 xor X"0000FFFF") WHEN '1'; +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in = LogicIn ( "in", 8 ) + self._cmd = LogicIn ( "cmd", 1 ) + + self._out = LogicOut ( "out", 8 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenXnor2mask' + , param = { 'nbit' : 8 + , 'const' : "0b000111" + } + , map = { 'i0' : self._in + , 'cmd' : self._cmd + , 'nq' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_dpgenxor2.tex b/stratus1/doc/man_dpgenxor2.tex new file mode 100644 index 00000000..f1244f59 --- /dev/null +++ b/stratus1/doc/man_dpgenxor2.tex @@ -0,0 +1,48 @@ +\begin{itemize} + \item Name : DpgenXor2 -- Xor2 Macro-Generator + \item Description : Generates a \verb-n- bits two inputs XOR with an output power of \verb-drive- named \verb-modelname-. + \begin{itemize} + \item Valid drive are : 1 or 4 + \end{itemize} + \item Terminal Names : + \begin{itemize} + \item i0 : input (\verb-n- bits) + \item i1 : input (\verb-n- bits) + \item q : output (\verb-n- bits) + \item vdd : power + \item vss : ground + \end{itemize} + \item Parameters : Parameters are given with a map called \verb-param-. + \begin{itemize} + \item nbit : Defines the size of the generator + \item drive (optional) : Defines the output power of the gates\\If this parameter is not defined, the \verb-drive- is the smallest one permitted. + \end{itemize} + \item Behavior : +\begin{verbatim} +nq <= i0 xor i1 +\end{verbatim} + \item Example : +\begin{verbatim} +class myClass ( Model ) : + def Interface ( self ) : + self._in0 = LogicIn ( "in0", 32 ) + self._in1 = LogicIn ( "in1", 32 ) + + self._out = LogicOut ( "out", 32 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + Inst ( 'DpgenXor2' + , param = { 'nbit' : 32 } + , map = { 'i0' : self._in0 + , 'i1' : self._in1 + , 'q' : self._out + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +\end{verbatim} +\end{itemize} diff --git a/stratus1/doc/man_example.tex b/stratus1/doc/man_example.tex new file mode 100644 index 00000000..c2baee39 --- /dev/null +++ b/stratus1/doc/man_example.tex @@ -0,0 +1,63 @@ +\subsubsection{Addaccu circuit} + +\begin{figure}[h!] +\centering +\includegraphics[width=.9\textwidth]{images/add1.png} +\end{figure} + +\newpage + +\subsubsection{Data-path} + +\begin{figure}[h!] +\centering +\includegraphics[width=.9\textwidth]{images/add2.png} +\end{figure} + +\subsubsection{Description of the circuit with \emph{Stratus}} + +\begin{figure}[hbp] +\centering +\includegraphics[width=1.2\textwidth]{images/addaccu.png} +\end{figure} + +\newpage + +\subsubsection{Creation of the circuit} + +\begin{figure}[hbp] +\centering +\includegraphics[width=1.3\textwidth]{images/test.png} +\end{figure} + +%\newpage + +\subsubsection{How to execute the file} + +\begin{verbatim} +python test.py -n 4 +\end{verbatim} +\indent or : +\begin{verbatim} +chmod u+x test.py +./test -n 4 +\end{verbatim} + +\subsubsection{The editor} + +The method \verb-View- permits to open an editor in which one can see the cell being created as shown in the picture below. +\begin{figure}[hbp] +\centering +\includegraphics[width=1\textwidth]{images/editor.png} +\end{figure} + + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Stratus}}{}{Stratus}{secstratus} +\hyperref[ref]{\emph{Model}}{}{Model}{secmodel} +\hyperref[ref]{\emph{Param}}{}{Param}{secparam} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{Place and Route}}{}{Place and Route}{secroute} +\hyperref[ref]{\emph{Facilities}}{}{Facilities}{secfacilities} diff --git a/stratus1/doc/man_extend.tex b/stratus1/doc/man_extend.tex new file mode 100644 index 00000000..4eab429e --- /dev/null +++ b/stratus1/doc/man_extend.tex @@ -0,0 +1,52 @@ +\subsubsection{Name} + +Extend -- Extention of nets + +\subsubsection{Synopsys} + +\begin{verbatim} +extendA = Signal ( "extend_a", 32 ) + +extendA <= netA.Extend ( 32, 'zero' ) +\end{verbatim} + +\subsubsection{Description} + +This method creates a net which is an extension of the net which it is applied to. The number given as parameter has to be greater than the arity of the net. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-n- : the number which is the arity of the net + \item \verb-type- : the type of the extension + \begin{itemize} + \item 'zero' : the extension nets are set to zero + \item 'one' : the extension nets are set to one + \item 'signed' : the extension nets are set thanks to the value of the msb bit + \end{itemize} +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +temp = Signal ( "temp", 5 ) +tempExt = Signal ( "temp_ext", 8 ) + +tempExt <= temp.Extand ( 8, 'one' ) +\end{verbatim} + +\indent The arity of the net \verb-tempExt- is 8 and 3 MSB of the net are "1". + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Extend :-\\\verb-the net can not be extended to n bits, it's arity is already m.-\\The number one wants must be greater than the arity of the net. Otherwise, the net can not be extended. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Nets}}{}{Nets}{secnet} +\hyperref[ref]{\emph{Alias}}{}{Alias}{secalias} +\hyperref[ref]{\emph{Cat}}{}{Cat}{seccat} diff --git a/stratus1/doc/man_fill_cell.tex b/stratus1/doc/man_fill_cell.tex new file mode 100644 index 00000000..6c4c5b8b --- /dev/null +++ b/stratus1/doc/man_fill_cell.tex @@ -0,0 +1,44 @@ +\subsubsection{Name} + +FillCell -- Automatic placement of ties. + +\subsubsection{Synopsys} + +\begin{verbatim} +FillCell ( cell ) +\end{verbatim} + +\subsubsection{Description} + +This function places automatically ties. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-cell- : the cell which the fonction is applied to +\end{itemize} + +%\subsubsection{Example} +% +%\begin{verbatim} +%FillCell ( core ) +%\end{verbatim} +% +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] FillCell : Given cell doesn't exist.-\\The argument is wrong. Check if one has created the cell correctly. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} diff --git a/stratus1/doc/man_generators.tex b/stratus1/doc/man_generators.tex new file mode 100644 index 00000000..5a511c48 --- /dev/null +++ b/stratus1/doc/man_generators.tex @@ -0,0 +1,82 @@ +\subsubsection{Description} + +One can create a generator and instantiate it in another generator.\\ +\indent To do that, the name given when instantiating the generator must have the form : "file\_name.class\_name".\\ + +\indent Note that if the two generators are not in the same directory, the directory of the generator to be instantiated has to be added in the CRL\_CATA\_LIB environment variable. + +\subsubsection{Example} + +\begin{itemize} + \item File describing the generator which is going to instanciated later : +\end{itemize} + +\begin{verbatim} +#!/usr/bin/python + +from stratus import * + +class class_function ( Model ) : + + def Interface ( self ) : + self.n = self._param['nbit'] + + self._A = LogicIn ( "a", self.n ) + self._B = LogicIn ( "b", self.n ) + self._C = LogicIn ( "c", self.n ) + + self._S = LogicOut ( "s", self.n ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + self._S <= ( self._A | self._B ) & self._C +\end{verbatim} + +\begin{itemize} + \item File instanciating the generator : +\end{itemize} + +\begin{verbatim} +#!/usr/bin/python + +from stratus import * + +class mycell ( Model ) : + + def Interface ( self ) : + self._in1 = LogicIn ( "in1", 4 ) + self._in2 = LogicIn ( "in2", 4 ) + self._in3 = LogicIn ( "in3", 4 ) + + self._out = LogicOut ( "out", 4 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + temp = Signal ( "temp", 4 ) + + Inst ( "myfunc.class_function" + , param = { 'nbit' : 4 } + , map = { 'a' : self._in1 + , 'b' : self._in2 + , 'c' : self._in3 + , 's' : temp + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self._out <= ~temp +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Inst : the model ... does not exist.-\\\verb-Check CRL_CATA_LIB.-\\One has to check the environment variable because the model is not found. +\end{itemize} + +\input{see_also} diff --git a/stratus1/doc/man_inst.tex b/stratus1/doc/man_inst.tex new file mode 100644 index 00000000..f2292d3c --- /dev/null +++ b/stratus1/doc/man_inst.tex @@ -0,0 +1,56 @@ +\subsubsection{Name} + +Inst -- Creation of instances + +\subsubsection{Synopsys} + +\begin{verbatim} +Inst ( model + , name + , param + , map + ) +\end{verbatim} + +\subsubsection{Description} + +Instantiation of an instance. The type of the instance is given by the \verb-model- parameter. The connexions are made thanks to the \verb-map- parameters. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-Model- : Name of the mastercell of the instance to create (mandatory argument) + \item \verb-name- : Name of the instance (optional)\\ +When this argument is not defined, the instance has a name created by default. This argument is usefull when one wants to create a layout as well. Indeed, the placement of the instances is much easier when the conceptor has chosen himself the name f the instances. + \item \verb-param- : Arguments of the mastercell (optional : only for mastercells which require it) + \item \verb-map- : Connexions in order to make the netlist\\ +\end{itemize} +\indent \verb-param- and \verb-map- are dictionnaries as shown in the example below. + +\subsubsection{Example} + +\begin{verbatim} +Inst ( 'DpgenAnd2' + , param = { 'nbit' : 4 + } + , map = { 'i0' : in0 + , 'i1' : in1 + , 'q' : out + , 'vdd' : vdd + , 'vss' : vss + } + ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-Error in Inst : the model Model does not exist.-\\\verb-Check CRL_CATA_LIB.-\\Either one has made a mistake in the name of the model, either the environment variable is not correct. + \item \verb-Error in Inst : port does not exist in model Model.-\\One port in map is not correct. + \item \verb-Error in Inst : one input net is not dimensionned.-\\The size of the output nets is automatically calculated bus the input nets must be dimensionned before being connected. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} diff --git a/stratus1/doc/man_library.tex b/stratus1/doc/man_library.tex new file mode 100644 index 00000000..de0dcd4d --- /dev/null +++ b/stratus1/doc/man_library.tex @@ -0,0 +1,68 @@ +\subsubsection{Description} + +All the cells that can be instantiated are listed below.\\ +\indent These cells are generators which are proportionned thanks to parameters. + +\subsubsection{List} + +\begin{itemize} + \item \verb-And2- : \verb-q <= i0 & i1- + \item \verb-And3- : \verb-q <= i0 & i1 & i2- + \item \verb-And4- : \verb-q <= i0 & i1 & i2 & i3- + \item \verb-Nand2- : \verb-nq <= ~ ( i0 & i1 )- + \item \verb-Nand3- : \verb-nq <= ~ ( i0 & i1 & i2 )- + \item \verb-Nand4- : \verb-nq <= ~ ( i0 & i1 & i2 & i3 )- + \item \verb-Or2- : \verb-q <= i0 & i1- + \item \verb-Or3- : \verb-q <= i0 & i1 & i2- + \item \verb-Or4- : \verb-q <= i0 & i1 & i2 & i3- + \item \verb-Nor2- : \verb-nq <= ~ ( i0 & i1 )- + \item \verb-Nor3- : \verb-nq <= ~ ( i0 & i1 & i2 )- + \item \verb-Nor4- : \verb-nq <= ~ ( i0 & i1 & i2 & i3 )- + \item \verb-Inv- : \verb-nq <= ~ i- + \item \verb-Buf- : \verb-q <= i- + \item \verb-Xor2- : \verb-q <= i0 ^ i1- + \item \verb-Nxor2- : \verb-nq <= ~ ( i0 ^ i1 )- + \item \verb-Zero- : \verb-nq <= '0'- + \item \verb-One- : \verb-q <= '1'- + \item \verb-Halfadder- : \verb-sout <= a ^ b- and \verb-cout <= a & b- + \item \verb-Fulladder- : \verb-sout <= a ^ b ^ cin-\\\indent and \verb-cout <= ( a & b ) | ( a & cin ) | ( b & cin )- + \item \verb-Sff- : \verb-if RISE ( ck ) : q <= i- +\end{itemize} + +\subsubsection{Parameters} + +The parameter \verb-'nbit'- gives the size of the generator. It is given through the dictionnary named \verb-param- (the default value is 1). + +\subsubsection{Mapping file} + +In order to map the virtual library, on has to write a .xml file which makes correspond models and interfaces. Note that the interfaces of the cells must be the same (except for the names of the ports). Otherwise, one has to create .vst files in order to make the interfaces match.\\ +\indent By default, the mapping is done with sxlib library. There is an example of the .xml file below.\\ +\indent The environment variable used to point the right file is \verb-STRATUS_MAPPING_NAME-. +\begin{figure}[hbp] +\centering +\includegraphics[width=1.3\textwidth]{images/xml.png} +\end{figure} + +\subsubsection{Example} + +\begin{verbatim} +Inst ( 'And2' + , param = { 'nbit' : 4 } + , map = { 'i0' : A + , 'i1' : B + , 'q' : S + , 'vdd' : vdd + , 'vss' : vss + } + ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Inst : the model ... does not exist.-\\\verb-Check CRL_CATA_LIB.-\\The model of the cell has not been found. One has to check the environment variable. + \item \verb-[Stratus ERROR] Virtual library : No file found in order to parse.-\\\verb-Check STRATUS_MAPPING_NAME.-\\The mapping faile is not given in the environment variable. +\end{itemize} + +\input{see_also} diff --git a/stratus1/doc/man_model.tex b/stratus1/doc/man_model.tex new file mode 100644 index 00000000..b5ce12ff --- /dev/null +++ b/stratus1/doc/man_model.tex @@ -0,0 +1,47 @@ +\subsubsection{Name} + +Model -- Master class + +\subsubsection{Description} + +Every cell made is a class herited from class \verb-Model-.\\ +\indent Some methods have to be created, like \verb-Interface-, \verb-Netlist- ... Some methods are inherited from the class \verb-Model-. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-name- : The name of the cell (which is the name of the files which will be created) + \item \verb-param- : A dictionnary which gives all the parameters usefull in order to create the cell +\end{itemize} + +\subsubsection{Methods} + +Methods of class \verb-Model- are listed below : +\begin{itemize} + \item \verb-View- : Opens/Refreshes the editor in order to see the created layout + \item \verb-Quit- : Finishes a cell without saving + \item \verb-Save- : Saves the created cell\\If several cells have been created, they are all going to be saved in separated files\\ +\end{itemize} + +Some of those methods have to be defined in order to create a new cell : +\begin{itemize} + \item \verb-Interface- : Description of the external ports of the cell + \item \verb-Netlist- : Description of the netlist of the cell + \item \verb-Layout- : Description of the layout of the cell + \item \verb-Vbe- : Description of the behavior of the cell + \item \verb-Pattern- : Description of the patterns in order to test the cell +\end{itemize} + +\subsubsection{Example} + +You can see a concrete example at : \hyperref[ref]{\emph{A concrete example}}{}{Example}{secexample} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Stratus}}{}{Stratus}{secstratus} +\hyperref[ref]{\emph{Param}}{}{Param}{secparam} +\hyperref[ref]{\emph{Example}}{}{Example}{secexample} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{Place and Route}}{}{Place and Route}{secroute} +\hyperref[ref]{\emph{Facilities}}{}{Facilities}{secfacilities} diff --git a/stratus1/doc/man_mux.tex b/stratus1/doc/man_mux.tex new file mode 100644 index 00000000..441b37d4 --- /dev/null +++ b/stratus1/doc/man_mux.tex @@ -0,0 +1,131 @@ +\subsubsection{Name} + +Mux -- Easy way to instantiate a multiplexor + +\subsubsection{Synopsys} + +\begin{verbatim} +netOut <= netCmd.Mux ( arg ) +\end{verbatim} + +\subsubsection{Description} + +This method is a method of net. The net which this method is applied to is the command of the multiplexor. The nets given as parameters are all the input nets. This method returns a net : the output net.\\ +There are two ways to describe the multiplexor : the argument \verb-arg- can be a list or a dictionnary.\\ +\indent Note that it is possible to change the generator instanciated with the \verb-SetMux- method. + +\subsubsection{Parameters} + +\begin{itemize} + \item List :\\ + \indent For each value of the command, the corresponding net is specified. All values must be specified.\\ + \indent For example : + \begin{verbatim} +out <= cmd.mux ( [in0, in1, in2, in3] ) + \end{verbatim} + \indent The net out is then initialised like this : + \begin{verbatim} +if cmd == 0 : out <= in0 +if cmd == 1 : out <= in1 +if cmd == 2 : out <= in2 +if cmd == 3 : out <= in3 + \end{verbatim} + \item Dictionnary :\\ + \indent A dictionnary makes the correspondance between a value of the command and the corresponding net.\\ + \indent For example : + \begin{verbatim} +out <= cmd.mux ( {"0" : in0, "1" : in1, "2" : in2, "3" : in3} ) + \end{verbatim} + \indent This initialisation corresponds to the one before. + \indent Thanks to the use of a dictionnary, the connections can be clearer : + \begin{itemize} + \item \verb-'default'-: This key of the dictionnary corresponds to all the nets that are not specified\\ + For example : + \begin{verbatim} +out <= cmd.mux ( {"0" : in0, "default" : in1} ) + \end{verbatim} + This notation corresponds to : + \begin{verbatim} +if cmd == 0 : out <= in0 +else : out <= in1 + \end{verbatim} + Note that if there is no \verb-'default'- key specified and that not all the nets are specified, the non specified nets are set to 0. + \item \verb-#- and \verb-?- : When a key of the dictionnary begins with \verb-#-, the number after the \verb-#- has to be binary and each ? in the number means that this bit is not precised\\ + For example : + \begin{verbatim} +out <= cmd.mux ( {"#01?" : in0, "default" : in1} ) + \end{verbatim} + This notation corresponds to : + \begin{verbatim} +if cmd in ( 2, 3 ) : out <= in0 +else : out <= in1 + \end{verbatim} + \item \verb-,- and \verb"-" : When keys contains thoses symbols, it permits to enumerate intervals\\ + For example : + \begin{verbatim} +out <= cmd.mux ( {"0,4" : in0, "1-3,5" : in1} ) + \end{verbatim} + This notation corresponds to : + \begin{verbatim} +if cmd in ( 0, 4 ) : out <= in0 +elif cmd in ( 1, 2, 3, 5) : out <= in1 +else : out <= 0 + \end{verbatim} + \end{itemize} +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = LogicIn ( "a", 4 ) + self.B = LogicIn ( "b", 4 ) + self.C = LogicIn ( "c", 4 ) + self.D = LogicIn ( "d", 4 ) + + self.Cmd1 = LogicIn ( "cmd1", 2 ) + self.Cmd2 = LogicIn ( "cmd2", 4 ) + + self.S1 = LogicOut ( "s1", 4 ) + self.S2 = LogicOut ( "s2", 4 ) + + self.Vdd = VddIn ( "vdd" ) + self.Vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S1 <= self.Cmd1.Mux ( [sefl.A, self.B, self.C, self.D] ) + + self.S2 <= self.Cmd2.Mux ( { "0" : self.A + , "1,5-7" : self.B + , "#1?1?" : self.C + , "default" : self.D + } ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Mux : all the nets must have the same lenght.-\\All the input nets pust have the same lenght. + \item \verb-[Stratus ERROR] Mux : there are no input nets.-\\The input nets seem to have been forgotten. + \item \verb-[Stratus ERROR] Mux : wrong argument type.-\\The connections of the buses are not described by a list nor a dictionnary. + \item \verb-[Stratus ERROR] Mux :-\\\verb-the number of nets does not match with the lenght of the command.-\\When using a list, the number of nets has to correspond to the number of possible values of the command. + \item \verb-[Stratus ERROR] Mux : wrong key.-\\One of the key of the dictionnary is not un number, neither a list or an interval. + \item \verb-[Stratus ERROR] Mux :-\\\verb-when an interval is specified, the second number of the interval-\\\verb-must be greater than the first one.-\\When creating an interval with "-", the second number has to be greater than the first one. + \item \verb-[Stratus ERROR] Mux :-\\\verb-the binary number does not match with the lenght of the command.-\\When using the \verb-#- notation, each digit of the binary number corresponds to a wire of the cmd. The leghts have to correspond. + \item \verb-[Stratus ERROR] Mux : after #, the number has to be binary.-\\When using the \verb-#- notation, the number has to be binary : one can use 0, 1 or ?. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a shifter}}{}{Shifter}{secshift} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} diff --git a/stratus1/doc/man_net.tex b/stratus1/doc/man_net.tex new file mode 100644 index 00000000..9a85c004 --- /dev/null +++ b/stratus1/doc/man_net.tex @@ -0,0 +1,57 @@ +\subsubsection{Name} + +LogicIn, LogicOut ... -- Creation of nets + +\subsubsection{Synopsys} + +\begin{verbatim} +netA = LogicIn ( "a", 4 ) +\end{verbatim} + +\subsubsection{Description} + +How to create and use nets. + +\subsubsection{Nets} + +Differents kind of nets are listed below : +\begin{itemize} + \item \verb-LogicIn- : Creation of an input port + \item \verb-LogicOut- : Creation of an output port + \item \verb-LogicInOut- : Creation of an inout port + \item \verb-LogicUnknown- : Creation of an input/output port which direction is not defined + \item \verb-TriState- : Creation of a tristate port + \item \verb-CkIn- : Creation of a clock port + \item \verb-VddIn- : Creation of the vdd alimentation + \item \verb-VssIn- : Creation of the vss alimentation + \item \verb-Signal- : Creation of an internal net +\end{itemize} + +\subsubsection{Parameters} + +All kind of constructors have the same parameters : +\begin{itemize} + \item \verb-name- : the name of the net (mandatory argument) + \item \verb-arity- : the arity of the net (mandatory argument) + \item \verb-indice- : for buses only : the LSB bit (optional argument : set to 0 by default) +\end{itemize} + +\indent Only \verb-CkIn-, \verb-VddIn- and \verb-VssIn- do not have the same parameters : there is only the \verb-name- parameter (they are 1 bit nets). + +\subsubsection{Example} + +You can see a concrete example at : \hyperref[ref]{\emph{A concrete example}}{}{Example}{secexample} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-Error in LogicIn :-\\\verb-the lenght of the net must be a positive value.-\\One can not create a net with a negative lenght. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Alias}}{}{Alias}{secalias} +\hyperref[ref]{\emph{Extand}}{}{Extand}{secextend} +\hyperref[ref]{\emph{Cat}}{}{Cat}{seccat} diff --git a/stratus1/doc/man_pads.tex b/stratus1/doc/man_pads.tex new file mode 100644 index 00000000..d4d83766 --- /dev/null +++ b/stratus1/doc/man_pads.tex @@ -0,0 +1,51 @@ +\subsubsection{Name} + +PadNorth, PadSouth, PadEast, PasWest -- Placement of pads at the periphery of the cell + +\subsubsection{Synopsys} + +\begin{verbatim} +PadNorth ( args ) +\end{verbatim} + +\subsubsection{Description} + +These functions place the pads given as arguments at the given side of the cell (PadNorth : up north, PadSouth : down south ...). + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-args- : List of pads to be placed +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +PadSouth ( self.p_cin, self.p_np, self.p_ng, self.p_vssick0 + , self.p_vddeck0, self.p_vsseck1, self.p_vddeck1, self.p_cout + , self.p_y[0], self.p_y[1], self.p_y[2] + ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PadNorth : not enough space for all pads.-\\The abutment box is not big enough in order to place all the pads. Maybe one could put pads on other faces of the cell. + \item \verb-[Stratus ERROR] PadNorth : one instance doesn't exist.-\\One of the pads given as arguments does not exist + \item \verb-[Stratus ERROR] PadNorth : one argument is not an instance.-\\One of the pads is not one of the pads of the cell. + \item \verb-[Stratus ERROR] PadNorth : the instance ins is already placed.-\\One is tryng to place a pad twice. + \item \verb-[Stratus ERROR] PadNorth : pad ins must be closer to the center.-\\The pad name ins must ben put closer to the center in order to route the cell +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} diff --git a/stratus1/doc/man_param.tex b/stratus1/doc/man_param.tex new file mode 100644 index 00000000..1f9045ad --- /dev/null +++ b/stratus1/doc/man_param.tex @@ -0,0 +1,50 @@ +\subsubsection{Name} + +Param -- How to use parameters + +\subsubsection{Synopsys} + +\begin{verbatim} +nbit, nword = Param ( "n", "w" ) +\end{verbatim} + +\subsubsection{Description} + +This function allows the user to give parameters when creating a cell. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-args- : letters which correspond to letter typed on the shell +\end{itemize} + +\subsubsection{Example} + +When one wants to give values to two parameters, one can type on the shell : +\begin{verbatim} +python test.py -n 4 -w 8 +\end{verbatim} + +The file \verb-test.py- has then to contain : +\begin{verbatim} +nbit, nword = Param ( "n", "w" ) +\end{verbatim} + +You can see a concrete example at : \hyperref[ref]{\emph{A concrete example}}{}{Example}{secexample} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-Error in Param : there is no parameter.-\\The parameters seem to have been forgotten. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Stratus}}{}{Stratus}{secstratus} +\hyperref[ref]{\emph{Model}}{}{Model}{secmodel} +\hyperref[ref]{\emph{Example}}{}{Example}{secexample} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{Place and Route}}{}{Place and Route}{secroute} +\hyperref[ref]{\emph{Facilities}}{}{Facilities}{secfacilities} diff --git a/stratus1/doc/man_place.tex b/stratus1/doc/man_place.tex new file mode 100644 index 00000000..a23e6843 --- /dev/null +++ b/stratus1/doc/man_place.tex @@ -0,0 +1,60 @@ +\subsubsection{Name} + +Place -- Places an instance + +\subsubsection{Synopsys} + +\begin{verbatim} +Place ( ins, sym, x, y ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist-, in order to use the \verb-Place- function. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-x-, \verb-y- : Coordinates of the lower left corner of the abutment box on the instance in the current figure. +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst, NOSYM, 0, 0 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] Place : wrong argument for placement type.-\\The symetry given as argument is not correct. + \item \verb-[Stratus ERROR] PLace : x value must be an integer or a float.-\\One of the coordinates is not correct. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} diff --git a/stratus1/doc/man_place_bottom.tex b/stratus1/doc/man_place_bottom.tex new file mode 100644 index 00000000..eaf93acd --- /dev/null +++ b/stratus1/doc/man_place_bottom.tex @@ -0,0 +1,63 @@ +\subsubsection{Name} + +PlaceBottom -- Places an instance below the "reference instance" + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceBottom ( ins, sym, offset ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use the \verb-PlaceTop- function.\\ + +\indent The top left corner of the abutment box of the instance is placed, after beeing symetrized and/or rotated, toward the bottom left corner of the abutment box of the "reference instance". The newly placed instance becomes the "reference instance". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-offset- (optionnal) : An offset is put between this instance and the reference instance. The value given as argument must be a multiple of PITCH and represents the lenght of the hole between the instances +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceBottom ( myInst2, SYM_Y ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] PlaceBottom : no previous instance.-\\One can use \verb-PlaceTop- only if a reference instance exist. Use a \verb-Place- call before. + \item \verb-[Stratus ERROR] PlaceBottom : wrong argument for placement type.-\\The symetry given as argument is not correct. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} diff --git a/stratus1/doc/man_place_centric.tex b/stratus1/doc/man_place_centric.tex new file mode 100644 index 00000000..a106165d --- /dev/null +++ b/stratus1/doc/man_place_centric.tex @@ -0,0 +1,46 @@ +\subsubsection{Name} + +PlaceCentric -- Placement of an instance in the middle of an abutment box + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceCentric ( ins ) +\end{verbatim} + +\subsubsection{Description} + +This function places an instance in the middle of and abutment box.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use this function. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place +\end{itemize} + +%\subsubsection{Example} +% +%\begin{verbatim} +%PlaceCentric ( core ) +%\end{verbatim} +% +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PlaceCentric: the instance does not exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] PlaceCentric :-\\\verb-the instance's size is greater than this model.-\\The instance must fit in the abutment box. The abutment box may not be big enough. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} diff --git a/stratus1/doc/man_place_glu.tex b/stratus1/doc/man_place_glu.tex new file mode 100644 index 00000000..cbfe1d68 --- /dev/null +++ b/stratus1/doc/man_place_glu.tex @@ -0,0 +1,37 @@ +\subsubsection{Name} + +PlaceGlue -- Automatic placement of non placed instances + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceGlue ( cell ) +\end{verbatim} + +\subsubsection{Description} + +This function places, thanks to the automatic placer Mistral of Coriolis, all the non placed instances of the cell. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-cell- : the cell which the fonction is applied to +\end{itemize} + +%\subsubsection{Example} +% +%\begin{verbatim} +%PlaceGlue ( core ) +%\end{verbatim} +% +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} diff --git a/stratus1/doc/man_place_left.tex b/stratus1/doc/man_place_left.tex new file mode 100644 index 00000000..e44b77a4 --- /dev/null +++ b/stratus1/doc/man_place_left.tex @@ -0,0 +1,63 @@ +\subsubsection{Name} + +PlaceLeft -- Places an instance at the left of the "reference instance" + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceLeft ( ins, sym, offset ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use the \verb-PlaceTop- function.\\ + +\indent The bottom right corner of the abutment box of the instance is placed, after beeing symetrized and/or rotated, toward the bottom left corner of the abutment box of the "reference instance". The newly placed instance becomes the "reference instance". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-offset- (optionnal) : An offset is put between this instance and the reference instance. The value given as argument must be a multiple of PITCH and represents the width of the hole between the instances +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceLeft ( myInst2, NOSYM ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] PlaceLeft : no previous instance.-\\One can use \verb-PlaceTop- only if a reference instance exist. Use a \verb-Place- call before. + \item \verb-[Stratus ERROR] PlaceLeft : wrong argument for placement type.-\\The symetry given as argument is not correct. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} diff --git a/stratus1/doc/man_place_right.tex b/stratus1/doc/man_place_right.tex new file mode 100644 index 00000000..4aab7cff --- /dev/null +++ b/stratus1/doc/man_place_right.tex @@ -0,0 +1,63 @@ +\subsubsection{Name} + +PlaceRight -- Places an instance at the right of the "reference instance" + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceRight ( ins, sym, offset ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use the \verb-PlaceTop- function.\\ + +\indent The bottom left corner of the abutment box of the instance is placed, after beeing symetrized and/or rotated, toward the bottom right corner of the abutment box of the "reference instance". The newly placed instance becomes the "reference instance". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-offset- (optionnal) : An offset is put between this instance and the reference instance. The value given as argument must be a multiple of PITCH and represents the width of the hole between the instances +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceRight ( myInst2, NOSYM ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] PlaceRight : no previous instance.-\\One can use \verb-PlaceTop- only if a reference instance exist. Use a \verb-Place- call before. + \item \verb-[Stratus ERROR] PlaceRight : wrong argument for placement type.-\\The symetry given as argument is not correct. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} diff --git a/stratus1/doc/man_place_top.tex b/stratus1/doc/man_place_top.tex new file mode 100644 index 00000000..d9d51db3 --- /dev/null +++ b/stratus1/doc/man_place_top.tex @@ -0,0 +1,63 @@ +\subsubsection{Name} + +PlaceTop -- Places an instance at the top of the "reference instance" + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceTop ( ins, sym, offset ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use the \verb-PlaceTop- function.\\ + +\indent The bottom left corner of the abutment box of the instance is placed, after beeing symetrized and/or rotated, toward the top left corner of the abutment box of the "reference instance". The newly placed instance becomes the "reference instance". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-offset- (optionnal) : An offset is put between this instance and the reference instance. The value given as argument must be a multiple of PITCH and represents the lenght of the hole between the instances +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceTop ( myInst2, SYM_Y ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] PlaceTop : no previous instance.-\\One can use \verb-PlaceTop- only if a reference instance exist. Use a \verb-Place- call before. + \item \verb-[Stratus ERROR] PlaceTop : wrong argument for placement type.-\\The symetry given as argument is not correct. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} diff --git a/stratus1/doc/man_power_ring.tex b/stratus1/doc/man_power_ring.tex new file mode 100644 index 00000000..fcbea685 --- /dev/null +++ b/stratus1/doc/man_power_ring.tex @@ -0,0 +1,45 @@ +\subsubsection{Name} + +PowerRing -- Placement of power rings. + +\subsubsection{Synopsys} + +\begin{verbatim} +PowerRing ( nb ) +\end{verbatim} + +\subsubsection{Description} + +This function places power rings around the core and around the plots. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-nb- : Number of pair of rings vdd/vss +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +PowerRing ( 3 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PowerRing : Pads in the north haven't been placed.-\\The pads of the 4 sides of the chip must be placed before calling function PowerRing. + \item \verb-[Stratus ERROR] PowerRing : too many rings, not enough space.-\\Wether The argument of PowerRing is to big, or the abutment box of the chip is to small. There's no space to put the rings. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} diff --git a/stratus1/doc/man_reg.tex b/stratus1/doc/man_reg.tex new file mode 100644 index 00000000..0af5ffcb --- /dev/null +++ b/stratus1/doc/man_reg.tex @@ -0,0 +1,51 @@ +\subsubsection{Name} + +Reg -- Easy way to instantiate a register + +\subsubsection{Synopsys} + +\begin{verbatim} +netOut <= netCk.Reg ( netIn ) +\end{verbatim} + +\subsubsection{Description} + +This method is a method of net. The net which this method is applied to is the clock of the register. The net given as parameter is the input net. The method returns a net : the output net.\\ +\indent Note that it is possible to change the generator instanciated with the \verb-SetReg- method. + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = LogicIn ( "a", 4 ) + self.S = LogicOut ( "s", 4 ) + + self.Ck = CkIn ( "ck" ) + + self.Vdd = VddIn ( "vdd" ) + self.Vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S <= self.Ck.Reg ( self.A ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Reg : The input net does not have a positive arity.-\\The input net must have a positive arity. + \item \verb-[Stratus ERROR] Reg : The clock does not have a positive arity.-\\The clock must have a positive arity. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multiplexor}{secmux} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} diff --git a/stratus1/doc/man_resize_ab.tex b/stratus1/doc/man_resize_ab.tex new file mode 100644 index 00000000..de142d3e --- /dev/null +++ b/stratus1/doc/man_resize_ab.tex @@ -0,0 +1,49 @@ +\subsubsection{Name} + +ResizeAb -- Modifies the abutment box of the current cell + +\subsubsection{Synopsys} + +\begin{verbatim} +ResizeAb ( dx1, dy1, dx2, dy2 ) +\end{verbatim} + +\subsubsection{Description} + +This function modifies the abutment box of the current cell.\\ +\indent The coordinates of the abutment box are the coordinates of the envelop of the abutment boxes of each instance plus the delta values given as argument.\\ + +\indent Note that one can not call this function in order to create the abutment box. This fonction only modifies the already created abutment box. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-(dx1, dy1)- : Values to be added to the lower left corner of the previous abutment box. + \item \verb-(dx2, dy2)- : Values to be added to the upper right corner of the previous abutment box. +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( Inv, NOSYM, 0, 0 ) + +ResizeAb ( 0, -100, 0, 100 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb- [Stratus ERROR] ResizeAb :-\\\verb-Coordinates of an abutment Box in y must be multiple of the slice.-\\\verb-Coordinates of an abutment Box in x must be multiple of the pitch.-\\One has called ResizeAb with non authorized values +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} diff --git a/stratus1/doc/man_route_ck.tex b/stratus1/doc/man_route_ck.tex new file mode 100644 index 00000000..1868ccd4 --- /dev/null +++ b/stratus1/doc/man_route_ck.tex @@ -0,0 +1,45 @@ +\subsubsection{Name} + +RouteCk -- Routing of signal Ck to standard cells + +\subsubsection{Synopsys} + +\begin{verbatim} +RouteCk ( net ) +\end{verbatim} + +\subsubsection{Description} + +This function routes signal Ck to standard cells. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-net- : the net which the fonction is applied to +\end{itemize} + +%\subsubsection{Example} +% +%\begin{verbatim} +%netCk = LogicIn ( "ck", 1 ) +%RouteCk ( netCk ) +%\end{verbatim} +% +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] RouteCk : Pads in the north haven't been placed-\\The pads must be placed before calling RoutageCk. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} diff --git a/stratus1/doc/man_set_ref_ins.tex b/stratus1/doc/man_set_ref_ins.tex new file mode 100644 index 00000000..404f4287 --- /dev/null +++ b/stratus1/doc/man_set_ref_ins.tex @@ -0,0 +1,53 @@ +\subsubsection{Name} + +SetRefIns -- Defines the new "reference instance" for placement + +\subsubsection{Synopsys} + +\begin{verbatim} +SetRefIns ( ins ) +\end{verbatim} + +\subsubsection{Description} + +This function defines the new "reference instance", used as starting point in the relative placement functions.\\ +\indent It's regarding the abutmentbox of the instance \verb-ins- that the next instance is going to be placed, if using the appropriate functions.\\ + +\indent Note that the more recently placed instance becomes automaticaly the "reference instance", if SetRefIns isn't called. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : defines the new "reference instance" +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceRight ( myInst2, NOSYM ) + +SetRefIns ( myInst1 ) +PlaceTop ( myInst3, SYM_Y ) +\end{verbatim} + +\indent \verb-myInst3- is on top of \verb-myInst1- instead of \verb-myInst2-. + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] SetRefIns : the instance doesn't exist.-\\If the instance has not been instanciated, it is impossible do to any placement from it. + \item \verb-[Stratus ERROR] SetRefIns : the instance ...is not placed.-\\If the instance has not been placed, it is impossible do to any placement from it. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} diff --git a/stratus1/doc/man_shift.tex b/stratus1/doc/man_shift.tex new file mode 100644 index 00000000..49867368 --- /dev/null +++ b/stratus1/doc/man_shift.tex @@ -0,0 +1,82 @@ +\subsubsection{Name} + +Shift -- Easy way to instantiate a shifter + +\subsubsection{Synopsys} + +\begin{verbatim} +netOut <= netCmd.Shift ( netIn, direction, type ) +\end{verbatim} + +\subsubsection{Description} + +This method is a method of net. The net which this method is applied to is the command of the shifter, it's the one which defines the number of bits to shift. The net given as parameter is the input net. The other arguments set the different patameters. The method returns a net : the output net.\\ +\indent Note that it is possible to change the generator instanciated with the \verb-SetShift- method. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-netIn- : the net which is going to be shifted + \item \verb-direction- : this string represents the direction of the shift : + \begin{itemize} + \item "left" + \item "right" + \end{itemize} + \item \verb-type- : this string represents the type of the shift : + \begin{itemize} + \item "logical" : only "zeros" are put in the net + \item "arith" : meaningful for "right" shift, the values put in the nets are an extension of the MSB + \item "circular" : the values put in the nets are the ones which have just been taken off + \end{itemize} +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = LogicIn ( "a", 4 ) + + self.Cmd = LogicIn ( "cmd", 2 ) + + self.S1 = LogicOut ( "s1", 4 ) + self.S2 = LogicOut ( "s2", 4 ) + self.S3 = LogicOut ( "s3", 4 ) + + self.Vdd = VddIn ( "vdd" ) + self.Vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S1 <= self.Cmd.Shift ( self.A, "right", "logical" ) + self.S2 <= self.Cmd.Shift ( self.A, "right", "arith" ) + + self.S3 <= self.Cmd.Shift ( self.A, "left", "circular" ) +\end{verbatim} +\indent If the value of "a" is "0b1001" and the value of "cmd" is "0b10", we will have : +\begin{itemize} + \item "s1" : "0b0010" + \item "s2" : "0b1110" + \item "s3" : "0b0110" +\end{itemize} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Shift : The input net does not have a positive arity.-\\The net which is going to be shifted must have a positive arity. + \item \verb-[Stratus ERROR] Shift :-\\\verb-The direction parameter must be "left" or "right".-\\The "direction" argument is not correct. + \item \verb-[Stratus ERROR] Shift :-\\\verb-The type parameter must be "logical" or "arith" or "circular".-\\The "type" argument is not correct. +\end{itemize} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multiplexor}{secmux} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} diff --git a/stratus1/doc/man_stratus.tex b/stratus1/doc/man_stratus.tex new file mode 100644 index 00000000..840123c7 --- /dev/null +++ b/stratus1/doc/man_stratus.tex @@ -0,0 +1,119 @@ +\subsubsection{Name} + +Stratus -- Procedural design language based upon \emph{Python} + +\subsubsection{Description} + +\emph{Stratus} is a set of \emph{Python} methods/functions dedicated to procedural generation purposes. From a user point of view, \emph{Stratus} is a circuit's description language that allows \emph{Python} programming flow control, variable use, and specialized functions in order to handle vlsi objects.\\ + +\indent Based upon the \emph{Hurricane} data structures, the \emph{Stratus} language gives the user the ability to describe netlist and layout views. + +\subsubsection{Creation of a cell} + +A cell is a hierachical structural description of a circuit in terms of ports (I/Os), signals (nets) and instances : + +\begin{itemize} +\item Method \verb-Interface- + \begin{itemize} + \item LogicIn + \item LogicOut + \item LogicInOut + \item TriState + \item VddIn + \item VssIn + \end{itemize} +\item Method \verb-Netlist- + \begin{itemize} + \item Signal + \item Inst + \item Facilities : \&, |, +, Mux, Shift, Eq/Ne ... + \end{itemize} +\item Method \verb-Layout- + \begin{itemize} + \item Place, PlaceTop, PlaceBottom, PlaceRight, PlaceLeft + \item SetRefIns + \item DefAb, ResizeAb + \item PlaceCentric + \item PlaceGlue, FillCell + \item PadNorth, PadSouth, PadEast, PadWest + \item AlimVerticalRail, AlimHorizontalRail + \item AlimConnectors + \item PowerRing + \item RouteCk + \end{itemize} + \item Method \verb-Pattern- + \item Method \verb-View- + \item Method \verb-Save- +\end{itemize} + +\subsubsection{Syntax highlighting} + +This chapter describes what to do to have the right syntax highlighting when using vi. + +\begin{itemize} + \item Commands to do when you want to change once the coloration of your file : +\end{itemize} +\begin{small} +\begin{verbatim} +:syntax off +:source /asim/coriolis/share/etc/stratus.vim +\end{verbatim} +\end{small} +\begin{itemize} + \item Modification of your .vimrc in order to have the syntax highlighting each time you open a file : +\end{itemize} +\begin{small} +\begin{verbatim} +syntax off +autocmd BufRead,BufNewfile *.py so /asim/coriolis/share/etc/stratus.vim +syntax on +\end{verbatim} +\end{small} + +\subsubsection{Environment variables} + +\begin{itemize} + \item CRL\_IN\_LO, default value : \verb-def- + \item CRL\_OUT\_LO, default value : \verb-def- + \item CRL\_IN\_PH, default value : \verb-def- + \item CRL\_OUT\_PH, default value : \verb-def- + \item CRL\_CATA\_LIB, default value : \verb-.- + \item CRL\_CATAL\_NAME, default value : \verb-CATAL- +\end{itemize} + +\subsubsection{Syntax} + +A \emph{Stratus} file must have a .py extension and must begin as follow : +\begin{verbatim} +#!/usr/bin/python + +from stratus import * +\end{verbatim} + +\indent In order to execute a \emph{Stratus} file (named \verb-file- for example), one has two choices : +\begin{verbatim} +python file.py +\end{verbatim} +\indent Or : +\begin{verbatim} +chmod u+x file.py +./file.py +\end{verbatim} + +\indent The names used in \emph{Stratus}, as arguments to \emph{Stratus} functions, should be alphanumerical, including the underscore. The arguments of \emph{Stratus} are case sensitive, so \textsc{VDD} is not equivalent to \textsc{vdd}.\\ + +\indent Vectorized connectors or signal can be used using the \textsc{[n:m]} construct.\\ + +\subsubsection{Example} + +You can see a concrete example at : \hyperref[ref]{\emph{A concrete example}}{}{Example}{secexample} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Model}}{}{Model}{secmodel} +\hyperref[ref]{\emph{Param}}{}{Param}{secparam} +\hyperref[ref]{\emph{Example}}{}{Example}{secexample} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{Place and Route}}{}{Place and Route}{secroute} +\hyperref[ref]{\emph{Facilities}}{}{Facilities}{secfacilities} diff --git a/stratus1/doc/patterns/.latex2html-init b/stratus1/doc/patterns/.latex2html-init new file mode 100644 index 00000000..41736623 --- /dev/null +++ b/stratus1/doc/patterns/.latex2html-init @@ -0,0 +1,308 @@ + +# -*- Perl -*- +# +#LaTeX2HTML Version 96.1 : dot.latex2html-init +# +### Command Line Argument Defaults ####################################### + +$MAX_SPLIT_DEPTH = 4; # Stop making separate files at this depth + +$MAX_LINK_DEPTH = 2; # Stop showing child nodes at this depth + +$NOLATEX = 0; # 1 = do not pass unknown environments to Latex + +$EXTERNAL_IMAGES = 0; # 1 = leave the images outside the document + +$ASCII_MODE = 0; # 1 = do not use any icons or internal images + +# 1 = use links to external postscript images rather than inlined bitmap +# images. +$PS_IMAGES = 0; + +#$TITLE = "Titre"; # The default is "No Title" + +$DESTDIR = ''; # Put the result in this directory + +# When this is set, the generated HTML files will be placed in the +# current directory. If set to 0 the default behaviour is to create (or reuse) +# another file directory. +$NO_SUBDIR = 0; + + +# Supply your own string if you don't like the default +$ADDRESS = "$address_data[0]
    \n$address_data[1]    "; + +$NO_NAVIGATION = 0; # 1 = do not put a navigation panel at the top of each page + +# Put navigation links at the top of each page. +# If the page exceeds $WORDS_IN_PAGE number of words then put one at the bottom of the page. +$AUTO_NAVIGATION = 1; + +# Put a link to the index page in the navigation panel +$INDEX_IN_NAVIGATION = 1; + +# Put a link to the table of contents in the navigation panel +$CONTENTS_IN_NAVIGATION = 1; + +# Put a link to the next logical page in the navigation panel +$NEXT_PAGE_IN_NAVIGATION = 1; + +# Put a link to the previous logical page in the navigation panel +$PREVIOUS_PAGE_IN_NAVIGATION = 1; + +$INFO = 0; # 0 = do not make a "About this document..." section + +# Reuse images generated during previous runs +$REUSE = 2; + +# When this is 1, the section numbers are shown. The section numbers should +# then match those that would have bee produced by LaTeX. +# The correct section numbers are obtained from the $FILE.aux file generated +# by LaTeX. +# Hiding the seciton numbers encourages use of particular sections +# as standalone documents. In this case the cross reference to a section +# is shown using the default symbol rather than the section number. +$SHOW_SECTION_NUMBERS = 0; + +### Other global variables ############################################### +$CHILDLINE = "
    \n"; + +# This is the line width measured in pixels and it is used to right justify +# equations and equation arrays; +$LINE_WIDTH = 500; + +# Used in conjunction with AUTO_NAVIGATION +#$WORDS_IN_PAGE = 300; !!! +$WORDS_IN_PAGE = 50; + +# Affects ONLY the way accents are processed +$default_language = 'english'; + +# The value of this variable determines how many words to use in each +# title that is added to the navigation panel (see below) +# +$WORDS_IN_NAVIGATION_PANEL_TITLES = 4; + +# This number will determine the size of the equations, special characters, +# and anything which will be converted into an inlined image +# *except* "image generating environments" such as "figure", "table" +# or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$MATH_SCALE_FACTOR = 1.6; + +# This number will determine the size of +# image generating environments such as "figure", "table" or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$FIGURE_SCALE_FACTOR = 1.6; + + +# If this is set then intermediate files are left for later inspection. +# This includes $$_images.tex and $$_images.log created during image +# conversion. +# Caution: Intermediate files can be *enormous*. +$DEBUG = 0; + +# If both of the following two variables are set then the "Up" button +# of the navigation panel in the first node/page of a converted document +# will point to $EXTERNAL_UP_LINK. $EXTERNAL_UP_TITLE should be set +# to some text which describes this external link. +$EXTERNAL_UP_LINK = ""; +$EXTERNAL_UP_TITLE = ""; + +# If this is set then the resulting HTML will look marginally better if viewed +# with Netscape. +$NETSCAPE_HTML = 0; + +# Valid paper sizes are "letter", "legal", "a4","a3","a2" and "a0" +# Paper sizes has no effect other than in the time it takes to create inlined +# images and in whether large images can be created at all ie +# - larger paper sizes *MAY* help with large image problems +# - smaller paper sizes are quicker to handle +$PAPERSIZE = "a4"; + +# Replace "english" with another language in order to tell LaTeX2HTML that you +# want some generated section titles (eg "Table of Contents" or "References") +# to appear in a different language. Currently only "english" and "french" +# is supported but it is very easy to add your own. See the example in the +# file "latex2html.config" +$TITLES_LANGUAGE = "english"; + +### Navigation Panel ########################################################## +# +# The navigation panel is constructed out of buttons and section titles. +# These can be configured in any combination with arbitrary text and +# HTML tags interspersed between them. +# The buttons available are: +# $PREVIOUS - points to the previous section +# $UP - points up to the "parent" section +# $NEXT - points to the next section +# $NEXT_GROUP - points to the next "group" section +# $PREVIOUS_GROUP - points to the previous "group" section +# $CONTENTS - points to the contents page if there is one +# $INDEX - points to the index page if there is one +# +# If the corresponding section exists the button will contain an +# active link to that section. If the corresponding section does +# not exist the button will be inactive. +# +# Also for each of the $PREVIOUS $UP $NEXT $NEXT_GROUP and $PREVIOUS_GROUP +# buttons there are equivalent $PREVIOUS_TITLE, $UP_TITLE, etc variables +# which contain the titles of their corresponding sections. +# Each title is empty if there is no corresponding section. +# +# The subroutine below constructs the navigation panels in each page. +# Feel free to mix and match buttons, titles, your own text, your logos, +# and arbitrary HTML (the "." is the Perl concatenation operator). + + +@my_icon_tags = (); +$my_icon_tags{'next'} = 'Next Page'; +$my_icon_tags{'next_page'} = 'Next Page'; +$my_icon_tags{'previous'} = 'Previous Page'; +$my_icon_tags{'previous_page'} = 'Previous Page'; +$my_icon_tags{'up'} = 'Up One Level'; +$my_icon_tags{'contents'} = 'Contents'; +$my_icon_tags{'index'} = 'Index'; +$my_icon_tags{'modules'} = 'Module Index'; + +@my_icon_names = (); +$my_icon_names{'previous_page'} = 'prev'; +$my_icon_names{'next_page'} = 'next'; + + +sub get_my_icon($) { + my $icon_file; + my $name = @_[0]; + my $text = $my_icon_tags{$name}; + if ($my_icon_names{$name}) { + $name = $my_icon_names{$name}; + } + if ($text eq '') { + $name = 'blank'; + } + $icon_file = $name . "." . $IMAGE_TYPE; + $used_icons{$icon_file} = 1; + return "\"$text\""; +} + + +sub use_my_icon($) { + my $s = @_[0]; + if ($s =~ /\/) { + my $r = get_my_icon($1); + $s =~ s/\/$r/; + } + return $s; +} + + +sub make_top_nav_panel() { + my $s; + $s = ('' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
    $t_title
    " + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
    " + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
    \n" + . "
    \n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub make_bot_nav_panel() { + my $s; + $s = ('
    ' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
    $t_title
    " + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
    " + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
    \n" + . "
    \n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub top_navigation_panel { + return "\n" + . make_top_nav_panel() + . "
    \n"; +} + + +sub bot_navigation_panel { + return "\n

    \n" + . make_bot_nav_panel() + . "\n"; +} + + +#$EXTERNAL_STYLESHEET = "../ASIM.css"; + +$ADDRESS = "Sophie BELLOEIL
    20051116.1"; + +$LOCAL_ICONS = 0; + +$USING_STYLES = 1; + +$TRANSPARENT_FIGURES = 1; + +$WHITE_BACKGROUND = 0; + +$used_icons{"home." . $IMAGE_TYPE} = 1; + +1; # This must be the last line diff --git a/stratus1/doc/patterns/ASIM.css b/stratus1/doc/patterns/ASIM.css new file mode 100644 index 00000000..180cadb3 --- /dev/null +++ b/stratus1/doc/patterns/ASIM.css @@ -0,0 +1,164 @@ + + html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 { + font-size: 100%; + font-family: verdana, sans-serif; + } + + body { + color: black; + background: white; + background-color: white; + background-position: top left; + background-attachment: fixed; + background-repeat: no-repeat; + margin-top: 2em; + margin-right: 10%; + margin-left: 10%; + } + + hr { + height: 1px; + border: 0; + color: #004400; + background-color: #004400; + } + + + h1, h2, h3, h4, h5, h6 { + font-family: verdana, sans-serif; + } + + h1 { text-align: center; } + h2, h3, h4, h5, h6 { text-align: left; + padding-top: 2em; + } + h1, h2, h3 { font-family: "Trebuchet MS", sans-serif; + color: #09550B; + } + h1 { font-weight: bold; font-size: 170%; } + h2 { font-weight: bold; font-size: 140%; } + h3 { font-weight: bold; font-size: 118%; } + h4 { font-weight: bold; font-size: 100%; } + h5 { font-style: italic; font-size: 100%; } + h6 { font-variant: small-caps; font-size: 100%; } + + .hide { + display: none; + color: white; + } + + + div.navigation { margin-bottom: 1em; } + div.navigation h1 { margin-top: 2em; clear: both; } + div.navigation table { margin-left: 2em; font-size: 90%; } + div.navigation img { color: white; border: none; } + + + p { + margin-top: 0.6em; + margin-bottom: 0.6em; + margin-left: 0.0em; + margin-right: 0.0em; + } + + p.copyright { font-size: 90%; } + p.copyright small { font-size: 80%; } + + p.changed { + padding-left: 0.2em; + border-left: solid; + border-top: none; + border-bottom: none; + border-right: none; + border-left-width: thin; + border-color: red; + } + + + address { + text-align: right; + font-weight: bold; + font-style: italic; + font-size: 80%; + } + + + blockquote { + margin-left: 4em; + margin-right: 4em; + margin-top: 0.8em; + margin-bottom: 0.8em; + font-style: italic; + color: #003300; + } + + blockquote p { + margin-bottom: 0; + } + + blockquote address { + margin: 0; + } + + + table { + border-collapse: collapse; + /* + margin-left: 0em; + margin-right: 0em; + */ + margin-top: 0.8em; + margin-bottom: 0.8em; + } + + dt, dd { margin-top: 0; margin-bottom: 0; } + dt { font-weight: bold; } + + + pre, tt, code { + font-family: "andale mono", monospace; + font-size: 100%; + white-space: pre; + } + + pre { + font-size: 80%; + border: solid; + border-width: thin; + border-color: #003300; + background-color: #EEEEEE; + padding: 0.5em; + margin-left: 2em; + margin-right: 2em + } + + tt { color: green; } + em { font-style: italic; font-weight: bold; } + strong { font-weight: bold; } + + span.textit { font-style: italic; } + span.textbf { font-weight: bold; } + + .small { font-size: 90%; } + .white { color: #FFFFFF; } + + + ul.toc { + list-style: disc; + list-style: none; + } + + + a:link img, a:visited img { border-style: none; } + a img { color: white; } + + a:link, a:active, a:visited { + color: #09550B; + text-decoration: none; + } + + a:hover, a:focus { + color: #FF9900; + text-decoration: underline; + } + diff --git a/stratus1/doc/patterns/Makefile.am b/stratus1/doc/patterns/Makefile.am new file mode 100644 index 00000000..750e420b --- /dev/null +++ b/stratus1/doc/patterns/Makefile.am @@ -0,0 +1,66 @@ + +doc_en_latex_patternsdir = $(datadir)/doc/en/latex/patterns +doc_en_html_patternsdir = $(datadir)/doc/en/html/patterns +doc_en_pdf_patternsdir = $(datadir)/doc/en/pdf/patterns + + +doc_en_patterns_EXTRA = patterns.tex \ + html.entry \ + ASIM.css \ + .latex2html-init + + +install-data-hook: + @if [ `which latex2html 2>/dev/null` ]; then \ + for file in `ls $(srcdir)/*.tex`; do \ + filename=`basename $$file`; \ + if [ ! -L $$filename -a ! -f $$filename ]; then \ + ln -sf $(srcdir)/$$filename . ; \ + fi ; \ + done ; \ + if [ ! -L ASIM.css -a ! -f ASIM.css ]; then \ + ln -sf $(srcdir)/*.css . ; \ + ln -sf $(srcdir)/.latex2html-init . ; \ + $(mkinstalldirs) images ; \ + ln -sf $(srcdir)/images/*.png ./images/ ; \ + fi ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_latex_patternsdir) ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_latex_patternsdir)/images ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_html_patternsdir) ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_pdf_patternsdir) ; \ + cp -r *.tex $(DESTDIR)$(doc_en_latex_patternsdir) ; \ + cp -r *.css $(DESTDIR)$(doc_en_latex_patternsdir) ; \ + cp -r .latex2html-init $(DESTDIR)$(doc_en_latex_patternsdir) ; \ + cp -r images/*.png $(DESTDIR)$(doc_en_latex_patternsdir)/images ; \ + rm -f *.aux *.lof *.log *.out *.toc *.dvi ; \ + latex2html -no_math -html_version 4.0,math -style ./ASIM.css patterns.tex ; \ + cp -pr patterns/* $(DESTDIR)$(doc_en_html_patternsdir) ; \ + cp -p ASIM.css $(DESTDIR)$(doc_en_html_patternsdir)/ASIM.css ; \ + pdflatex patterns.tex ; \ + pdflatex patterns.tex ; \ + cp patterns.pdf $(DESTDIR)$(doc_en_pdf_patternsdir) ; \ + cp $(srcdir)/html.entry $(DESTDIR)$(doc_en_html_patternsdir); \ + if [ -x $(datadir)/doc/en/html/generateIndex.sh ]; then \ + $(datadir)/doc/en/html/generateIndex.sh \ + --prefix=${prefix} --destdir=$(DESTDIR) ; \ + fi ; \ + else \ + echo "[WARNING] latex2html not found, skipping doc generation."; \ + fi + + +EXTRA_DIST = $(doc_en_patterns_EXTRA) + +CLEANFILES = *.dvi \ + *.ps \ + *.lof \ + *.log \ + *.out \ + *.toc \ + *.aux \ + *.bak \ + stratus/*.html \ + stratus/*.css \ + stratus/*.pl \ + stratus/WARNINGS + diff --git a/stratus1/doc/patterns/html.entry b/stratus1/doc/patterns/html.entry new file mode 100644 index 00000000..902d828c --- /dev/null +++ b/stratus1/doc/patterns/html.entry @@ -0,0 +1 @@ +

  • Patterns module
    Patterns description using Stratus

    diff --git a/stratus1/doc/patterns/patterns.tex b/stratus1/doc/patterns/patterns.tex new file mode 100644 index 00000000..45009167 --- /dev/null +++ b/stratus1/doc/patterns/patterns.tex @@ -0,0 +1,269 @@ +\documentclass[12pt]{article} +\usepackage[latin1]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{palatino} +\usepackage{fancyhdr} +\usepackage{float} +\usepackage{subfigure} +\usepackage{wrapfig} +\usepackage[dvips]{graphics} +\usepackage{graphicx} +\usepackage{epsfig} +\usepackage{multicol} +\usepackage{url} +\usepackage{html} +\usepackage{color} + + \definecolor{violet}{rgb}{0.5,0,0.5} + +\setlength{\topmargin}{0cm} +\setlength{\headheight}{1cm} +\setlength{\textheight}{21cm} +\setlength{\textwidth}{16cm} +\setlength{\oddsidemargin}{0cm} +\setlength{\evensidemargin}{0cm} +\setlength{\columnsep}{0.125in} +\setlength{\columnseprule}{0.5pt} +\setlength{\footskip}{1cm} +\sloppy + +%--------------------------------- page style -------------------------------- +\pagestyle{fancy} +\rhead{} +\lhead{} +\rfoot{\thepage} +\lfoot{} +\cfoot{} +%---------------------------------- document --------------------------------- +\date {} +\title {Patterns Module User's Manual} +\author {Roselyne Chotin-Avot} + +\begin{document} + +\setlength{\footrulewidth}{0.6pt} +\maketitle + +%%\begin{htmlonly} +%% \htmlrule +%% \noindent La version imprimable de ce document est disponible ici~: \\ +%% \begin{center} +%% \hyperref[hyper]{http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf}{}{} +%% {http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf} +%% \end{center} +%%\end{htmlonly} + +\tableofchildlinks +\htmlrule + +\section{Description} +The patterns module of \emph{Stratus} is a set of \emph{Python} classes and +methods that allows a procedural description of input pattern file for the +logic simulator. The \emph{Stratus} \verb-Pattern- method produces a pattern +description file as output. The file generated by \verb-Pattern- method is in +pat format, so IT IS STRONGLY RECOMMENDED TO SEE pat(5) manual BEFORE TO USE +IT. + +\section{Syntax} +From a user point of view, \verb-Pattern- method is a pattern description +language using all standard \emph{Python} facilities. Here follows the +description of the \verb-Pattern- method.\\ +A pat format file can be divided in two parts : declaration and description +part.\\ +The declaration part is the list of inputs, outputs, internal signals and +registers. Inputs are to be forced to a certain value and all the others are +to be observed during simulation.\\ +The description part is a set of patterns, where each pattern defines the value +of inputs and outputs. The pattern number represents actually the absolute time +for the simulator.\\ +Similarly, a \verb-Pattern- method can be divided in two parts : declaration +and description part. Methods related to the declaration must be called +before any function related to the description part. + +\subsection{Declaration part} +The first thing you should do in this part is to instantiate the class +\verb-Patwrite- to have access to all patterns declaration and description +methods. The constructor of this class take as parameters the name of pattern +output file and the \emph{Stratus} cell that is described (see \verb-PatWrite- +\ref{patwrite}).\\ +Then, this part allows you to declare the inputs, the outputs, and internal +observing points (see \verb-declar-\ref{declar} and \verb-declar_interface- +\ref{declar_interface}). + +\subsection{Description part} +After all signals are declared, you can begin the description part (see +\verb-pattern_begin- \ref{pattern_begin}). In this part you have to define +input values which are to be applied to the inputs of the circuit or output +values which are to be compare with the values produced during the simulation. +(see \verb-affect- \ref{affect}, \verb-affect_any- \ref{affect_any}, +\verb-affect_int- \ref{affect_int} and \verb-affect_fix- \ref{affect_fix}). +\verb-Pattern- method describes the stimulus by event : only signal transitions +are described. After each event there is a new input in the pattern file (see +\verb-addpat- \ref{addpat}). Last thing you should do in this part is to +generate the output file (see \verb-pattern_end- \ref{pattern_end}). + +\section{Methods} +\subsection{PatWrite} +\label{patwrite} +This class is used to create patterns for \emph{Stratus} models. Currently +it only supports Alliance ".pat" pattern format. Patterns time stamps are in +the "absolute date" format, "relative date" isn't allowed. Legal time unit are +ps (default), ns, us and ms. The constructor takes as parameters the pattern +output filename and an optional reference to Stratus cell. + +\subsection{declar} +\label{declar} +Adds a connector from a Stratus model to the pattern interface. Writes the +corresponding connector declaration in the pattern file with name, arity and +direction automatically extracted from the connector properties.\\ +Supported Stratus connectors are: +\begin{itemize} +\item{SignalIn,} +\item{SignalOut (only supported if used as an output),} +\item{VddIn,} +\item{VssIn,} +\item{CkIn,} +\item{SignalInOut,} +\item{TriState (always an output),} +\item{Signals.} +\end{itemize} + +\subsubsection{Parameters} +\begin{itemize} +\item{connector : can either be a reference to a stratus net or a string +containing the name of the stratus net.} +\item{format : optional format for the connectors values into the pattern file, +accepted values are :} + \begin{itemize} + \item{'B': binary (default),} + \item{'X': hexadecimal,} + \item{'O': octal.} + \end{itemize} +\end{itemize} + +\subsection{declar\_interface} +\label{declar_interface} +Adds all the connectors from a Stratus model to the pattern interface. Write +the corresponding connector declaration in the pattern file with name, arity +and direction directly taken from the connector proprieties.\\ + +\subsubsection{Parameters} +\begin{itemize} +\item{cell : the tested Stratus model reference. Optional if a reference to the +tested Stratus model was given during instanciation\ref{patwrite}.} +\item{format : optional format for the connectors values into the pattern file, +accepted values are :} + \begin{itemize} + \item{'B': binary (default),} + \item{'X': hexadecimal,} + \item{'O': octal.} + \end{itemize} +\end{itemize} + +\subsection{declar} +\label{declar} +Affect a string value to a connector. + +\subsubsection{Parameters} +\begin{itemize} +\item{connector : \emph{Stratus} connector} +\item{value : string to affect to connector} +\end{itemize} + +\subsection{affect\_int} +\label{affect_int} +Affect an integer (CA2) value to a connector. Convert the 2's complement value +to the corresponding binary value. The binary size is taken from the connector +arity. If the connector is an output, the binary value is preceded by "?". + +\subsubsection{Parameters} +\begin{itemize} +\item{connector : \emph{Stratus} connector.} +\item{value : 2's complement value to affect to the connector.} +\end{itemize} + +\subsection{affect\_fix} +\label{affect_fix} +Affect a fixed point value to a connector. Convert the floating point input +value to the corresponding fixed point value with +word\_length=connector.arity() and integer\_word\_length=iwl. If the connector +is an output, the binary value is preceded by "?". + +\subsubsection{Parameters} +\begin{itemize} +\item{connector : \emph{Stratus} connector.} +\item{value : floating point value to convert and asign to connector.} +\item{iwl : integer word length} +\end{itemize} + +\subsection{affect\_any} +\label{affect_any} +Disable comparison between this connector value and the one calculated during +simulation. + +\subsubsection{Parameters} +\begin{itemize} +\item{connector : \emph{Stratus} connector.} +\end{itemize} + +\subsection{addpat} +\label{addpat} +Adds a pattern in the pattern file. + +\subsection{pattern\_begin} +\label{pattern_begin} +Mark the end of the interface declaration and the beginning of the test +vectors. + +\subsection{pattern\_end} +\label{pattern_end} +Mark the end of the test vectors and of the patterns file. + +\section{Example} +\verb-Pattern- method for an addaccu +\begin{verbatim} +def Pattern(self): + # initialisation + pat = PatWrite(self._name+'.pat',self) + + # declaration of ports + pat.declar(self.ck, 'B') + pat.declar(self.load, 'B') + pat.declar(self.input, 'X') + pat.declar(self.output, 'X') + pat.declar(self.vdd, 'B') + pat.declar(self.vss, 'B') + + # use of pat.declar_interface(self) has the same effect + + # description beginning + pat.pattern_begin() + + # affect vdd and vss values + pat.affect_int(self.vdd,1) + pat.affect_int(self.vss,0) + + # first pattern : load an initial value + pat.affect_int(self.input,5) + pat.affect_int(self.load,1) + pat.affect_int(self.ck,0) + # add the pattern in the pattern file + pat.addpat() + # compute next event + pat.affect_int(self.ck,1) + pat.addpat() + + # compute 22 cycle of accumulation + pat.affect_int(self.load,0) + for i in range(1,22): + pat.affect_int(self.ck,0) + pat.addpat() + pat.affect_int(self.ck,1) + pat.affect_int(self.output,i+5) + pat.addpat() + + # end of the description + pat.pattern_end() +\end{verbatim} + +\end{document} diff --git a/stratus1/doc/see_also.tex b/stratus1/doc/see_also.tex new file mode 100644 index 00000000..32299cf7 --- /dev/null +++ b/stratus1/doc/see_also.tex @@ -0,0 +1,3 @@ +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} diff --git a/stratus1/doc/stratus.tex b/stratus1/doc/stratus.tex new file mode 100644 index 00000000..3ff42f29 --- /dev/null +++ b/stratus1/doc/stratus.tex @@ -0,0 +1,289 @@ +\documentclass[12pt]{article} +\usepackage[latin1]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{palatino} +\usepackage{fancyheadings} +\usepackage{float} +\usepackage{subfigure} +\usepackage{wrapfig} +\usepackage[dvips]{graphics} +\usepackage{graphicx} +\usepackage{epsfig} +\usepackage{multicol} +\usepackage{color} +\usepackage{url} +\usepackage{html} + +\setlength{\topmargin}{0cm} +\setlength{\headheight}{1cm} +\setlength{\textheight}{21cm} +\setlength{\textwidth}{16cm} +\setlength{\oddsidemargin}{0cm} +\setlength{\evensidemargin}{0cm} +\setlength{\columnsep}{0.125in} +\setlength{\columnseprule}{0.5pt} +\setlength{\footskip}{1cm} +\sloppy + +\newcommand{\image}[4] +% {\begin{figure}[htbp] + {\begin{figure}[h!] + \includegraphics[width=#2\textwidth]{#1} + \end{figure} + } +% \image{fig.eps}{scale} + +%--------------------------------- page style -------------------------------- +\pagestyle{fancy} +\rhead{} +\lhead{} +\rfoot{\thepage} +\lfoot{} +\cfoot{} +%---------------------------------- document --------------------------------- +\date {} +\title {Stratus User's Manual} +\author {Sophie Belloeil} + +\begin{document} + +\setlength{\footrulewidth}{0.6pt} +\maketitle + +%%\begin{htmlonly} +%% \htmlrule +%% \noindent La version imprimable de ce document est disponible ici~: \\ +%% \begin{center} +%% \hyperref[hyper]{http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf}{}{} +%% {http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf} +%% \end{center} +%%\end{htmlonly} + +\tableofchildlinks +\htmlrule + +\section{Introduction} +\label{secintroduction} + + \subsection{Stratus} + \label{secstratus} + \input{man_stratus} + \subsection{Class Model} + \label{secmodel} + \input{man_model} + \subsection{Function Param} + \label{secparam} + \input{man_param} + \subsection{A concrete example} + \label{secexample} + \input{man_example} + +\newpage +\section{Description of a netlist} +\label{secnetlist} + + \subsection{Creation of nets} + \label{secnet} + \input{man_net} + \subsection{Creation of instances} + \label{secinst} + \input{man_inst} + \subsection{Method Alias} + \label{secalias} + \input{man_alias} + \subsection{Method Extend} + \label{secextend} + \input{man_extend} + \subsection{Function Cat} + \label{seccat} + \input{man_cat} + +\newpage +\section{Description of a layout} +\label{seclayout} + + \subsection{Place} + \label{secplace} + \input{man_place} + \subsection{PlaceTop} + \label{sectop} + \input{man_place_top} + \subsection{PlaceBottom} + \label{secbottom} + \input{man_place_bottom} + \subsection{PlaceRight} + \label{secright} + \input{man_place_right} + \subsection{PlaceLeft} + \label{secleft} + \input{man_place_left} + \subsection{SetRefIns} + \label{secsetrefins} + \input{man_set_ref_ins} + \subsection{DefAb} + \label{secdefab} + \input{man_def_ab} + \subsection{ResizeAb} + \label{secresizeab} + \input{man_resize_ab} + +\newpage +\section{Place and Route} +\label{secroute} + + \subsection{PlaceCentric} + \label{seccentric} + \input{man_place_centric} + \subsection{PlaceGlu} + \label{secglu} + \input{man_place_glu} + \subsection{FillCell} + \label{secfillcell} + \input{man_fill_cell} + \subsection{Pads} + \label{secpads} + \input{man_pads} + \subsection{Alimentation rails} + \label{secrails} + \input{man_alim_rail} + \subsection{Alimentation connectors} + \label{secconnectors} + \input{man_alim_connectors} + \subsection{PowerRing} + \label{secpowerring} + \input{man_power_ring} + \subsection{RouteCk} + \label{secrouteck} + \input{man_route_ck} + +\newpage +\section{Facilities} +\label{secfacilities} + + \subsection{Instanciation of a buffer} + \label{secbuff} + \input{man_buff} + \subsection{Instanciation of a multiplexor} + \label{secmux} + \input{man_mux} + \subsection{Instanciation of a shifter} + \label{secshift} + \input{man_shift} + \subsection{Instanciation of a register} + \label{secreg} + \input{man_reg} + \subsection{Instanciation of constants} + \label{secconstant} + \input{man_const} + \subsection{Logical operations} + \label{secbool} + \input{man_boolean} + \subsection{Arithmetical operations} + \label{secarithmetic} + \input{man_arithmetic} + \subsection{Comparison operations} + \label{seccomp} + \input{man_comp} + +\begin{htmlonly} +\section{Stratus' tools} + +You can have the documentation of the tools related to stratus at :\\ +file:////users/outil/arith/latest/doc/index.html +\end{htmlonly} + +\newpage +\section{Instanciation of your own generators} +\input{man_generators} + +\section{Libraries} + + \subsection{Virtual library} + \input{man_library} + + \subsection{DPGEN generators} + + \subsubsection{DpgenInv} + \input{man_dpgeninv} + \subsubsection{DpgenBuff} + \input{man_dpgenbuff} + \subsubsection{DpgenNand2} + \input{man_dpgennand2} + \subsubsection{DpgenNand3} + \input{man_dpgennand3} + \subsubsection{Dpgennand4} + \input{man_dpgennand4} + \subsubsection{DpgenAnd2} + \input{man_dpgenand2} + \subsubsection{DpgenAnd3} + \input{man_dpgenand3} + \subsubsection{DpgenAnd4} + \input{man_dpgenand4} + \subsubsection{DpgenNor2} + \input{man_dpgennor2} + \subsubsection{DpgenNor3} + \input{man_dpgennor3} + \subsubsection{DpgenNor4} + \input{man_dpgennor4} + \subsubsection{DpgenOr2} + \input{man_dpgenor2} + \subsubsection{DpgenOr3} + \input{man_dpgenor3} + \subsubsection{DpgenOr4} + \input{man_dpgenor4} + \subsubsection{DpgenXor2} + \input{man_dpgenxor2} + \subsubsection{DpgenXnor2} + \input{man_dpgenxnor2} + \subsubsection{DpgenNmux2} + \input{man_dpgennmux2} + \subsubsection{DpgenMux2} + \input{man_dpgenmux2} + \subsubsection{DpgenNbuse} + \input{man_dpgennbuse} + \subsubsection{DpgenBuse} + \input{man_dpgenbuse} + \subsubsection{DpgenNand2mask} + \input{man_dpgennand2mask} + \subsubsection{DpgenNor2mask} + \input{man_dpgennor2mask} + \subsubsection{DpgenXnor2mask} + \input{man_dpgenxnor2mask} + \subsubsection{DpgenAdsb2f} + \input{man_dpgenadsb2f} + \subsubsection{DpgenShift} + \input{man_dpgenshift} + \subsubsection{DpgenShrot} + \input{man_dpgenshrot} + \subsubsection{DpgenNul} + \input{man_dpgennul} + \subsubsection{DpgenConst} + \input{man_dpgenconst} + \subsubsection{DpgenRom2} + \input{man_dpgenrom2} + \subsubsection{DpgenRom4} + \input{man_dpgenrom4} + \subsubsection{DpgenRam} + \input{man_dpgenram} + \subsubsection{DpgenRf1} + \input{man_dpgenrf1} + \subsubsection{DpgenRf1d} + \input{man_dpgenrf1d} + \subsubsection{DpgenFifo} + \input{man_dpgenfifo} + \subsubsection{DpgenDff} + \input{man_dpgendff} + \subsubsection{DpgenDfft} + \input{man_dpgendfft} + \subsubsection{DpgenSff} + \input{man_dpgensff} + \subsubsection{DpgenSfft} + \input{man_dpgensfft} + +\begin{htmlonly} + \subsection{Arithmetic generators} + +You can have the documentation of the arithmetic library at :\\ +file:////users/outil/arith/latest/doc/index.html +\end{htmlonly} +\end{document} diff --git a/stratus1/doc/stratus/.latex2html-init b/stratus1/doc/stratus/.latex2html-init new file mode 100644 index 00000000..df1398eb --- /dev/null +++ b/stratus1/doc/stratus/.latex2html-init @@ -0,0 +1,308 @@ + +# -*- Perl -*- +# +#LaTeX2HTML Version 96.1 : dot.latex2html-init +# +### Command Line Argument Defaults ####################################### + +$MAX_SPLIT_DEPTH = 5; # Stop making separate files at this depth + +$MAX_LINK_DEPTH = 2; # Stop showing child nodes at this depth + +$NOLATEX = 0; # 1 = do not pass unknown environments to Latex + +$EXTERNAL_IMAGES = 0; # 1 = leave the images outside the document + +$ASCII_MODE = 0; # 1 = do not use any icons or internal images + +# 1 = use links to external postscript images rather than inlined bitmap +# images. +$PS_IMAGES = 0; + +#$TITLE = "Titre"; # The default is "No Title" + +$DESTDIR = ''; # Put the result in this directory + +# When this is set, the generated HTML files will be placed in the +# current directory. If set to 0 the default behaviour is to create (or reuse) +# another file directory. +$NO_SUBDIR = 0; + + +# Supply your own string if you don't like the default +$ADDRESS = "$address_data[0]
    \n$address_data[1]    "; + +$NO_NAVIGATION = 0; # 1 = do not put a navigation panel at the top of each page + +# Put navigation links at the top of each page. +# If the page exceeds $WORDS_IN_PAGE number of words then put one at the bottom of the page. +$AUTO_NAVIGATION = 1; + +# Put a link to the index page in the navigation panel +$INDEX_IN_NAVIGATION = 1; + +# Put a link to the table of contents in the navigation panel +$CONTENTS_IN_NAVIGATION = 1; + +# Put a link to the next logical page in the navigation panel +$NEXT_PAGE_IN_NAVIGATION = 1; + +# Put a link to the previous logical page in the navigation panel +$PREVIOUS_PAGE_IN_NAVIGATION = 1; + +$INFO = 0; # 0 = do not make a "About this document..." section + +# Reuse images generated during previous runs +$REUSE = 2; + +# When this is 1, the section numbers are shown. The section numbers should +# then match those that would have bee produced by LaTeX. +# The correct section numbers are obtained from the $FILE.aux file generated +# by LaTeX. +# Hiding the seciton numbers encourages use of particular sections +# as standalone documents. In this case the cross reference to a section +# is shown using the default symbol rather than the section number. +$SHOW_SECTION_NUMBERS = 0; + +### Other global variables ############################################### +$CHILDLINE = "
    \n"; + +# This is the line width measured in pixels and it is used to right justify +# equations and equation arrays; +$LINE_WIDTH = 500; + +# Used in conjunction with AUTO_NAVIGATION +#$WORDS_IN_PAGE = 300; !!! +$WORDS_IN_PAGE = 50; + +# Affects ONLY the way accents are processed +$default_language = 'english'; + +# The value of this variable determines how many words to use in each +# title that is added to the navigation panel (see below) +# +$WORDS_IN_NAVIGATION_PANEL_TITLES = 4; + +# This number will determine the size of the equations, special characters, +# and anything which will be converted into an inlined image +# *except* "image generating environments" such as "figure", "table" +# or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$MATH_SCALE_FACTOR = 1.6; + +# This number will determine the size of +# image generating environments such as "figure", "table" or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$FIGURE_SCALE_FACTOR = 1.6; + + +# If this is set then intermediate files are left for later inspection. +# This includes $$_images.tex and $$_images.log created during image +# conversion. +# Caution: Intermediate files can be *enormous*. +$DEBUG = 0; + +# If both of the following two variables are set then the "Up" button +# of the navigation panel in the first node/page of a converted document +# will point to $EXTERNAL_UP_LINK. $EXTERNAL_UP_TITLE should be set +# to some text which describes this external link. +$EXTERNAL_UP_LINK = ""; +$EXTERNAL_UP_TITLE = ""; + +# If this is set then the resulting HTML will look marginally better if viewed +# with Netscape. +$NETSCAPE_HTML = 0; + +# Valid paper sizes are "letter", "legal", "a4","a3","a2" and "a0" +# Paper sizes has no effect other than in the time it takes to create inlined +# images and in whether large images can be created at all ie +# - larger paper sizes *MAY* help with large image problems +# - smaller paper sizes are quicker to handle +$PAPERSIZE = "a4"; + +# Replace "english" with another language in order to tell LaTeX2HTML that you +# want some generated section titles (eg "Table of Contents" or "References") +# to appear in a different language. Currently only "english" and "french" +# is supported but it is very easy to add your own. See the example in the +# file "latex2html.config" +$TITLES_LANGUAGE = "english"; + +### Navigation Panel ########################################################## +# +# The navigation panel is constructed out of buttons and section titles. +# These can be configured in any combination with arbitrary text and +# HTML tags interspersed between them. +# The buttons available are: +# $PREVIOUS - points to the previous section +# $UP - points up to the "parent" section +# $NEXT - points to the next section +# $NEXT_GROUP - points to the next "group" section +# $PREVIOUS_GROUP - points to the previous "group" section +# $CONTENTS - points to the contents page if there is one +# $INDEX - points to the index page if there is one +# +# If the corresponding section exists the button will contain an +# active link to that section. If the corresponding section does +# not exist the button will be inactive. +# +# Also for each of the $PREVIOUS $UP $NEXT $NEXT_GROUP and $PREVIOUS_GROUP +# buttons there are equivalent $PREVIOUS_TITLE, $UP_TITLE, etc variables +# which contain the titles of their corresponding sections. +# Each title is empty if there is no corresponding section. +# +# The subroutine below constructs the navigation panels in each page. +# Feel free to mix and match buttons, titles, your own text, your logos, +# and arbitrary HTML (the "." is the Perl concatenation operator). + + +@my_icon_tags = (); +$my_icon_tags{'next'} = 'Next Page'; +$my_icon_tags{'next_page'} = 'Next Page'; +$my_icon_tags{'previous'} = 'Previous Page'; +$my_icon_tags{'previous_page'} = 'Previous Page'; +$my_icon_tags{'up'} = 'Up One Level'; +$my_icon_tags{'contents'} = 'Contents'; +$my_icon_tags{'index'} = 'Index'; +$my_icon_tags{'modules'} = 'Module Index'; + +@my_icon_names = (); +$my_icon_names{'previous_page'} = 'prev'; +$my_icon_names{'next_page'} = 'next'; + + +sub get_my_icon($) { + my $icon_file; + my $name = @_[0]; + my $text = $my_icon_tags{$name}; + if ($my_icon_names{$name}) { + $name = $my_icon_names{$name}; + } + if ($text eq '') { + $name = 'blank'; + } + $icon_file = $name . "." . $IMAGE_TYPE; + $used_icons{$icon_file} = 1; + return "\"$text\""; +} + + +sub use_my_icon($) { + my $s = @_[0]; + if ($s =~ /\/) { + my $r = get_my_icon($1); + $s =~ s/\/$r/; + } + return $s; +} + + +sub make_top_nav_panel() { + my $s; + $s = ('' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
    $t_title
    " + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
    " + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
    \n" + . "
    \n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub make_bot_nav_panel() { + my $s; + $s = ('
    ' + #. "\n" + . "\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n\n" + # ... and the ``previous'' title + . "\n" + # Similarly with the ``up'' title ... + . "\n" + # If ``next'' section exists, add its title to the navigation panel + . "\n" + . "\n
    $t_title
    " + . ($PREVIOUS_TITLE ? "Previous" : " ") + . "" + . ($UP_TITLE ? "Up" : " ") + . "" + . ($NEXT_TITLE ? "Next" : " ") + . "
    " + . ($PREVIOUS_TITLE ? "$PREVIOUS_TITLE" : " ") + . "" + . ($UP_TITLE ? "$UP_TITLE" : " ") + . "" + . ($NEXT_TITLE ? "$NEXT_TITLE" : " ") + . "
    \n" + . "
    \n" + ); + # remove these; they are unnecessary and cause errors from validation + $s =~ s/ NAME="tex2html\d+"\n */ /g; + return $s; +} + + +sub top_navigation_panel { + return "\n" + . make_top_nav_panel() + . "
    \n"; +} + + +sub bot_navigation_panel { + return "\n

    \n" + . make_bot_nav_panel() + . "\n"; +} + + +#$EXTERNAL_STYLESHEET = "../ASIM.css"; + +$ADDRESS = "Sophie BELLOEIL
    20051116.1"; + +$LOCAL_ICONS = 0; + +$USING_STYLES = 1; + +$TRANSPARENT_FIGURES = 1; + +$WHITE_BACKGROUND = 0; + +$used_icons{"home." . $IMAGE_TYPE} = 1; + +1; # This must be the last line diff --git a/stratus1/doc/stratus/ASIM.css b/stratus1/doc/stratus/ASIM.css new file mode 100644 index 00000000..180cadb3 --- /dev/null +++ b/stratus1/doc/stratus/ASIM.css @@ -0,0 +1,164 @@ + + html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 { + font-size: 100%; + font-family: verdana, sans-serif; + } + + body { + color: black; + background: white; + background-color: white; + background-position: top left; + background-attachment: fixed; + background-repeat: no-repeat; + margin-top: 2em; + margin-right: 10%; + margin-left: 10%; + } + + hr { + height: 1px; + border: 0; + color: #004400; + background-color: #004400; + } + + + h1, h2, h3, h4, h5, h6 { + font-family: verdana, sans-serif; + } + + h1 { text-align: center; } + h2, h3, h4, h5, h6 { text-align: left; + padding-top: 2em; + } + h1, h2, h3 { font-family: "Trebuchet MS", sans-serif; + color: #09550B; + } + h1 { font-weight: bold; font-size: 170%; } + h2 { font-weight: bold; font-size: 140%; } + h3 { font-weight: bold; font-size: 118%; } + h4 { font-weight: bold; font-size: 100%; } + h5 { font-style: italic; font-size: 100%; } + h6 { font-variant: small-caps; font-size: 100%; } + + .hide { + display: none; + color: white; + } + + + div.navigation { margin-bottom: 1em; } + div.navigation h1 { margin-top: 2em; clear: both; } + div.navigation table { margin-left: 2em; font-size: 90%; } + div.navigation img { color: white; border: none; } + + + p { + margin-top: 0.6em; + margin-bottom: 0.6em; + margin-left: 0.0em; + margin-right: 0.0em; + } + + p.copyright { font-size: 90%; } + p.copyright small { font-size: 80%; } + + p.changed { + padding-left: 0.2em; + border-left: solid; + border-top: none; + border-bottom: none; + border-right: none; + border-left-width: thin; + border-color: red; + } + + + address { + text-align: right; + font-weight: bold; + font-style: italic; + font-size: 80%; + } + + + blockquote { + margin-left: 4em; + margin-right: 4em; + margin-top: 0.8em; + margin-bottom: 0.8em; + font-style: italic; + color: #003300; + } + + blockquote p { + margin-bottom: 0; + } + + blockquote address { + margin: 0; + } + + + table { + border-collapse: collapse; + /* + margin-left: 0em; + margin-right: 0em; + */ + margin-top: 0.8em; + margin-bottom: 0.8em; + } + + dt, dd { margin-top: 0; margin-bottom: 0; } + dt { font-weight: bold; } + + + pre, tt, code { + font-family: "andale mono", monospace; + font-size: 100%; + white-space: pre; + } + + pre { + font-size: 80%; + border: solid; + border-width: thin; + border-color: #003300; + background-color: #EEEEEE; + padding: 0.5em; + margin-left: 2em; + margin-right: 2em + } + + tt { color: green; } + em { font-style: italic; font-weight: bold; } + strong { font-weight: bold; } + + span.textit { font-style: italic; } + span.textbf { font-weight: bold; } + + .small { font-size: 90%; } + .white { color: #FFFFFF; } + + + ul.toc { + list-style: disc; + list-style: none; + } + + + a:link img, a:visited img { border-style: none; } + a img { color: white; } + + a:link, a:active, a:visited { + color: #09550B; + text-decoration: none; + } + + a:hover, a:focus { + color: #FF9900; + text-decoration: underline; + } + diff --git a/stratus1/doc/stratus/Makefile.am b/stratus1/doc/stratus/Makefile.am new file mode 100644 index 00000000..6eef8038 --- /dev/null +++ b/stratus1/doc/stratus/Makefile.am @@ -0,0 +1,106 @@ + +SUBDIRS = images + +doc_en_latex_stratusdir = $(datadir)/doc/en/latex/stratus +doc_en_html_stratusdir = $(datadir)/doc/en/html/stratus +doc_en_pdf_stratusdir = $(datadir)/doc/en/pdf/stratus + + +doc_en_stratus_EXTRA = stratus.tex \ + man_new.tex \ + man_alim_connectors.tex \ + man_alim_rail.tex \ + man_arithmetic.tex \ + man_boolean.tex \ + man_buff.tex \ + man_comp.tex \ + man_const.tex \ + man_def_ab.tex \ + man_example.tex \ + man_fill_cell.tex \ + man_generate.tex \ + man_get_ref.tex \ + man_inst.tex \ + man_library.tex \ + man_mux.tex \ + man_net.tex \ + man_pads.tex \ + man_place_bottom.tex \ + man_place_centric.tex \ + man_place_contact.tex \ + man_place_glu.tex \ + man_place_left.tex \ + man_place_ref.tex \ + man_place_right.tex \ + man_place_segment.tex \ + man_place_pin.tex \ + man_place.tex \ + man_place_top.tex \ + man_copy_up_segment.tex \ + man_power_ring.tex \ + man_reg.tex \ + man_resize_ab.tex \ + man_route_ck.tex \ + man_set_ref_ins.tex \ + man_shift.tex \ + man_stratus.tex \ + see_also.tex \ + html.entry \ + ASIM.css \ + .latex2html-init + + +install-data-hook: + @if [ `which latex2html 2>/dev/null` ]; then \ + for file in `ls $(srcdir)/*.tex`; do \ + filename=`basename $$file`; \ + if [ ! -L $$filename -a ! -f $$filename ]; then \ + ln -sf $(srcdir)/$$filename . ; \ + fi ; \ + done ; \ + if [ ! -L ASIM.css -a ! -f ASIM.css ]; then \ + ln -sf $(srcdir)/*.css . ; \ + ln -sf $(srcdir)/.latex2html-init . ; \ + $(mkinstalldirs) images ; \ + ln -sf $(srcdir)/images/*.png ./images/ ; \ + fi ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_latex_stratusdir) ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_latex_stratusdir)/images ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_html_stratusdir) ; \ + $(mkinstalldirs) $(DESTDIR)$(doc_en_pdf_stratusdir) ; \ + cp -r *.tex $(DESTDIR)$(doc_en_latex_stratusdir) ; \ + cp -r *.css $(DESTDIR)$(doc_en_latex_stratusdir) ; \ + cp -r .latex2html-init $(DESTDIR)$(doc_en_latex_stratusdir) ; \ + cp -r images/*.png $(DESTDIR)$(doc_en_latex_stratusdir)/images ; \ + rm -f *.aux *.lof *.log *.out *.toc *.dvi ; \ + latex2html -no_math -html_version 4.0,math -style ./ASIM.css stratus.tex ; \ + cp -pr stratus/* $(DESTDIR)$(doc_en_html_stratusdir) ; \ + cp -p ASIM.css $(DESTDIR)$(doc_en_html_stratusdir)/ASIM.css ; \ + pdflatex stratus.tex ; \ + pdflatex stratus.tex ; \ + cp stratus.pdf $(DESTDIR)$(doc_en_pdf_stratusdir) ; \ + cp $(srcdir)/html.entry $(DESTDIR)$(doc_en_html_stratusdir); \ + if [ -x $(datadir)/doc/en/html/generateIndex.sh ]; then \ + $(datadir)/doc/en/html/generateIndex.sh \ + --prefix=${prefix} --destdir=$(DESTDIR) ; \ + fi ; \ + else \ + echo "[WARNING] latex2html not found, skipping doc generation."; \ + fi + + +EXTRA_DIST = $(doc_en_stratus_EXTRA) + +CLEANFILES = *.dvi \ + *.ps \ + *.lof \ + *.log \ + *.out \ + *.toc \ + *.aux \ + *.bak \ + stratus/*.html \ + stratus/*.css \ + stratus/*.pl \ + stratus/WARNINGS + diff --git a/stratus1/doc/stratus/fichiers/Makefile b/stratus1/doc/stratus/fichiers/Makefile new file mode 100644 index 00000000..2f18881b --- /dev/null +++ b/stratus1/doc/stratus/fichiers/Makefile @@ -0,0 +1,5 @@ +test: + time ./test.py -n 4 + +clean : + rm -f *.vst *.ap *.pyc diff --git a/stratus1/doc/stratus/fichiers/addaccu.py b/stratus1/doc/stratus/fichiers/addaccu.py new file mode 100644 index 00000000..8942c77f --- /dev/null +++ b/stratus1/doc/stratus/fichiers/addaccu.py @@ -0,0 +1,79 @@ +#!/usr/bin/env python + +from stratus import * + +class addaccu ( Model ) : + + def Interface ( self ) : + self.nbit = self._param['nbit'] + + self.a = SignalIn ( "a", self.nbit ) + self.b = SignalIn ( "b", self.nbit ) + self.c = SignalIn ( "c", self.nbit ) + self.v = SignalIn ( "v", 1 ) + self.cmd = SignalIn ( "cmd", 1 ) + + self.cout = SignalOut ( "cout", 1 ) + self.s = SignalOut ( "s", self.nbit ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + d_aux = Signal ( "d_aux", self.nbit ) + e_aux = Signal ( "e_aux", self.nbit ) + ovr = Signal ( "ovr", 1 ) + + + Generate ( "DpgenNand2", "nand2%d" % self.nbit + , param = { 'nbit' : self.nbit + , 'physical' : True + } + ) + temp = Cat ( self.v, self.v, self.v, self.v ) + self.instNand2 = Inst ( "nand2%d" % self.nbit, "instance_nand2" + , map = { 'i0' : temp + , 'i1' : self.a + , 'nq' : d_aux + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + Generate ( "DpgenOr2", "or2%d" % self.nbit + , param = { 'nbit' : self.nbit + , 'physical' : True + } + ) + self.instOr2 = Inst ( "or2%d" % self.nbit, "instance_or2" + , map = { 'i0' : d_aux + , 'i1' : self.b + , 'q' : e_aux + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + Generate ( "DpgenAdsb2f", "adder%d" % self.nbit + , param = { 'nbit' : self.nbit + , 'physical' : True + } + ) + self.instAdd2 = Inst ( "adder%d" % self.nbit, "instance_add2" + , map = { 'i0' : e_aux + , 'i1' : self.c + , 'q' : self.s + , 'add_sub' : self.cmd + , 'c31' : self.cout + , 'c30' : ovr + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + Place ( self.instNand2, NOSYM, XY ( 0, 0 ) ) + PlaceRight ( self.instOr2, NOSYM ) + PlaceRight ( self.instAdd2, NOSYM ) + + diff --git a/stratus1/doc/stratus/fichiers/test.py b/stratus1/doc/stratus/fichiers/test.py new file mode 100755 index 00000000..08461e93 --- /dev/null +++ b/stratus1/doc/stratus/fichiers/test.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python + +from stratus import * +from addaccu import addaccu + +nbit = Param ( "n" ) + +dict = { 'nbit' : nbit } + +inst_addaccu = addaccu ( "inst_addaccu", dict ) + +inst_addaccu.Interface() +inst_addaccu.Netlist() +inst_addaccu.Layout() +inst_addaccu.View() + +inst_addaccu.Save ( PHYSICAL ) + + diff --git a/stratus1/doc/stratus/html.entry b/stratus1/doc/stratus/html.entry new file mode 100644 index 00000000..239ad936 --- /dev/null +++ b/stratus1/doc/stratus/html.entry @@ -0,0 +1 @@ +

  • Stratus
    Netlist / Layout description language

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zvajnS5flHu=Sp1j@poH-JXMAPlvrS_T~TR&zC9vZdpq53fi#qA<;I6WCEsM4FVN?c z94&M9yTeL~al6UN61en6UcWV2X)7CR@4&tpBS4}2JGN2F={Ma(Q@fyZ>In=JVO3(P zvby!P8P$ss&TU>!7ioz`#ULdG(@;|XDMo*cwIwTkbG8475I7#9V@5KA`oWenVrk<7o}nz*Zp zfg=Cdr=Yu7-5;=FubiDh=tG*BRrZ<Md(u6p-NqUR(OTENnw>_AsCLV) zZuPSZIHz+VmXyywhsw{Rl>hzyg%f%H#NQ zVcg`1_JZN&Tp(v>s59s=#ohqfgy}8DF=Dk67=(%Mtoyx!TcbmNF(ghw74(Vx__!td zA3UVk_ge6<@gcbW^*s!&fw=QgedF=TPZfD(o^F9acB?v$z;5#+>!gnT5vR#8Z7krl zP1dM+Tc@h?z(GfWF@igkKzhHB + \item \verb-connectmap- : Connexions in order to make the netlist\\ +\end{itemize} +\indent \verb-param- and \verb-map- are dictionnaries as shown in the example below. + +\subsubsection{Example} + +\begin{verbatim} +Inst ( 'a2_x2' + , map = { 'i0' : in0 + , 'i1' : in1 + , 'q' : out + , 'vdd' : vdd + , 'vss' : vss + } + ) +\end{verbatim} + +\begin{htmlonly} +You can see a concrete example at : \hyperref[ref]{\emph{Example}}{}{Example}{secexample} +\end{htmlonly} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-Error in Inst : the model Model does not exist.-\\\verb-Check CRL_CATA_LIB.-\\Either one has made a mistake in the name of the model, either the environment variable is not correct. + \item \verb-Error in Inst : port does not exist in model Model.-\\One port in map is not correct. + \item \verb-Error in Inst : one input net is not dimensionned.-\\The size of the output nets is automatically calculated bus the input nets must be dimensionned before being connected. +\end{itemize} + +\begin{htmlonly} +\input{see_also} +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_library.tex b/stratus1/doc/stratus/man_library.tex new file mode 100644 index 00000000..66e78355 --- /dev/null +++ b/stratus1/doc/stratus/man_library.tex @@ -0,0 +1,96 @@ +\subsubsection{Description} + +The virtual library permits to create a cell and map it to different libraries without having to change it. + +\subsubsection{List of the generators provided} + +\begin{itemize} + \item \verb-a2- : \verb-q <= i0 & i1- + \item \verb-a3- : \verb-q <= i0 & i1 & i2- + \item \verb-a4- : \verb-q <= i0 & i1 & i2 & i3- + \item \verb-na2- : \verb-nq <= ~ ( i0 & i1 )- + \item \verb-na3- : \verb-nq <= ~ ( i0 & i1 & i2 )- + \item \verb-na4- : \verb-nq <= ~ ( i0 & i1 & i2 & i3 )- + \item \verb-o2- : \verb-q <= i0 & i1- + \item \verb-o3- : \verb-q <= i0 & i1 & i2- + \item \verb-o4- : \verb-q <= i0 & i1 & i2 & i3- + \item \verb-no2- : \verb-nq <= ~ ( i0 & i1 )- + \item \verb-no3- : \verb-nq <= ~ ( i0 & i1 & i2 )- + \item \verb-no4- : \verb-nq <= ~ ( i0 & i1 & i2 & i3 )- + \item \verb-inv- : \verb-nq <= ~ i- + \item \verb-buf- : \verb-q <= i- + \item \verb-xr2- : \verb-q <= i0 ^ i1- + \item \verb-nxr2- : \verb-nq <= ~ ( i0 ^ i1 )- + \item \verb-zero- : \verb-nq <= '0'- + \item \verb-one- : \verb-q <= '1'- + \item \verb-halfadder- : \verb-sout <= a ^ b- and \verb-cout <= a & b- + \item \verb-fulladder- : \verb-sout <= a ^ b ^ cin-\\\indent and \verb-cout <= ( a & b ) | ( a & cin ) | ( b & cin )- + \item \verb-mx2- : \verb-q <= (i0 & ~cmd) | (i1 & cmd)- + \item \verb-nmx2- : \verb-nq <= ~( (i0 & ~cmd) | (i1 & cmd) )- + \item \verb-sff- : \verb-if RISE ( ck ) : q <= i- + \item \verb-sff2- : \verb-if RISE ( ck ) : q <= (i0 & ~cmd) | (i1 & cmd)- + \item \verb-sff3- : \verb-if RISE ( ck ) :-\\\verb- q <= (i0 & ~cmd0) | (((i1 & cmd1)|(i2&~cmd1)) & cmd0)- + \item \verb-ts- : \verb-if cmd : q <= i- + \item \verb-nts- : \verb-if cmd : nq <= ~i- +\end{itemize} + +\subsubsection{Mapping file} + +The virtual library is mapped to the sxlib library. A piece of the corresponding mapping file is shown below.\\ +\indent In order to map the virtual library to another library, on has to write a .xml file which makes correspond models and interfaces.\\ +\indent Note that the interfaces of the cells must be the same (except for the names of the ports). Otherwise, one has to create .vst file in order to make the interfaces match.\\ + +\indent The environment variable used to point the right file is \verb-STRATUS_MAPPING_NAME-. + +\begin{figure}[h!] +%\centering +\includegraphics[width=1\textwidth]{images/xml.png} +\end{figure} + +\subsubsection{Generators} + +Some generators are also provided in order to use the cells of the library with nets of more than 1 bit. One has to upper the first letter of the model name in order to user those generators. What is simply done is a for loop with the bits of the nets. The parameter \verb-'nbit'- gives the size of the generator. + +\subsubsection{Example} + +\begin{itemize} + \item Direct instanciation of a cell +\end{itemize} +\begin{verbatim} +for i in range ( 4 ) : + Inst ( 'a2' + , map = { 'i0' : neti0[i] + , 'i1' : neti1[i] + , 'q' : netq[i] + , 'vdd' : netvdd + , 'vss' : netvss + } + ) +\end{verbatim} + +\begin{itemize} + \item Instanciation of a generator +\end{itemize} +\begin{verbatim} +Generate ( 'A2', "my_and2_4bits", param = { 'nbit' : 4 } ) +Inst ( 'my_and2_4bits' + , map = { 'i0' : neti0 + , 'i1' : neti1 + , 'q' : netq + , 'vdd' : vdd + , 'vss' : vss + } + ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Inst : the model ... does not exist.-\\\verb-Check CRL_CATA_LIB.-\\The model of the cell has not been found. One has to check the environment variable. + \item \verb-[Stratus ERROR] Virtual library : No file found in order to parse.-\\\verb-Check STRATUS_MAPPING_NAME.-\\The mapping file is not given in the environment variable. +\end{itemize} + +\begin{htmlonly} +\input{see_also} +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_mux.tex b/stratus1/doc/stratus/man_mux.tex new file mode 100644 index 00000000..a1e8320b --- /dev/null +++ b/stratus1/doc/stratus/man_mux.tex @@ -0,0 +1,135 @@ +\subsubsection{Name} + +Mux -- Easy way to instantiate a multiplexor + +\subsubsection{Synopsys} + +\begin{verbatim} +netOut <= netCmd.Mux ( arg ) +\end{verbatim} + +\subsubsection{Description} + +This method is a method of net. The net which this method is applied to is the command of the multiplexor. The nets given as parameters are all the input nets. This method returns a net : the output net.\\ +There are two ways to describe the multiplexor : the argument \verb-arg- can be a list or a dictionnary.\\ +\indent Note that it is possible to change the generator instanciated with the \verb-SetMux- method. + +\subsubsection{Parameters} + +\begin{itemize} + \item List :\\ + \indent For each value of the command, the corresponding net is specified. All values must be specified.\\ + \indent For example : + \begin{verbatim} +out <= cmd.Mux ( [in0, in1, in2, in3] ) + \end{verbatim} + \indent The net out is then initialised like this : + \begin{verbatim} +if cmd == 0 : out <= in0 +if cmd == 1 : out <= in1 +if cmd == 2 : out <= in2 +if cmd == 3 : out <= in3 + \end{verbatim} + \item Dictionnary :\\ + \indent A dictionnary makes the correspondance between a value of the command and the corresponding net.\\ + \indent For example : + \begin{verbatim} +out <= cmd.Mux ( {"0" : in0, "1" : in1, "2" : in2, "3" : in3} ) + \end{verbatim} + \indent This initialisation corresponds to the one before. + \indent Thanks to the use of a dictionnary, the connections can be clearer : + \begin{itemize} + \item \verb-'default'-: This key of the dictionnary corresponds to all the nets that are not specified\\ + For example : + \begin{verbatim} +out <= cmd.Mux ( {"0" : in0, "default" : in1} ) + \end{verbatim} + This notation corresponds to : + \begin{verbatim} +if cmd == 0 : out <= in0 +else : out <= in1 + \end{verbatim} + Note that if there is no \verb-'default'- key specified and that not all the nets are specified, the non specified nets are set to 0. + \item \verb-#- and \verb-?- : When a key of the dictionnary begins with \verb-#-, the number after the \verb-#- has to be binary and each ? in the number means that this bit is not precised\\ + For example : + \begin{verbatim} +out <= cmd.Mux ( {"#01?" : in0, "default" : in1} ) + \end{verbatim} + This notation corresponds to : + \begin{verbatim} +if cmd in ( 2, 3 ) : out <= in0 +else : out <= in1 + \end{verbatim} + \item \verb-,- and \verb"-" : When keys contains thoses symbols, it permits to enumerate intervals\\ + For example : + \begin{verbatim} +out <= cmd.Mux ( {"0,4" : in0, "1-3,5" : in1} ) + \end{verbatim} + This notation corresponds to : + \begin{verbatim} +if cmd in ( 0, 4 ) : out <= in0 +elif cmd in ( 1, 2, 3, 5) : out <= in1 +else : out <= 0 + \end{verbatim} + \end{itemize} +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = SignalIn ( "a", 4 ) + self.B = SignalIn ( "b", 4 ) + self.C = SignalIn ( "c", 4 ) + self.D = SignalIn ( "d", 4 ) + + self.Cmd1 = SignalIn ( "cmd1", 2 ) + self.Cmd2 = SignalIn ( "cmd2", 4 ) + + self.S1 = SignalOut ( "s1", 4 ) + self.S2 = SignalOut ( "s2", 4 ) + + self.Vdd = VddIn ( "vdd" ) + self.Vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S1 <= self.Cmd1.Mux ( [sefl.A, self.B, self.C, self.D] ) + + self.S2 <= self.Cmd2.Mux ( { "0" : self.A + , "1,5-7" : self.B + , "#1?1?" : self.C + , "default" : self.D + } ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Mux : all the nets must have the same lenght.-\\All the input nets pust have the same lenght. + \item \verb-[Stratus ERROR] Mux : there are no input nets.-\\The input nets seem to have been forgotten. + \item \verb-[Stratus ERROR] Mux : wrong argument type.-\\The connections of the buses are not described by a list nor a dictionnary. + \item \verb-[Stratus ERROR] Mux :-\\\verb-the number of nets does not match with the lenght of the command.-\\When using a list, the number of nets has to correspond to the number of possible values of the command. + \item \verb-[Stratus ERROR] Mux : wrong key.-\\One of the key of the dictionnary is not un number, neither a list or an interval. + \item \verb-[Stratus ERROR] Mux :-\\\verb-when an interval is specified, the second number of the interval-\\\verb-must be greater than the first one.-\\When creating an interval with "-", the second number has to be greater than the first one. + \item \verb-[Stratus ERROR] Mux :-\\\verb-the binary number does not match with the lenght of the command.-\\When using the \verb-#- notation, each digit of the binary number corresponds to a wire of the cmd. The leghts have to correspond. + \item \verb-[Stratus ERROR] Mux : after #, the number has to be binary.-\\When using the \verb-#- notation, the number has to be binary : one can use 0, 1 or ?. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a shifter}}{}{Shifter}{secshift} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_net.tex b/stratus1/doc/stratus/man_net.tex new file mode 100644 index 00000000..b85d9108 --- /dev/null +++ b/stratus1/doc/stratus/man_net.tex @@ -0,0 +1,118 @@ +\subsubsection{Name} + +SignalIn, SignalOut ... -- Creation of nets + +\subsubsection{Synopsys} + +\begin{verbatim} +netA = SignalIn ( "a", 4 ) +\end{verbatim} + +\subsubsection{Description} + +How to create and use nets. + +\subsubsection{Nets} + +Differents kind of nets are listed below : +\begin{itemize} + \item \verb-SignalIn- : Creation of an input port + \item \verb-SignalOut- : Creation of an output port + \item \verb-SignalInOut- : Creation of an inout port + \item \verb-SignalUnknown- : Creation of an input/output port which direction is not defined + \item \verb-TriState- : Creation of a tristate port + \item \verb-CkIn- : Creation of a clock port + \item \verb-VddIn- : Creation of the vdd alimentation + \item \verb-VssIn- : Creation of the vss alimentation + \item \verb-Signal- : Creation of an internal net +\end{itemize} + +\subsubsection{Parameters} + +All kind of constructors have the same parameters : +\begin{itemize} + \item \verb-name- : the name of the net (mandatory argument) + \item \verb-arity- : the arity of the net (mandatory argument) + \item \verb-indice- : for bit vectors only : the LSB bit (optional argument : set to 0 by default) +\end{itemize} + +\indent Only \verb-CkIn-, \verb-VddIn- and \verb-VssIn- do not have the same parameters : there is only the \verb-name- parameter (they are 1 bit nets). + +\subsubsection{Functions and methods} + +Some functions/methods are provided in order to handle nets : +\begin{itemize} + \item function \verb-Cat- : Concatenation of nets, beginning with the MSB +\begin{verbatim} +Inst ( 'DpgenInv' + , map = { 'i0' : Cat ( A, B ) + , 'nq' : S + , 'vdd' : vdd + , 'vss' : vss + } + ) +\end{verbatim} +\indent Or : +\begin{verbatim} +tab = [] +tab.append ( A ) +tab.append ( B ) + +Inst ( 'DpgenInv' + , map = { 'i0' : Cat ( tab ) + , 'nq' : S + , 'vdd' : vdd + , 'vss' : vss + } + ) +\end{verbatim} +\indent If A and B are 2 bits nets, the net \verb-myNet- will be such as : +\begin{verbatim} +myNet[3] = A[1] +myNet[2] = A[0] +myNet[1] = B[1] +myNet[0] = B[0] +\end{verbatim} + \item function \verb-Extend- : Creation of a net which is an extension of the net which it is applied to +\begin{verbatim} +temp = Signal ( "temp", 5 ) +tempExt = Signal ( "temp_ext", 8 ) + +tempExt <= temp.Extand ( 8, 'one' ) +\end{verbatim} + \item method \verb-Alias- : Creation of an alias name for a net +\begin{verbatim} +cin.Alias ( c_temp[0] ) +cout.Alias ( c_temp[4] ) +for i in range ( 4 ) : + Inst ( "Fulladder" + , map = { 'a' : a[i] + , 'b' : b[i] + , 'cin' : c_temp[i] + , 'sout' : sout[i] + , 'cout' : c_temp[i+1] + , 'vdd' : vdd + , 'vss' : vss + } + ) +\end{verbatim} +\end{itemize} + +\begin{htmlonly} + +\subsubsection{Example} + +You can see a concrete example at : \hyperref[ref]{\emph{Example}}{}{Example}{secexample} + +\end{htmlonly} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-Error in SignalIn :-\\\verb-the lenght of the net must be a positive value.-\\One can not create a net with a negative lenght. +\end{itemize} + +\begin{htmlonly} +\input{see_also} +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_new.tex b/stratus1/doc/stratus/man_new.tex new file mode 100644 index 00000000..9581f186 --- /dev/null +++ b/stratus1/doc/stratus/man_new.tex @@ -0,0 +1,15 @@ + \subsection{march 2007} + +A modification has been done to the virtual library. The name of the cells have been changed in order to be synchronised with the sxlib cells.\\ +\indent Two utilizations can be done with the cells of the virtual library : wether direct instanciation of 1 bit cells, wether use of a generator (same model name with the first letter uppered) in order to have several bits cells. + + \subsection{mai 2006} + +First of all, the modifications made to stratus make all files created for version 2.0 deprecated, and unusable with this version 3.0.\\ +\indent All following releases will be improvements, and not major changements.\\ + +\begin{itemize} + \item The main modification is the new funtion \verb-Generate- : this function is used to generate generators before their instanciation.\\ + \item One other modification is the type of arguments of function \verb-Place- : it no longer takes x and y coordinates but a \verb-XY- object (which is a point (x, y) ).\\ + \item Some improvements are also added for layout : the creation of segments, contacts, and references. +\end{itemize} diff --git a/stratus1/doc/stratus/man_pads.tex b/stratus1/doc/stratus/man_pads.tex new file mode 100644 index 00000000..b4f8f5d3 --- /dev/null +++ b/stratus1/doc/stratus/man_pads.tex @@ -0,0 +1,56 @@ +\subsubsection{Name} + +PadNorth, PadSouth, PadEast, PasWest -- Placement of pads at the periphery of the cell + +\subsubsection{Synopsys} + +\begin{verbatim} +PadNorth ( args ) +\end{verbatim} + +\subsubsection{Description} + +These functions place the pads given as arguments at the given side of the cell (PadNorth : up north, PadSouth : down south ...). +Pads are placed from bottom to top for PadNorth and PadSouth and from left to right for PadWest and PasEast. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-args- : List of pads to be placed +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +PadSouth ( self.p_cin, self.p_np, self.p_ng, self.p_vssick0 + , self.p_vddeck0, self.p_vsseck1, self.p_vddeck1, self.p_cout + , self.p_y[0], self.p_y[1], self.p_y[2] + ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PadNorth : not enough space for all pads.-\\The abutment box is not big enough in order to place all the pads. Maybe one could put pads on other faces of the cell. + \item \verb-[Stratus ERROR] PadNorth : one instance doesn't exist.-\\One of the pads given as arguments does not exist + \item \verb-[Stratus ERROR] PadNorth : one argument is not an instance.-\\One of the pads is not one of the pads of the cell. + \item \verb-[Stratus ERROR] PadNorth : the instance ins is already placed.-\\One is trying to place a pad twice. + \item \verb-[Stratus ERROR] PadNorth : pad ins must be closer to the center.-\\The pad name ins must be put closer to the center in order to route the cell +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place.tex b/stratus1/doc/stratus/man_place.tex new file mode 100644 index 00000000..27c4cfa7 --- /dev/null +++ b/stratus1/doc/stratus/man_place.tex @@ -0,0 +1,64 @@ +\subsubsection{Name} + +Place -- Places an instance + +\subsubsection{Synopsys} + +\begin{verbatim} +Place ( ins, sym, point ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist-, in order to use the \verb-Place- function. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-point- : coordinates of the lower left corner of the abutment box of the instance in the current figure. +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst, NOSYM, XY ( 0, 0 ) ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] Place : wrong argument for placement type.-\\The symetry given as argument is not correct. + \item \verb-[Stratus ERROR] Place : wrong argument for placement,-\\\verb- the coordinates must be put in a XY object.-\\The coordinates are not descrobed the bood way. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_bottom.tex b/stratus1/doc/stratus/man_place_bottom.tex new file mode 100644 index 00000000..8d767d3c --- /dev/null +++ b/stratus1/doc/stratus/man_place_bottom.tex @@ -0,0 +1,68 @@ +\subsubsection{Name} + +PlaceBottom -- Places an instance below the "reference instance" + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceBottom ( ins, sym, offsetX, offsetY ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use the \verb-PlaceTop- function.\\ + +\indent The top left corner of the abutment box of the instance is placed, after beeing symetrized and/or rotated, toward the bottom left corner of the abutment box of the "reference instance". The newly placed instance becomes the "reference instance". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-offsetX- (optionnal) : An offset is put horizontally. The value given as argument must be a multiple of PITCH + \item \verb-offsetY- (optionnal) : An offset is put vertically. The value given as argument must be a multiple of SLICE +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceBottom ( myInst2, SYM_Y ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] PlaceBottom : no previous instance.-\\One can use \verb-PlaceBottom- only if a reference instance exist. Use a \verb-Place- call before. + \item \verb-[Stratus ERROR] PlaceBottom : wrong argument for placement type.-\\The symetry given as argument is not correct. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_centric.tex b/stratus1/doc/stratus/man_place_centric.tex new file mode 100644 index 00000000..86bc02ea --- /dev/null +++ b/stratus1/doc/stratus/man_place_centric.tex @@ -0,0 +1,50 @@ +\subsubsection{Name} + +PlaceCentric -- Placement of an instance in the middle of an abutment box + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceCentric ( ins ) +\end{verbatim} + +\subsubsection{Description} + +This function places an instance in the middle of and abutment box.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use this function. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place +\end{itemize} + +%\subsubsection{Example} +% +%\begin{verbatim} +%PlaceCentric ( core ) +%\end{verbatim} +% +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PlaceCentric: the instance does not exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] PlaceCentric :-\\\verb-the instance's size is greater than this model.-\\The instance must fit in the abutment box. The abutment box may not be big enough. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_contact.tex b/stratus1/doc/stratus/man_place_contact.tex new file mode 100644 index 00000000..155f1864 --- /dev/null +++ b/stratus1/doc/stratus/man_place_contact.tex @@ -0,0 +1,56 @@ +\subsubsection{Name} + +PlaceContact -- Places a contact + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceContact ( net, layer, point, width, height ) +\end{verbatim} + +\subsubsection{Description} + +Placement of a contact.\\ +\indent The contact is located at the coodinates of \verb-point-, on the layer \verb-layer- and has a size of 1 per 1. It belongs to the net \verb-net-.\\ +\indent Note that the segment must be horizontal or vertival. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-net- : Net which the contact belongs to + \item \verb-layer- : Layer of the segment.\\The \verb-layer- argument is a string wich can take different values, thanks to the technology (file described in HUR\_TECHNO\_NAME) + \begin{itemize} + \item NWELL, PWELL, ptie, ntie, pdif, ndif, ntrans, ptrans, poly, ALU1, ALU2, ALU3, ALU4, ALU5, ALU6, VIA1, VIA2, VIA3, VIA4, VIA5, TEXT, UNDEF, SPL1, TALU1, TALU2, TALU3, TALU4, TALU5, TALU6, POLY, NTIE, PTIE, NDIF, PDIF, PTRANS, NTRANS, CALU1, CALU2, CALU3, CALU4, CALU5, CALU6, CONT\_POLY, CONT\_DIF\_N, CONT\_DIF\_P, CONT\_BODY\_N, CONT\_BODY\_P, via12, via23, via34, via45, via56, via24, via25, via26, via35, via36, via46, CONT\_TURN1, CONT\_TURN2, CONT\_TURN3, CONT\_TURN4, CONT\_TURN5, CONT\_TURN6 + \end{itemize} + \item \verb-point- : Coodinates of the contact + \item \verb-width- : Width of the contact + \item \verb-height- : Height of the contact +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +PlaceContact ( myNet, "ALU2", XY (10, 0), 2, 2 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PlaceContact : Argument layer must be a string.- + \item \verb-[Stratus ERROR] PlaceContact : Wrong argument,-\\\verb-the coordinates of the contact must be put in a XY object.- +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceSegment}}{}{PlaceSegment}{secsegment} +\hyperref[ref]{\emph{PlacePin}}{}{PlacePin}{secpin} +\hyperref[ref]{\emph{PlaceRef}}{}{PlaceRef}{secref} +\hyperref[ref]{\emph{GetRefXY}}{}{GetRefXY}{secgetref} +\hyperref[ref]{\emph{CopyUpSegment}}{}{CopyUpSegment}{seccopy} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_glu.tex b/stratus1/doc/stratus/man_place_glu.tex new file mode 100644 index 00000000..d4c3cfbd --- /dev/null +++ b/stratus1/doc/stratus/man_place_glu.tex @@ -0,0 +1,42 @@ +\subsubsection{Name} + +PlaceGlue -- Automatic placement of non placed instances + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceGlue ( cell ) +\end{verbatim} + +\subsubsection{Description} + +This function places, thanks to the automatic placer Mistral of Coriolis, all the non placed instances of the cell. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-cell- : the cell which the fonction is applied to +\end{itemize} + +%\subsubsection{Example} +% +%\begin{verbatim} +%PlaceGlue ( core ) +%\end{verbatim} +% + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_left.tex b/stratus1/doc/stratus/man_place_left.tex new file mode 100644 index 00000000..0bef031b --- /dev/null +++ b/stratus1/doc/stratus/man_place_left.tex @@ -0,0 +1,68 @@ +\subsubsection{Name} + +PlaceLeft -- Places an instance at the left of the "reference instance" + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceLeft ( ins, sym, offsetX, offsetY ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use the \verb-PlaceTop- function.\\ + +\indent The bottom right corner of the abutment box of the instance is placed, after beeing symetrized and/or rotated, toward the bottom left corner of the abutment box of the "reference instance". The newly placed instance becomes the "reference instance". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-offsetX- (optionnal) : An offset is put horizontally. The value given as argument must be a multiple of PITCH + \item \verb-offsetY- (optionnal) : An offset is put vertically. The value given as argument must be a multiple of SLICE +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceLeft ( myInst2, NOSYM ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] PlaceLeft : no previous instance.-\\One can use \verb-PlaceLeft- only if a reference instance exist. Use a \verb-Place- call before. + \item \verb-[Stratus ERROR] PlaceLeft : wrong argument for placement type.-\\The symetry given as argument is not correct. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_pin.tex b/stratus1/doc/stratus/man_place_pin.tex new file mode 100644 index 00000000..9455055a --- /dev/null +++ b/stratus1/doc/stratus/man_place_pin.tex @@ -0,0 +1,60 @@ +\subsubsection{Name} + +PlacePin -- Places a pin + +\subsubsection{Synopsys} + +\begin{verbatim} +PlacePin ( net, layer, direction, point, width, height ) +\end{verbatim} + +\subsubsection{Description} + +Placement of a pin.\\ +\indent The pin is located at the coodinates of \verb-point-, on the layer \verb-layer-, has a a direction of \verb-direction- and size of 1 per 1. It belongs to the net \verb-net-. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-net- : Net which the pin belongs to + \item \verb-layer- : Layer of the segment.\\The \verb-layer- argument is a string wich can take different values, thanks to the technology (file described in HUR\_TECHNO\_NAME) + \begin{itemize} + \item NWELL, PWELL, ptie, ntie, pdif, ndif, ntrans, ptrans, poly, ALU1, ALU2, ALU3, ALU4, ALU5, ALU6, VIA1, VIA2, VIA3, VIA4, VIA5, TEXT, UNDEF, SPL1, TALU1, TALU2, TALU3, TALU4, TALU5, TALU6, POLY, NTIE, PTIE, NDIF, PDIF, PTRANS, NTRANS, CALU1, CALU2, CALU3, CALU4, CALU5, CALU6, CONT\_POLY, CONT\_DIF\_N, CONT\_DIF\_P, CONT\_BODY\_N, CONT\_BODY\_P, via12, via23, via34, via45, via56, via24, via25, via26, via35, via36, via46, CONT\_TURN1, CONT\_TURN2, CONT\_TURN3, CONT\_TURN4, CONT\_TURN5, CONT\_TURN6 + \end{itemize} + \item \verb-direction- : Direction of the pin + \begin{itemize} + \item UNDEFINED, NORTH, SOUTH, EAST, WEST + \end{itemize} + \item \verb-point- : Coodinates of the pin + \item \verb-width- : Width of the pin + \item \verb-height- : Height of the pin +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +PlacePin ( myNet, "ALU2", NORTH, XY (10, 0), 2, 2 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PlacePin : Argument layer must be a string.- + \item \verb-[Stratus ERROR] PlacePin : Illegal pin access direction.-\\\verb-The values are : UNDEFINED, NORTH, SOUTH, EAST, WEST.- + \item \verb-[Stratus ERROR] PlacePin : Wrong argument,-\\\verb-the coordinates of the pin must be put in a XY object.- +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceSegment}}{}{PlaceSegment}{secsegment} +\hyperref[ref]{\emph{PlaceContact}}{}{PlaceContact}{seccontact} +\hyperref[ref]{\emph{PlaceRef}}{}{PlaceRef}{secref} +\hyperref[ref]{\emph{GetRefXY}}{}{GetRefXY}{secgetref} +\hyperref[ref]{\emph{CopyUpSegment}}{}{CopyUpSegment}{seccopy} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_ref.tex b/stratus1/doc/stratus/man_place_ref.tex new file mode 100644 index 00000000..bb842d88 --- /dev/null +++ b/stratus1/doc/stratus/man_place_ref.tex @@ -0,0 +1,49 @@ +\subsubsection{Name} + +PlaceRef -- Places a reference + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceRef ( point, name ) +\end{verbatim} + +\subsubsection{Description} + +Placement of a reference.\\ +\indent The reference is located at the coordinates of \verb-point-, with name \verb-name-. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-point- : Coodinates of the reference + \item \verb-name- : Name of the reference +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +PlaceRef ( XY (10, 0), "myref" ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PlaceRef : Wrong argument,-\\\verb-the coordinates of the reference must be put in a XY object.- + \item \verb-[Stratus ERROR] PlaceRef : Argument layer must be a string.- +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceSegment}}{}{PlaceSegment}{secsegment} +\hyperref[ref]{\emph{PlaceContact}}{}{PlaceContact}{seccontact} +\hyperref[ref]{\emph{PlacePin}}{}{PlacePin}{secpin} +\hyperref[ref]{\emph{GetRefXY}}{}{GetRefXY}{secgetref} +\hyperref[ref]{\emph{CopyUpSegment}}{}{CopyUpSegment}{seccopy} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_right.tex b/stratus1/doc/stratus/man_place_right.tex new file mode 100644 index 00000000..24b31b7c --- /dev/null +++ b/stratus1/doc/stratus/man_place_right.tex @@ -0,0 +1,68 @@ +\subsubsection{Name} + +PlaceRight -- Places an instance at the right of the "reference instance" + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceRight ( ins, sym, offsetX, offsetY ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use the \verb-PlaceTop- function.\\ + +\indent The bottom left corner of the abutment box of the instance is placed, after beeing symetrized and/or rotated, toward the bottom right corner of the abutment box of the "reference instance". The newly placed instance becomes the "reference instance". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-offsetX- (optionnal) : An offset is put horizontally. The value given as argument must be a multiple of PITCH + \item \verb-offsetY- (optionnal) : An offset is put vertically. The value given as argument must be a multiple of SLICE +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceRight ( myInst2, NOSYM ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] PlaceRight : no previous instance.-\\One can use \verb-PlaceRight- only if a reference instance exist. Use a \verb-Place- call before. + \item \verb-[Stratus ERROR] PlaceRight : wrong argument for placement type.-\\The symetry given as argument is not correct. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_segment.tex b/stratus1/doc/stratus/man_place_segment.tex new file mode 100644 index 00000000..b697d3c1 --- /dev/null +++ b/stratus1/doc/stratus/man_place_segment.tex @@ -0,0 +1,55 @@ +\subsubsection{Name} + +PlaceSegment -- Places a segment + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceSegment ( net, layer, point1, point2, width ) +\end{verbatim} + +\subsubsection{Description} + +Placement of a segment.\\ +\indent The segment is created between \verb-point1- and \verb-point2- on the layer \verb-layer- and with width \verb-width-. It belongs to the net \verb-net-.\\ +\indent Note that the segment must be horizontal or vertival. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-net- : Net which the segment belongs to + \item \verb-layer- : Layer of the segment.\\The \verb-layer- argument is a string wich can take different values, thanks to the technology (file described in HUR\_TECHNO\_NAME) + \begin{itemize} + \item NWELL, PWELL, ptie, ntie, pdif, ndif, ntrans, ptrans, poly, ALU1, ALU2, ALU3, ALU4, ALU5, ALU6, VIA1, VIA2, VIA3, VIA4, VIA5, TEXT, UNDEF, SPL1, TALU1, TALU2, TALU3, TALU4, TALU5, TALU6, POLY, NTIE, PTIE, NDIF, PDIF, PTRANS, NTRANS, CALU1, CALU2, CALU3, CALU4, CALU5, CALU6, CONT\_POLY, CONT\_DIF\_N, CONT\_DIF\_P, CONT\_BODY\_N, CONT\_BODY\_P, via12, via23, via34, via45, via56, via24, via25, via26, via35, via36, via46, CONT\_TURN1, CONT\_TURN2, CONT\_TURN3, CONT\_TURN4, CONT\_TURN5, CONT\_TURN6 + \end{itemize} + \item \verb-point1-, \verb-point2- : The segment is created between those two points +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +PlaceSegment ( myNet, "ALU3", XY (10, 0), XY (10, 100), 2 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PlaceSegment : Argument layer must be a string.- + \item \verb-[Stratus ERROR] PlaceSegment : Wrong argument,-\\\verb-the coordinates of the segment must be put in XY objects.- + \item \verb-[Stratus ERROR] PlaceSegment : Segments are vertical or horizontal.-\\The two references given as argument do not describe a vertical or horizontal segment. Wether coordinate x or y of the references must be identical. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceContact}}{}{PlaceContact}{seccontact} +\hyperref[ref]{\emph{PlacePin}}{}{PlacePin}{secpin} +\hyperref[ref]{\emph{PlaceRef}}{}{PlaceRef}{secref} +\hyperref[ref]{\emph{GetRefXY}}{}{GetRefXY}{secgetref} +\hyperref[ref]]{\emph{CopyUpSegment}}{}{CopyUpSegment}{seccopy} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_place_top.tex b/stratus1/doc/stratus/man_place_top.tex new file mode 100644 index 00000000..95d83ccc --- /dev/null +++ b/stratus1/doc/stratus/man_place_top.tex @@ -0,0 +1,68 @@ +\subsubsection{Name} + +PlaceTop -- Places an instance at the top of the "reference instance" + +\subsubsection{Synopsys} + +\begin{verbatim} +PlaceTop ( ins, sym, offsetX, offsetY ) +\end{verbatim} + +\subsubsection{Description} + +Placement of an instance.\\ +\indent The instance has to be instantiated in the method \verb-Netlist- in order to use the \verb-PlaceTop- function.\\ + +\indent The bottom left corner of the abutment box of the instance is placed, after beeing symetrized and/or rotated, toward the top left corner of the abutment box of the "reference instance". The newly placed instance becomes the "reference instance". + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : Instance to place. + \item \verb-sym- : Geometrical operation to be performed on the instance before beeing placed.\\The \verb-sym- argument can take eight legal values : + \begin{itemize} + \item \verb-NOSYM- : no geometrical operation is performed + \item \verb-SYM_Y- : Y becomes -Y, that means toward X axe symetry + \item \verb-SYM_X- : X becomes -X, that means toward Y axe symetry + \item \verb-SYMXY- : X becomes -X, Y becomes -Y + \item \verb-ROT_P- : a positive 90 degrees rotation takes place + \item \verb-ROT_M- : a negative 90 degrees rotation takes place + \item \verb-SY_RP- : Y becomes -Y, and then a positive 90 degrees rotation takes place + \item \verb-SY_RM- : Y becomes -Y, and then a negative 90 degrees rotation takes place + \end{itemize} + \item \verb-offsetX- (optionnal) : An offset is put horizontally. The value given as argument must be a multiple of PITCH + \item \verb-offsetY- (optionnal) : An offset is put vertically. The value given as argument must be a multiple of SLICE +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceTop ( myInst2, SYM_Y ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Placement : the instance doesn't exist.-\\The instance must be instanciated in order to be placed. + \item \verb-[Stratus ERROR] Placement : the first argument is not an instance.- + \item \verb-[Stratus ERROR] Placement : the instance is already placed.-\\One can not place an instance twice + \item \verb-[Stratus ERROR] PlaceTop : no previous instance.-\\One can use \verb-PlaceTop- only if a reference instance exist. Use a \verb-Place- call before. + \item \verb-[Stratus ERROR] PlaceTop : wrong argument for placement type.-\\The symetry given as argument is not correct. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_power_ring.tex b/stratus1/doc/stratus/man_power_ring.tex new file mode 100644 index 00000000..bea4384d --- /dev/null +++ b/stratus1/doc/stratus/man_power_ring.tex @@ -0,0 +1,49 @@ +\subsubsection{Name} + +PowerRing -- Placement of power rings. + +\subsubsection{Synopsys} + +\begin{verbatim} +PowerRing ( nb ) +\end{verbatim} + +\subsubsection{Description} + +This function places power rings around the core and around the plots. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-nb- : Number of pair of rings vdd/vss +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +PowerRing ( 3 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] PowerRing : Pads in the north haven't been placed.-\\The pads of the 4 sides of the chip must be placed before calling function PowerRing. + \item \verb-[Stratus ERROR] PowerRing : too many rings, not enough space.-\\Wether The argument of PowerRing is to big, or the abutment box of the chip is to small. There's no space to put the rings. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{RouteCk}}{}{RouteCk}{secrouteck} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_reg.tex b/stratus1/doc/stratus/man_reg.tex new file mode 100644 index 00000000..4e43faba --- /dev/null +++ b/stratus1/doc/stratus/man_reg.tex @@ -0,0 +1,55 @@ +\subsubsection{Name} + +Reg -- Easy way to instantiate a register + +\subsubsection{Synopsys} + +\begin{verbatim} +netOut <= netCk.Reg ( netIn ) +\end{verbatim} + +\subsubsection{Description} + +This method is a method of net. The net which this method is applied to is the clock of the register. The net given as parameter is the input net. The method returns a net : the output net.\\ +\indent Note that it is possible to change the generator instanciated with the \verb-SetReg- method. + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = SignalIn ( "a", 4 ) + self.S = SignalOut ( "s", 4 ) + + self.Ck = CkIn ( "ck" ) + + self.Vdd = VddIn ( "vdd" ) + self.Vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S <= self.Ck.Reg ( self.A ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Reg : The input net does not have a positive arity.-\\The input net must have a positive arity. + \item \verb-[Stratus ERROR] Reg : The clock does not have a positive arity.-\\The clock must have a positive arity. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multiplexor}{secmux} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_resize_ab.tex b/stratus1/doc/stratus/man_resize_ab.tex new file mode 100644 index 00000000..8eb71021 --- /dev/null +++ b/stratus1/doc/stratus/man_resize_ab.tex @@ -0,0 +1,59 @@ +\subsubsection{Name} + +ResizeAb -- Modifies the abutment box of the current cell + +\subsubsection{Synopsys} + +\begin{verbatim} +ResizeAb ( dx1, dy1, dx2, dy2 ) +\end{verbatim} + +\subsubsection{Description} + +This function modifies the abutment box of the current cell.\\ +\indent The coordinates of the abutment box are the coordinates of the envelop of the abutment boxes of each instance plus the delta values given as argument.\\ + +\indent Note that one can not call this function in order to create the abutment box. This fonction only modifies the already created abutment box. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-(dx1, dy1)- : Values to be substracted to the lower left corner of the previous abutment box. + \item \verb-(dx2, dy2)- : Values to be added to the upper right corner of the previous abutment box. +\end{itemize} + +\indent The Values are used as follow : +\begin{figure}[h!] +\centering +\includegraphics[width=.3\textwidth]{./images/resizeAb.png} +\end{figure} + +\subsubsection{Example} + +\begin{verbatim} +% Expansion of the abutment box at the top and the bottom +ResizeAb ( 0, 100, 0, 100 ) +\end{verbatim} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb- [Stratus ERROR] ResizeAb :-\\\verb-Coordinates of an abutment Box in y must be multiple of the slice.-\\\verb-Coordinates of an abutment Box in x must be multiple of the pitch.-\\One has called ResizeAb with non authorized values + \item \verb- [Stratus ERROR] ResizeAb :-\\\verb-one of the values of dx1 or dx2 (dy1 or dy2) is incompatible with-\\\verb-the size of the abutment box.-\\\verb-Coordinates of an abutment Box in x must be multiple of the pitch.-\\One has called ResizeAb with a value which deteriorates the abtument box +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{SetRefIns}}{}{SetRefIns}{secsetrefins} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_route_ck.tex b/stratus1/doc/stratus/man_route_ck.tex new file mode 100644 index 00000000..cdb4303c --- /dev/null +++ b/stratus1/doc/stratus/man_route_ck.tex @@ -0,0 +1,49 @@ +\subsubsection{Name} + +RouteCk -- Routing of signal Ck to standard cells + +\subsubsection{Synopsys} + +\begin{verbatim} +RouteCk ( net ) +\end{verbatim} + +\subsubsection{Description} + +This function routes signal Ck to standard cells. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-net- : the net which the fonction is applied to +\end{itemize} + +%\subsubsection{Example} +% +%\begin{verbatim} +%netCk = SignalIn ( "ck", 1 ) +%RouteCk ( netCk ) +%\end{verbatim} +% +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] RouteCk : Pads in the north haven't been placed-\\The pads must be placed before calling RoutageCk. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{PlaceCentric}}{}{PlaceCentric}{seccentric} +\hyperref[ref]{\emph{PlaceGlu}}{}{PlaceGlu}{secglu} +\hyperref[ref]{\emph{FillCell}}{}{FillCell}{secfillcell} +\hyperref[ref]{\emph{Pads}}{}{Pads}{secpads} +\hyperref[ref]{\emph{Alimentation rails}}{}{Alimentation rails}{secrails} +\hyperref[ref]{\emph{Alimentation connectors}}{}{Alimentation connectors}{secconnectors} +\hyperref[ref]{\emph{PowerRing}}{}{PowerRing}{secpowerring} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_set_ref_ins.tex b/stratus1/doc/stratus/man_set_ref_ins.tex new file mode 100644 index 00000000..17eda9a9 --- /dev/null +++ b/stratus1/doc/stratus/man_set_ref_ins.tex @@ -0,0 +1,57 @@ +\subsubsection{Name} + +SetRefIns -- Defines the new "reference instance" for placement + +\subsubsection{Synopsys} + +\begin{verbatim} +SetRefIns ( ins ) +\end{verbatim} + +\subsubsection{Description} + +This function defines the new "reference instance", used as starting point in the relative placement functions.\\ +\indent It's regarding the abutmentbox of the instance \verb-ins- that the next instance is going to be placed, if using the appropriate functions.\\ + +\indent Note that the more recently placed instance becomes automaticaly the "reference instance", if SetRefIns isn't called. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-ins- : defines the new "reference instance" +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +Place ( myInst1, NOSYM, 0, 0 ) +PlaceRight ( myInst2, NOSYM ) + +SetRefIns ( myInst1 ) +PlaceTop ( myInst3, SYM_Y ) +\end{verbatim} + +\indent \verb-myInst3- is on top of \verb-myInst1- instead of \verb-myInst2-. + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] SetRefIns : the instance doesn't exist.-\\If the instance has not been instanciated, it is impossible do to any placement from it. + \item \verb-[Stratus ERROR] SetRefIns : the instance ...is not placed.-\\If the instance has not been placed, it is impossible do to any placement from it. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Place}}{}{Place}{secplace} +\hyperref[ref]{\emph{PlaceTop}}{}{PlaceTop}{sectop} +\hyperref[ref]{\emph{PlaceBottom}}{}{PlaceBottom}{secbottom} +\hyperref[ref]{\emph{PlaceRight}}{}{PlaceRight}{secright} +\hyperref[ref]{\emph{PlaceLeft}}{}{PlaceLeft}{secleft} +\hyperref[ref]{\emph{DefAb}}{}{DefAb}{secdefab} +\hyperref[ref]{\emph{ResizeAb}}{}{ResizeAb}{secresizeab} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_shift.tex b/stratus1/doc/stratus/man_shift.tex new file mode 100644 index 00000000..1da6b7d4 --- /dev/null +++ b/stratus1/doc/stratus/man_shift.tex @@ -0,0 +1,86 @@ +\subsubsection{Name} + +Shift -- Easy way to instantiate a shifter + +\subsubsection{Synopsys} + +\begin{verbatim} +netOut <= netCmd.Shift ( netIn, direction, type ) +\end{verbatim} + +\subsubsection{Description} + +This method is a method of net. The net which this method is applied to is the command of the shifter, it's the one which defines the number of bits to shift. The net given as parameter is the input net. The other arguments set the different patameters. The method returns a net : the output net.\\ +\indent Note that it is possible to change the generator instanciated with the \verb-SetShift- method. + +\subsubsection{Parameters} + +\begin{itemize} + \item \verb-netIn- : the net which is going to be shifted + \item \verb-direction- : this string represents the direction of the shift : + \begin{itemize} + \item "left" + \item "right" + \end{itemize} + \item \verb-type- : this string represents the type of the shift : + \begin{itemize} + \item "logical" : only "zeros" are put in the net + \item "arith" : meaningful for "right" shift, the values put in the nets are an extension of the MSB + \item "circular" : the values put in the nets are the ones which have just been taken off + \end{itemize} +\end{itemize} + +\subsubsection{Example} + +\begin{verbatim} +class essai ( Model ) : + + def Interface ( self ) : + self.A = SignalIn ( "a", 4 ) + + self.Cmd = SignalIn ( "cmd", 2 ) + + self.S1 = SignalOut ( "s1", 4 ) + self.S2 = SignalOut ( "s2", 4 ) + self.S3 = SignalOut ( "s3", 4 ) + + self.Vdd = VddIn ( "vdd" ) + self.Vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + self.S1 <= self.Cmd.Shift ( self.A, "right", "logical" ) + self.S2 <= self.Cmd.Shift ( self.A, "right", "arith" ) + + self.S3 <= self.Cmd.Shift ( self.A, "left", "circular" ) +\end{verbatim} +\indent If the value of "a" is "0b1001" and the value of "cmd" is "0b10", we will have : +\begin{itemize} + \item "s1" : "0b0010" + \item "s2" : "0b1110" + \item "s3" : "0b0110" +\end{itemize} + +\subsubsection{Errors} + +Some errors may occur : +\begin{itemize} + \item \verb-[Stratus ERROR] Shift :-\\\verb-The input net does not have a positive arity.-\\The net which is going to be shifted must have a positive arity. + \item \verb-[Stratus ERROR] Shift :-\\\verb-The direction parameter must be "left" or "right".-\\The "direction" argument is not correct. + \item \verb-[Stratus ERROR] Shift :-\\\verb-The type parameter must be "logical" or "arith" or "circular".-\\The "type" argument is not correct. +\end{itemize} + +\begin{htmlonly} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Instanciation of a multiplexor}}{}{Multiplexor}{secmux} +\hyperref[ref]{\emph{Instanciation of a register}}{}{Reg}{secreg} +\hyperref[ref]{\emph{Instanciation of constants}}{}{Constant}{secconstant} +\hyperref[ref]{\emph{Boolean operations}}{}{Boolean}{secbool} +\hyperref[ref]{\emph{Arithmetical operations}}{}{Arithmetic}{secarithmetic} +\hyperref[ref]{\emph{Comparison operations}}{}{Comparison}{seccomp} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/man_stratus.tex b/stratus1/doc/stratus/man_stratus.tex new file mode 100644 index 00000000..0209920f --- /dev/null +++ b/stratus1/doc/stratus/man_stratus.tex @@ -0,0 +1,127 @@ +\subsubsection{Name} + +Stratus -- Procedural design language based upon \emph{Python} + +\subsubsection{Description} + +\emph{Stratus} is a set of \emph{Python} methods/functions dedicated to procedural generation purposes. From a user point of view, \emph{Stratus} is a circuit's description language that allows \emph{Python} programming flow control, variable use, and specialized functions in order to handle vlsi objects.\\ + +\indent Based upon the \emph{Hurricane} data structures, the \emph{Stratus} language gives the user the ability to describe netlist and layout views. + +\subsubsection{Creation of a cell} + +A cell is a hierachical structural description of a circuit in terms of ports (I/Os), signals (nets) and instances.\\ + +\indent The creation of a cell is done by creating a new class, derivating for class \verb-Model-, with different methods : + +\begin{itemize} +\item Method \verb-Interface- : Description of the external ports of the cell : + \begin{itemize} + \item SignalIn, SignalOut, ... + \end{itemize} +\item Method \verb-Netlist- : Description of the netlist of the cell : + \begin{itemize} + \item Inst, Signal + \end{itemize} +\item Method \verb-Layout- : Description of the layout of the cell : + \begin{itemize} + \item Place, PlaceTop, PlaceBottom, PlaceRight, PlaceLeft ... + \end{itemize} +\end{itemize} + +\indent Two methods are provided : +\begin{itemize} + \item Method \verb-View- : Opens/Refreshes the editor in order to see the created layout + \item Method \verb-Save- : Saves the created cell + \begin{itemize} + \item no argument : creation of a netlist file (format file thanks to CRL\_OUT\_LO) + \item PHYSICAL : creation of a netlist file AND a layout file (format files thanks to CRL\_OUT\_LO and CRL\_OUT\_PH) + \item STRATUS : creation of a python/stratus file + \begin{itemize} + \item FileName : optionnal argument when using Save(STRATUS) in order to choose the name of the file to be generated + \item Be careful : if one wants to create a stratus file AND a netlist, always use Save(STRATUS) before Save() ! + \end{itemize} + \end{itemize} +\end{itemize} + +\subsubsection{Syntax} + +A \emph{Stratus} file must have a .py extension and must begin as follow : +\begin{verbatim} +#!/usr/bin/env python + +from stratus import * +\end{verbatim} + +\indent The creation of a class is done as follow : +\begin{verbatim} +class myClass ( Model ) : + ... + +exemple = myClass ( name, param ) +\end{verbatim} + +\indent In order to execute a \emph{Stratus} file (named \verb-file- for example), one has two choices : +\begin{verbatim} +python file.py +\end{verbatim} +\indent Or : +\begin{verbatim} +chmod u+x file.py +./file.py +\end{verbatim} + +\indent The names used in \emph{Stratus}, as arguments to \emph{Stratus} functions, should be alphanumerical, including the underscore. The arguments of \emph{Stratus} are case sensitive, so \textsc{VDD} is not equivalent to \textsc{vdd}.\\ + +\indent Vectorized connectors or signal can be used using the \textsc{[n:m]} construct.\\ + +\subsubsection{Syntax highlighting} + +When using vi, it's possible to have the right syntax highlighting when using vi : + +\begin{itemize} + \item Commands to do when you want to change once the coloration of your file : +\end{itemize} +\begin{small} +\begin{verbatim} +:syntax off +:source /asim/coriolis/share/etc/stratus.vim +\end{verbatim} +\end{small} +\begin{itemize} + \item Modification of your .vimrc in order to have the syntax highlighting each time you open a file : +\end{itemize} +\begin{small} +\begin{verbatim} +syntax off +autocmd BufRead,BufNewfile *.py so /asim/coriolis/share/etc/stratus.vim +syntax on +\end{verbatim} +\end{small} + +\subsubsection{Environment variables} + +\begin{itemize} + \item CRL\_IN\_LO, default value : \verb-def- + \item CRL\_OUT\_LO, default value : \verb-def- + \item CRL\_IN\_PH, default value : \verb-def- + \item CRL\_OUT\_PH, default value : \verb-def- + \item CRL\_CATA\_LIB, default value : \verb-.- + \item CRL\_CATAL\_NAME, default value : \verb-CATAL- +\end{itemize} + +\begin{htmlonly} + +\subsubsection{Example} + +You can see a concrete example at : \hyperref[ref]{\emph{Example}}{}{Example}{secexample} + +\subsubsection{See Also} + +\hyperref[ref]{\emph{Netlist}}{}{Netlist}{secnetlist} +\hyperref[ref]{\emph{Layout}}{}{Layout}{seclayout} +\hyperref[ref]{\emph{Place and Route}}{}{Place and Route}{secroute} +\hyperref[ref]{\emph{Virtual libraty}}{}{Virtual library}{seclibrary} +\hyperref[ref]{\emph{Instanciation facilities}}{}{Instanciation facilities}{secfacilities} + +\end{htmlonly} diff --git a/stratus1/doc/stratus/see_also.tex b/stratus1/doc/stratus/see_also.tex new file mode 100644 index 00000000..32299cf7 --- /dev/null +++ b/stratus1/doc/stratus/see_also.tex @@ -0,0 +1,3 @@ +\subsubsection{See Also} + +\hyperref[ref]{\emph{Introduction}}{}{Introduction}{secintroduction} diff --git a/stratus1/doc/stratus/stratus.tex b/stratus1/doc/stratus/stratus.tex new file mode 100644 index 00000000..44fef7ce --- /dev/null +++ b/stratus1/doc/stratus/stratus.tex @@ -0,0 +1,232 @@ +\documentclass[12pt]{article} +\usepackage[latin1]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{palatino} +\usepackage{fancyhdr} +\usepackage{float} +\usepackage{subfigure} +\usepackage{wrapfig} +\usepackage[dvips]{graphics} +\usepackage{graphicx} +\usepackage{epsfig} +\usepackage{multicol} +\usepackage{url} +\usepackage{html} +\usepackage{color} + + \definecolor{violet}{rgb}{0.5,0,0.5} + +\setlength{\topmargin}{0cm} +\setlength{\headheight}{1cm} +\setlength{\textheight}{21cm} +\setlength{\textwidth}{16cm} +\setlength{\oddsidemargin}{0cm} +\setlength{\evensidemargin}{0cm} +\setlength{\columnsep}{0.125in} +\setlength{\columnseprule}{0.5pt} +\setlength{\footskip}{1cm} +\sloppy + +%--------------------------------- page style -------------------------------- +\pagestyle{fancy} +\rhead{} +\lhead{} +\rfoot{\thepage} +\lfoot{} +\cfoot{} +%---------------------------------- document --------------------------------- +\date {} +\title {Stratus User's Manual} +\author {Sophie Belloeil} + +\begin{document} + +\setlength{\footrulewidth}{0.6pt} +\maketitle + +%%\begin{htmlonly} +%% \htmlrule +%% \noindent La version imprimable de ce document est disponible ici~: \\ +%% \begin{center} +%% \hyperref[hyper]{http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf}{}{} +%% {http://asim.lip6.fr/~jpc/M1-C++/TME/6/TME6.pdf} +%% \end{center} +%%\end{htmlonly} + +\tableofchildlinks +\htmlrule + +\section{What's new} +\input{man_new} + +\section{Introduction} +\label{secintroduction} + + \subsection{Stratus} + \label{secstratus} + \input{man_stratus} + \subsection{Example} + \label{secexample} + \input{man_example} + +\section{Description of a netlist} +\label{secnetlist} + + \subsection{Nets} + \label{secnet} + \input{man_net} + \subsection{Instances} + \label{secinst} + \input{man_inst} + \subsection{Generators} + \label{secgen} + \input{man_generate} + +\section{Description of a layout} +\label{seclayout} + + \subsection{Place} + \label{secplace} + \input{man_place} + \subsection{PlaceTop} + \label{sectop} + \input{man_place_top} + \subsection{PlaceBottom} + \label{secbottom} + \input{man_place_bottom} + \subsection{PlaceRight} + \label{secright} + \input{man_place_right} + \subsection{PlaceLeft} + \label{secleft} + \input{man_place_left} + \subsection{SetRefIns} + \label{secsetrefins} + \input{man_set_ref_ins} + \subsection{DefAb} + \label{secdefab} + \input{man_def_ab} + \subsection{ResizeAb} + \label{secresizeab} + \input{man_resize_ab} + +\section{Place and Route} +\label{secroute} + + \subsection{PlaceSegment} + \label{secsegment} + \input{man_place_segment} + \subsection{PlaceContact} + \label{seccontact} + \input{man_place_contact} + \subsection{PlacePin} + \label{secpin} + \input{man_place_pin} + \subsection{PlaceRef} + \label{secref} + \input{man_place_ref} + \subsection{GetRefXY} + \label{secgetref} + \input{man_get_ref} + \subsection{CopyUpSegment} + \label{seccopy} + \input{man_copy_up_segment} + \subsection{PlaceCentric} + \label{seccentric} + \input{man_place_centric} + \subsection{PlaceGlu} + \label{secglu} + \input{man_place_glu} + \subsection{FillCell} + \label{secfillcell} + \input{man_fill_cell} + \subsection{Pads} + \label{secpads} + \input{man_pads} + \subsection{Alimentation rails} + \label{secrails} + \input{man_alim_rail} + \subsection{Alimentation connectors} + \label{secconnectors} + \input{man_alim_connectors} + \subsection{PowerRing} + \label{secpowerring} + \input{man_power_ring} + \subsection{RouteCk} + \label{secrouteck} + \input{man_route_ck} + +\section{Instanciation facilities} +\label{secfacilities} + + \subsection{Buffer} + \label{secbuff} + \input{man_buff} + \subsection{Multiplexor} + \label{secmux} + \input{man_mux} + \subsection{Shifter} + \label{secshift} + \input{man_shift} + \subsection{Register} + \label{secreg} + \input{man_reg} + \subsection{Constants} + \label{secconstant} + \input{man_const} + \subsection{Boolean operations} + \label{secbool} + \input{man_boolean} + \subsection{Arithmetical operations} + \label{secarithmetic} + \input{man_arithmetic} + \subsection{Comparison operations} + \label{seccomp} + \input{man_comp} + +%\section{Developper's manual} +%\label{secdev} +% +% \subsection{Class Model} +% \label{secmodeldev} +% \input{man_model_dev} +% +% \subsection{Nets} +% \label{secnetdev} +% \input{man_net_dev} +% +% \subsection{Instances} +% \label{secinstdev} +% \input{man_inst_dev} + +\section{Virtual library} +\label{seclibrary} +\input{man_library} + +\begin{htmlonly} + +\section{Useful links} + + \subsection{Patterns module} + +You can find the documentation of the patterns module :\\ +\url{file:///asim/coriolis/share/doc/en/html/patterns/index.html} + + \subsection{DPGEN generators} + +You can find the documentation of the DPGEN library at :\\ +\url{file:///asim/coriolis/share/doc/en/html/dpgen/index.html} + + \subsection{Arithmetic package of stratus} + +You can find the documentation of the arithmetic stratus's package at :\\ +\url{file:////users/outil/arith/latest/modules_stratus/arithmetic/doc/arith/index.html} + + \subsection{Arithmetic generators and some stratus packages} + +You can find the documentation of the arithmetic library at :\\ +\url{file:////users/outil/arith/latest/doc/index.html} + +\end{htmlonly} + +\end{document} diff --git a/stratus1/etc/CMakeLists.txt b/stratus1/etc/CMakeLists.txt new file mode 100644 index 00000000..00281917 --- /dev/null +++ b/stratus1/etc/CMakeLists.txt @@ -0,0 +1,3 @@ + + install ( FILES stratus2sxlib.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 ) + install ( FILES stratus.vim DESTINATION ${SYS_CONF_DIR}/coriolis2 ) diff --git a/stratus1/etc/stratus.vim b/stratus1/etc/stratus.vim new file mode 100644 index 00000000..7f9164c4 --- /dev/null +++ b/stratus1/etc/stratus.vim @@ -0,0 +1,174 @@ +" Vim syntax file +" Language: Stratus +" +" There are four options to control Stratus syntax highlighting : +" +" For highlighted numbers : + let s_highlight_numbers = 1 +" +" For highlighted builtin functions : + let s_highlight_builtins = 1 +" +" For highlighted standard exceptions : + let s_highlight_exceptions = 1 +" +" For highlighted stratus : + let s_highlight_stratus = 1 + + +" remove old syntax +syn clear + +syn keyword sStatement break continue del +syn keyword sStatement except exec finally +syn keyword sStatement pass print raise +syn keyword sStatement return try +syn keyword sStatement global assert +syn keyword sStatement lambda +syn keyword sStatement def class nextgroup=sFunction skipwhite +syn match sFunction "[a-zA-Z_][a-zA-Z0-9_]*" contained +syn keyword sRepeat for while +syn keyword sConditional if elif else +syn keyword sOperator and in is not or +syn keyword sPreCondit import from +syn match sComment "#.*$" contains=sTodo +syn keyword sTodo contained TODO FIXME XXX + +" strings +syn region sString matchgroup=Normal start=+'+ end=+'+ skip=+\\\\\|\\'+ contains=sEscape +syn region sString matchgroup=Normal start=+"+ end=+"+ skip=+\\\\\|\\"+ contains=sEscape +syn region sString matchgroup=Normal start=+"""+ end=+"""+ contains=sEscape +syn region sString matchgroup=Normal start=+'''+ end=+'''+ contains=sEscape +syn region sRawString matchgroup=Normal start=+[rR]'+ end=+'+ skip=+\\\\\|\\'+ +syn region sRawString matchgroup=Normal start=+[rR]"+ end=+"+ skip=+\\\\\|\\"+ +syn region sRawString matchgroup=Normal start=+[rR]"""+ end=+"""+ +syn region sRawString matchgroup=Normal start=+[rR]'''+ end=+'''+ +syn match sEscape +\\[abfnrtv'"\\]+ contained +syn match sEscape "\\\o\o\=\o\=" contained +syn match sEscape "\\x\x\+" contained +syn match sEscape "\\$" + +if exists("s_highlight_numbers") + " numbers (including longs and complex) + syn match sNumber "\<0x\x\+[Ll]\=\>" + syn match sNumber "\<\d\+[LljJ]\=\>" + syn match sNumber "\.\d\+\([eE][+-]\=\d\+\)\=[jJ]\=\>" + syn match sNumber "\<\d\+\.\([eE][+-]\=\d\+\)\=[jJ]\=\>" + syn match sNumber "\<\d\+\.\d\+\([eE][+-]\=\d\+\)\=[jJ]\=\>" +endif + +if exists("s_highlight_builtins") + " builtin functions, not really part of the syntax + syn keyword sBuiltin abs apply callable chr cmp coerce + syn keyword sBuiltin compile complex delattr dir divmod + syn keyword sBuiltin eval execfile filter float getattr + syn keyword sBuiltin globals hasattr hash hex id input + syn keyword sBuiltin int intern isinstance issubclass +" syn keyword sBuiltin len list locals long map max min + syn keyword sBuiltin len list locals long max min + syn keyword sBuiltin oct open ord pow range raw_input + syn keyword sBuiltin reduce reload repr round setattr + syn keyword sBuiltin slice str tuple type vars xrange +endif + +if exists("s_highlight_exceptions") + " builtin exceptions + syn keyword sException None + syn keyword sException ArithmeticError AssertionError + syn keyword sException AttributeError EOFError EnvironmentError + syn keyword sException Exception FloatingPointError IOError + syn keyword sException ImportError IndexError KeyError + syn keyword sException KeyboardInterrupt LookupError + syn keyword sException MemoryError NameError NotImplementedError + syn keyword sException OSError OverflowError RuntimeError + syn keyword sException StandardError SyntaxError SystemError + syn keyword sException SystemExit TypeError ValueError + syn keyword sException ZeroDivisionError +endif + +if exists("s_highlight_stratus") + " builtin exceptions + syn keyword stratusSpecial self + + syn keyword stratusClass Model + syn keyword stratusClass SignalIn SignalOut SignalInOut SignalUnknown TriState CkIn VddIn VssIn Signal + syn keyword stratusClass Inst + syn keyword stratusClass XY + + syn keyword stratusMethod Interface Netlist Layout Vbe Pattern View Save Simul HurricanePlug Quit GetModelName Clean + syn keyword stratusMethod Alias Extend + syn keyword stratusMethod Buffer Mux Shift Reg Eq Ne + syn keyword stratusMethod SetAnd SetOr SetNot SetXor SetNot SetMux SetAdd SetMult SetDiv + syn keyword stratusMethod Delete + + syn keyword stratusMap param map + + syn keyword stratusNumber NOSYM SYM_X SYM_Y SYMXY ROT_P ROT_M SY_RP SY_RM + syn keyword stratusNumber VIEWS LOGICAL PHYSICAL + syn keyword stratusNumber STRATUS + syn keyword stratusNumber UNPLACED PLACED FIXED + syn keyword stratusNumber F_LSB_FIRST F_MSB_FIRST + syn keyword stratusNumber TypePOWER TypeGROUND TypeCLOCK + syn keyword stratusNumber DirectionIN DirectionOUT DirectionINOUT DirectionTRISTATE DirectionUNDEFINED + + syn keyword stratusFunction Generate + syn keyword stratusFunction Place PlaceTop PlaceBottom PlaceRight PlaceLeft SetRefIns DefAb ResizeAb + syn keyword stratusFunction PlaceCentric AlimVerticalRail AlimHorizontalRail AlimConnectors PadNorth PadSouth PadEast PadWest AffichePad SearchVddVss IsConflit PowerRing GetNetInstances RoutageNet RouteCk FillCell PlaceGlue GlobalRoute DetailRoute + syn keyword stratusFunction GetRefXY PlaceRef PlaceContact PlaceSegment PlacePin CopyUpSegment + syn keyword stratusFunction Cat + syn keyword stratusFunction Param + syn keyword stratusFunction One Zero + +endif + + + +" This is fast but code inside triple quoted strings screws it up. It +" is impossible to fix because the only way to know if you are inside a +" triple quoted string is to start from the beginning of the file. If +" you have a fast machine you can try uncommenting the "sync minlines" +" and commenting out the rest. +syn sync match sSync grouphere NONE "):$" +syn sync maxlines=100 +"syn sync minlines=2000 + +if !exists("did_s_syntax_inits") + let did_s_syntax_inits = 1 + " The default methods for highlighting. Can be overridden later + hi link sStatement Statement + hi link sFunction Function + hi link sConditional Conditional + hi link sRepeat Repeat + hi link sString String + hi link sRawString String + hi link sEscape Special + hi link sOperator Operator + hi link sPreCondit PreCondit + hi link sComment Comment + hi link sTodo Todo + + if exists("s_highlight_numbers") + hi link sNumber Number + endif + + if exists("s_highlight_builtins") + hi link sBuiltin Function + endif + + if exists("s_highlight_exceptions") + hi link sException Exception + endif + + if exists("s_highlight_stratus") + hi link stratusSpecial Statement + hi link stratusClass Include + hi link stratusFunction Special + hi link stratusMethod Function + hi link stratusMap Identifier + hi link stratusNumber Number + endif +endif + + +let b:current_syntax = "stratus" + diff --git a/stratus1/etc/stratus2sxlib.xml b/stratus1/etc/stratus2sxlib.xml new file mode 100644 index 00000000..2ee7dd32 --- /dev/null +++ b/stratus1/etc/stratus2sxlib.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stratus1/src/CMakeLists.txt b/stratus1/src/CMakeLists.txt new file mode 100644 index 00000000..d4e973f3 --- /dev/null +++ b/stratus1/src/CMakeLists.txt @@ -0,0 +1,3 @@ + add_subdirectory ( stratus ) + add_subdirectory ( dpgen ) + add_subdirectory ( modules ) diff --git a/stratus1/src/dpgen/CMakeLists.txt b/stratus1/src/dpgen/CMakeLists.txt new file mode 100644 index 00000000..53f37ae8 --- /dev/null +++ b/stratus1/src/dpgen/CMakeLists.txt @@ -0,0 +1,16 @@ + + set ( pysources ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_ADSB2F.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_Nul.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_RAM.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_Regular.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_RF1.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_RF2.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_ROM2.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_ROM4.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_ROM.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_Shifter.py + ${CMAKE_CURRENT_SOURCE_DIR}/dpgen_Shrot.py + ${CMAKE_CURRENT_SOURCE_DIR}/ROM_encours.py + ) + + install ( FILES ${pysources} DESTINATION ${PYTHON_SITE_PACKAGES}/stratus ) diff --git a/stratus1/src/dpgen/ROM_encours.py b/stratus1/src/dpgen/ROM_encours.py new file mode 100644 index 00000000..4085f65f --- /dev/null +++ b/stratus1/src/dpgen/ROM_encours.py @@ -0,0 +1,865 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_ROM.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +# Le nombre de mots peut prendre cinq valeurs : 64, 128, 256, 512, 1024 +# Le nombre de bits est un multiple de 4 et doit etre inferieur ou egal a 64 +# On peut avoir une sortie tri-state en option (pour construire des ROMs +# de capacite superieure a 1024 mots. +# La largeur est egale a ( nmot / 64 * 50) + 150 (+ 20 si option tristate) +# La hauteur est egale a ( nbit + 8) * 50 pour 64 ou 128 mots +# ( nbit + 9) * 50 pour 256, 512 ou 1024 mots +# +# Les valeurs a encoder dans la ROM sont recuperees dans le tableau data[2048] +# qui contient des "mots" de 32 bits : une valeur est stockee dans deux cases +# consecutives de ce tableau, ce qui permet d'avoir des mots de 64 bits. +# Les poids faibles de la valeur i sont a l'adresse data[2*i] +# Les poids forts de la valeur i sont a l'adresse data[2*i+1] +# +# Les lignes de bit horizontales en ALU2 sont hors grilles et pre-routees +# la ROM respecte le gabarit SXLIB pour ce qui concerne les caissons et les +# alimentations en ALU1 sur les faces est et ouest, mais il n'y a pas +# de continuite des alimentations en ALU1 dans la zone data. +# Pour la partie "donnees", on utilise les cellules suivantes : +# - rom_data_invss +# - rom_data_insel +# - rom_data_midvss +# - rom_data_midsel +# - rom_data_outvss +# - rom_data_outsel +# - rom_data_outvss_ts +# - rom_data_outsel_ts +# +# Pour le decodeur, on utilise les cellules suivantes : +# - rom_dec_adbuf +# - rom_dec_nop +# - rom_dec_prech +# - rom_dec_col2 +# - rom_dec_col3 +# - rom_dec_col4 +# - rom_dec_colbuf +# - rom_dec_line01 +# - rom_dec_line23 +# - rom_dec_line45 +# - rom_dec_line67 +# - rom_dec_selmux01 +# - rom_dec_selmux23 +# - rom_dec_selmux45 +# - rom_dec_selmux67 +# - rom_dec_selmux67_128 +# - rom_dec_selmux01_ts +# - rom_dec_selmux23_ts +# - rom_dec_selmux45_ts +# - rom_dec_selmux67_ts +# - rom_dec_selmux67_128_ts + +class dpgen_ROM ( Model ) : + + ## Interface ## + ############### + def Interface ( self, nbit, nword ) : + + if nword == 64 : adrange = 6 + elif nword == 128 : adrange = 7 + elif nword == 256 : adrange = 8 + elif nword == 512 : adrange = 9 + elif nword == 1024 : adrange = 10 + else : + print "Error : DPGEN_ROM" + print "The word number (nword := %d) ", nword, "can only takes values : 64, 128, 256, 512 or 1024.\n" + sys.exit ( 3 ) + + if nbit % 4 != 0 or nbit > 64 or nbit < 4 : + print "Error : DPGEN_ROM\n" + print "The bus width (nbit := %d) ", nbit, "must be multiple of 4 and no larger than 64.\n" + sys.exit ( 3 ) + + ck = LogicIn ( "ck", 1 ) + selrom = LogicIn ( "selrom", 1 ) + + ad = LogicIn ( "ad", adrange ) + data = LogicOut ( "data", nbit ) + + vdd = VddIn ( "vdd" ) + vss = VssIn ( "vss" ) + + + ## Architecture ## + ################## + def architecture ( self, nbit, nword ) : + +# // Acquisition du tableau des valeurs a encoder +# +# /* ICI IL FAUT APPELER LE PARSER DE FICHIER .vbe */ +# /* +# for(i=0 ; i<1024 ; i++) { +# data[2*i] = i; +# data[2*i+1] = 1024 - i; +# } +# */ +# +# dpgen_ROM_code ( LV_name, nbit, nword, 0, 0, data ) # !!! + + for i in range ( nbit ) : + if i % 4 == 0 : + cellin = "rom_data_invss" + cellmid = "rom_data_midvss" + + cellout = "rom_data_outvss" + + elif i % 4 == 1 : + cellin = "rom_data_insel" + cellmid = "rom_data_midsel" + + cellout = "rom_data_outsel" + + elif i % 4 == 2: + cellin = "rom_data_insel" + cellmid = "rom_data_midsel" + + cellout = "rom_data_outsel" + + elif i % 4 == 3 : + cellin = "rom_data_invss" + cellmid = "rom_data_midvss" + + cellout = "rom_data_outvss" + + instanciate ( cellin + , "in%d" % i + , map = { 'prech' : prech + , 'bit0' : bit0[i] + , 'bit1' : bit1[i] + , 'bit2' : bit2[i] + , 'bit3' : bit3[i] + , 'bit4' : bit4[i] + , 'bit5' : bit5[i] + , 'bit6' : bit6[i] + , 'bit7' : bit7[i] + } + ) + + for j in range ( 0, nword, 64 ) : + instanciate ( cellmid + , "bit%d_%d" % ( i, j ) + , map = { 'sela' : line0[j] + , 'selb' : line2[j] + , 'selc' : line4[j] + , 'seld' : line6[j] + , 'bit0' : bit0 [i] + , 'bit1' : bit1 [i] + , 'bit2' : bit2 [i] + , 'bit3' : bit3 [i] + , 'bit4' : bit4 [i] + , 'bit5' : bit5 [i] + , 'bit6' : bit6 [i] + , 'bit7' : bit7 [i] + } + ) + + instanciate ( cellmid + , "bit%d_%d" % ( i, j + 32 ) + , map = { 'sela' : line1[j] + , 'selb' : line3[j] + , 'selc' : line5[j] + , 'seld' : line7[j] + , 'bit0' : bit0 [i] + , 'bit1' : bit1 [i] + , 'bit2' : bit2 [i] + , 'bit3' : bit3 [i] + , 'bit4' : bit4 [i] + , 'bit5' : bit5 [i] + , 'bit6' : bit6 [i] + , 'bit7' : bit7 [i] + } + ) + + instanciate ( cellout + , "out%d" % i + , map = { 'nprech' : nprech + , 'mux0' : mux0 + , 'mux1' : mux1 + , 'mux2' : mux2 + , 'mux3' : mux3 + , 'mux4' : mux4 + , 'mux5' : mux5 + , 'mux6' : mux6 + , 'mux7' : mux7 + , 'bit0' : bit0[i] + , 'bit1' : bit1[i] + , 'bit2' : bit2[i] + , 'bit3' : bit3[i] + , 'bit4' : bit4[i] + , 'bit5' : bit5[i] + , 'bit6' : bit6[i] + , 'bit7' : bit7[i] + , 'q' : data[i] + } + ) + + ## Placement des cellules decodeur ## + + # Lignes 0 et 1 + instanciate ( "rom_dec_prech" + , "prech" + , map = { 'nck' : nck + , 'prech' : prech + , 'nprech' : nprech + } + ) + + for j in range ( 0, nword, 64 ) : + thisMap = { 'nck0' : nck + , 'nck1' : nck + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'line0' : line0[j] + , 'line1' : line1[j] + } + + if nword != 64 : thisMap['col'] = col[j] + else : thisMap['col'] = vdd + + instanciate ( "rom_dec_line01" + , "and01_%d" % j + , map = thisMap + ) + + instanciate ( "rom_dec_selmux01" + , "selmux01" + , map = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'ck' : ck + , 'selrom' : selrom + , 'nck' : nck + , 'mux0' : mux0 + , 'sel0' : sel0 + , 'mux1' : mux1 + , 'sel1' : sel1 + } + ) + + # Lignes 2 et 3 + instanciate ( "rom_dec_adbuf" + , "ad4" + , map = { 'ad' : ad[4] + , 'adx' : a4 + , 'nadx' : na4 + } + ) + + instanciate ( "rom_dec_adbuf" + , "ad5" + , map = { 'ad' : ad[5] + , 'adx' : a5 + , 'nadx' : na5 + } + ) + + for j in range ( 0, nword, 64 ) : + thisMap = { 'nck2' : nck + , 'nck3' : nck + , 'sel2' : sel2 + , 'sel3' : sel3 + , 'line2' : line2[j] + , 'line3' : line3[j] + } + + if nword != 64 : thisMap['col'] = col[j] + else : thisMap['col'] = vdd + + instanciate ( "rom_dec_line23" + , "and23_%d" % j + , map = thisMap + ) + + LV_name.PLACE_RIGHT ( "rom_dec_selmux23" + , "selmux23" + , map = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'ck' : ck + , 'selrom' : selrom + , 'nck' : nck + , 'mux2' : mux2 + , 'sel2' : sel2 + , 'mux3' : mux3 + , 'sel3' : sel3 + } + ) + + # Lignes 4 et 5 + instanciate ( "rom_dec_adbuf" + , "ad2" + , map = { 'ad' : ad[2] + , 'adx' : a2 + , 'nadx' : na2 + } + ) + + nstanciate ( "rom_dec_adbuf" + , "ad3" + , map = { 'ad' : ad[3] + , 'adx' : a3 + , 'nadx' : na3 + } + ) + + for j in range ( 0, nword, 64 ) : + thisMap = { 'nck4' : nck + , 'nck5' : nck + , 'sel4' : sel4 + , 'sel5' : sel5 + , 'line4' : line4[j] + , 'line5' : line5[j] + } + + if nword != 64 : thisMap['col'] = col[j] + else : thisMap['col'] = vdd + + instanciate ( "rom_dec_line45" + , "and45_%d" % j + , map = thisMap + ) + + instanciate ( "rom_dec_selmux45" + , "selmux45" + , map = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'ck' : ck + , 'selrom' : selrom + , 'nck' : nck + , 'mux4' : mux4 + , 'sel5' : sel4 + , 'mux5' : mux5 + , 'sek5' : sel5 + } + ) + + # Lignes 6 et 7 + instanciate ( "rom_dec_adbuf" + , "ad0" + , map = { 'ad' : ad[0] + , 'adx' : a0 + , 'nadx' : na0 + } + ) + + instanciate ( "rom_dec_adbuf" + , "ad1" + , map = { "ad => ad[1]" + , "adx => a1" + , "nadx => na1" + } + ) + + for j in range ( 0, nword, 64 ) : + thisMap = { 'nck6' : nck + , 'nck7' : nck + , 'sel6' : sel6 + , 'sel7' : sel7 + , 'line6' : line6[j] + , 'line7' : line7[j] + } + + if nword != 64 : thisMap['col'] = col[j] + else : thisMap['col'] = vdd + + instanciate ( "rom_dec_line67" + , "and67_%d" % j + , map = thisMap + ) + + if nword != 128 : # pas de sortie tristate + instanciate ( "rom_dec_selmux67" + , "selmux67" + , map = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'ck' : ck + , 'selrom' : selrom + , 'nck' : nck + , 'mux6' : mux6 + , 'sel6' : sel6 + , 'mux7' : mux7 + , 'sel7' : sel7 + } + ) + + else : # pas de sortie tristate - 128 mots + instanciate ( "rom_dec_selmux67_128" + , "selmux67" + , map = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'a6' : ad[6] + , 'selrom' : selrom + , 'a6x' : col_64 + , 'na6x' : col_0 + , 'mux6' : mux6 + , 'sel6' : sel6 + , 'mux7' : mux7 + , 'sel7' : sel7 + } + ) + + # Ligne 9 dans le cas 1024 mots + if nword == 1024 : + instanciate ( "rom_dec_nop" + , "nop" + ) + + for j in range ( 0, nword, 64 ) : + thisMap = { 'q' : col[j] } + + if ( j >> 6 ) % 2 == 0 : thisMap['i0'] = na6x + else : thisMap['i0'] = a6x + + if ( j >> 7 ) % 2 == 0 : thisMap['i1'] = na7x + else : thisMap['i1'] = a7x + + if ( j >> 8 ) % 2 == 0 : thisMap['i2'] = na8x + else : thisMap['i2'] = a8x + + if ( j >> 9 ) % 2 == 0 : thisMap['i3'] = na9x + else : thisMap['i3'] = a9x + + instanciate ( "rom_dec_col4" + , "col_%d" % j + , map = thisMap + ) + + instanciate ( "rom_dec_colbuf" + , "colbuf6" + , map = { " => ad[6]" + , " => a6x" + , " => na6x" + ) + + instanciate ( "rom_dec_colbuf" + , "colbuf7" + , NOSYM + , FIXED + , "a => ad[7]" + , "ax => a7x" + , "nax => na7x" + , vdd + , vss + ) + + LV_name.PLACE_RIGHT ( "rom_dec_colbuf" + , "colbuf8" + , NOSYM + , FIXED + , "a => ad[8]" + , "ax => a8x" + , "nax => na8x" + , vdd + , vss + ) + + LV_name.PLACE_RIGHT ( "rom_dec_colbuf" + , "colbuf9" + , NOSYM + , FIXED + , "a => ad[9]" + , "ax => a9x" + , "nax => na9x" + , vdd + , vss + ) + + # Ligne 9 dans le cas 512 mots + if nword == 512 : + LV_name.PLACE ( "rom_dec_nop" + , "nop" + , NOSYM + , 0 + , ( nbit + 8 ) * HCELL + , FIXED + , vdd + , vss + ) + + for j in range ( 0, nword, 64 ) : + if ( j >> 6 ) % 2 == 0 : x6 = "i0 => na6x" + else : x6 = "i0 => a6x" + + if ( j >> 7 ) % 2 == 0 : x7 = "i1 => na7x" + else : x7 = "i1 => a7x" + + if ( j >> 8 ) % 2 == 0 : x8 = "i2 => na8x" + else : x8 = "i2 => a8x" + + LV_name.PLACE_RIGHT ( "rom_dec_col3" + , "col_%d" % j + , NOSYM + , FIXED + , x6 + , x7 + , x8 + , "q => col_%d" % j + , vdd + , vss + ) + + LV_name.PLACE_RIGHT ( "rom_dec_colbuf" + , "colbuf6" + , NOSYM + , FIXED + , "a => ad[6]" + , "ax => a6x" + , "nax => na6x" + , vdd + , vss + ) + + LV_name.PLACE_RIGHT ( "rom_dec_colbuf" + , "colbuf7" + , NOSYM + , FIXED + , "a => ad[7]" + , "ax => a7x" + , "nax => na7x" + , vdd + , vss + ) + + LV_name.PLACE_RIGHT ( "rom_dec_colbuf" + , "colbuf8" + , NOSYM + , FIXED + , "a => ad[8]" + , "ax => a8x" + , "nax => na8x" + , vdd + , vss + ) + + # Ligne 9 dans le cas 256 mots + if nword == 256 : + LV_name.PLACE ( "rom_dec_nop" + , "nop" + , NOSYM + , 0 + , ( nbit + 8 ) * HCELL + , FIXED + , vdd + , vss + ) + + for j in range ( 0, nword, 64 ) : + if ( j >> 6 ) % 2 == 0 : x6 = "i0 => na6x" + else : x6 = "i0 => a6x" + + if ( j >> 7 ) % 2 == 0 : x7 = "i1 => na7x" + else : x7 = "i1 => a7x" + + LV_name.PLACE_RIGHT ( "rom_dec_col2" + , "col_%d" % j + , NOSYM + , FIXED + , x6 + , x7 + , "q => col_%d" % j + , vdd + , vss + ) + + LV_name.PLACE_RIGHT ( "rom_dec_colbuf" + , "colbuf6" + , NOSYM + , FIXED + , "a => ad[6]" + , "ax => a6x" + , "nax => na6x" + , vdd + , vss + ) + + LV_name.PLACE_RIGHT ( "rom_dec_colbuf" + , "colbuf7" + , NOSYM + , FIXED + , "a => ad[7]" + , "ax => a7x" + , "nax => na7x" + , vdd + , vss + ) + +# ## Routage des rappels d'alimentation et des signaux hors grille ## +# y1 = nbit * HCELL +# +# if nword > 128 : y2 = ( nbit + 9 ) * HCELL +# else : y2 = ( nbit + 8 ) * HCELL +# +# if type == 0 : x2 = ( nword / 64 * 50 ) + 150 +# else : x2 = ( nword / 64 * 50 ) + 170 +# +# # alimentations verticales ALU3 +# LV_name.PHSEG ( CALU3,12, "vdd", 10, 0, 10, y2) +# LV_name.PHSEG ( CALU3, 2, "vss", 20, 0, 20, y2) +# LV_name.PHSEG ( CALU3, 2, "vss", 30, 0, 30, y2) +# +# for j in range ( 0, nword, 64 ) : +# LV_name.PHSEG ( CALU3, 2, "vss", 55 + ( 50 * j / 64 ), 0, 55 + ( 50 * j / 64 ), y2 ) +# LV_name.PHSEG ( CALU3, 2, "vss", 80 + ( 50 * j / 64 ), 0, 80 + ( 50 * j / 64 ), y2 ) +# +# if type == 0 : +# LV_name.PHSEG ( CALU3, 2, "vss", 125 + ( nword / 64 * 50 ), 0, 125 + ( nword / 64 * 50 ), y1 ) +# LV_name.PHSEG ( CALU3, 2, "vdd", 135 + ( nword / 64 * 50 ), 0, 135 + ( nword / 64 * 50 ), y1 ) +# LV_name.PHSEG ( CALU3, 2, "vdd", 145 + ( nword / 64 * 50 ), 0, 145 + ( nword / 64 * 50 ), y1 ) +# +# else : +# LV_name.PHSEG ( CALU3, 2, "vss", 135 + ( nword / 64 * 50 ), 0, 135 + ( nword / 64 * 50 ), y1 ) +# LV_name.PHSEG ( CALU3, 2, "vdd", 145 + ( nword / 64 * 50 ), 0, 145 + ( nword / 64 * 50 ), y1 ) +# LV_name.PHSEG ( CALU3, 2, "vss", 155 + ( nword / 64 * 50 ), 0, 155 + ( nword / 64 * 50 ), y2 ) +# LV_name.PHSEG ( CALU3, 2, "vdd", 165 + ( nword / 64 * 50 ), 0, 165 + ( nword / 64 * 50 ), y2 ) +# +# # alimemtations horizontales ALU2 +# for i in range ( 0, nbit, 4 ) : +# LV_name.PHSEG ( CALU2, 2, "vss", 0, i * HCELL, x2, i * HCELL ) +# +# for l in range ( 0, 8, 2 ) : +# LV_name.PHSEG ( CALU2, 2, "vss", 0, ( nbit + l ) * HCELL, x2, ( nbit + l ) * HCELL ) +# LV_name.PHSEG ( CALU2, 2, "vdd", 0, ( nbit + l + 1 ) * HCELL, x2, ( nbit + l + 1 ) * HCELL ) +# +# LV_name.PHSEG ( CALU2, 2, "vss", 0, ( nbit + 8 ) * HCELL, x2, ( nbit + 8 ) * HCELL ) +# +# if nword > 128 : LV_name.PHSEG ( CALU2, 2, "vdd", 0, ( nbit + 9 ) * HCELL, x2, ( nbit + 9 ) * HCELL ) +# +# # alimentations horizontales ALU1 +# for i in range ( 0, nbit, 2 ) : +# LV_name.PHSEG ( CALU1, 6, "vss", 0 , HCELL * i + 3, 5, HCELL * i + 3 ) +# LV_name.PHSEG ( CALU1, 6, "vss", x2 - 5, HCELL * i + 3, x2, HCELL * i + 3 ) +# LV_name.PHSEG ( CALU1, 6, "vdd", 0 , HCELL * i + 47, 5, HCELL * i + 47 ) +# LV_name.PHSEG ( CALU1, 6, "vdd", x2 - 5, HCELL * i + 47, x2, HCELL * i + 47 ) +# LV_name.PHSEG ( CALU1, 6, "vdd", 0 , HCELL * i + 53, 5, HCELL * i + 53 ) +# LV_name.PHSEG ( CALU1, 6, "vdd", x2 - 5, HCELL * i + 53, x2, HCELL * i + 53 ) +# LV_name.PHSEG ( CALU1, 6, "vss", 0 , HCELL * i + 97, 5, HCELL * i + 97 ) +# LV_name.PHSEG ( CALU1, 6, "vss", x2 - 5, HCELL * i + 97, x2, HCELL * i + 97 ) +# +# for l in range ( 0, 8, 2 ) : +# LV_name.PHSEG ( CALU1, 6, "vss", 0, y1 + HCELL * l + 3, x2, y1 + HCELL * l + 3 ) +# LV_name.PHSEG ( CALU1, 6, "vdd", 0, y1 + HCELL * l + 47, x2, y1 + HCELL * l + 47 ) +# LV_name.PHSEG ( CALU1, 6, "vdd", 0, y1 + HCELL * l + 53, x2, y1 + HCELL * l + 53 ) +# LV_name.PHSEG ( CALU1, 6, "vss", 0, y1 + HCELL * l + 97, x2, y1 + HCELL * l + 97 ) +# +# if nword > 128 : +# LV_name.PHSEG ( CALU1, 6, "vss", 0, y1 + 403, x2, y1 + 403 ) +# LV_name.PHSEG ( CALU1, 6, "vdd", 0, y1 + 447, x2, y1 + 447 ) +# +# # routage des lignes de bit horizontales hors grille +# for i in range ( nbit ) : +# for l inr ange ( 8 ) : +# x1 = GET_REF_X ( "in%d" % i), "bit%d" % ,l ) ) +# y1 = GET_REF_Y ( "in%d" % i), "bit%d" % ,l ) ) +# x2 = GET_REF_X ( "out%d" % i), "bit%d" % ,l ) ) +# y2 = GET_REF_Y ( "out%d" % i), "bit%d" % ,l ) ) +# +# LV_name.PHSEG ( ALU2, 2, "bit%d_%d" % ( l, i ), x1, y1, x2, y2 ) +# +# # cablage a 1 de l'entree col dans le cas 64 mots +# if nword == 64 : +# x1 = GET_REF_X ( "and01_0", "refcol" ) +# y1 = GET_REF_Y ( "and01_0", "refcol" ) +# PHBIGVIA ( CONT_VIA2, x1, y1, 0, 0, "vdd" ) +# +# x1 = GET_REF_X ( "and23_0", "refcol" ) +# y1 = GET_REF_Y ( "and23_0", "refcol" ) +# PHBIGVIA ( CONT_VIA2, x1, y1, 0, 0, "vdd" ) +# +# x1 = GET_REF_X ( "and45_0", "refcol" ) +# y1 = GET_REF_Y ( "and45_0", "refcol" ) +# PHBIGVIA ( CONT_VIA2, x1, y1, 0, 0, "vdd" ) +# +# x1 = GET_REF_X ( "and67_0", "refcol" ) +# y1 = GET_REF_Y ( "and67_0", "refcol" ) +# PHBIGVIA ( CONT_VIA2, x1, y1, 0, 0, "vdd" ) +# +# # Codage Plan Memoire (codage diffusion) +# a modifier pour creer ces segments dans une figure separee +# for j in range ( 0, nword ; j+=32) : # boucle sur les cellules +# for k in range ( 4 ) : # boucle sur les colonnes +# for l in range ( 8 ) : # boucle sur le multiplexeur de sortie +# for i in range ( nbit ) : # boucle sur les bits du mot +# x1 = GET_REF_X ( "bit%d_%d" % ( i, j ), "ref%d%d" % ( k, l ) ) +# y1 = GET_REF_Y ( "bit%d_%d" % ( i, j ), "ref%d%d" % ( k, l ) ) +# +# if i < 32 : +# value = data[2*(j + 8*k + l)] +# +# if (value>>i ) % 2 == 0 : LV_name.PHSEG ( NTRANS, 1, "", x1, y1 - 3, x1, y1 + 3 ) +# else : LV_name.PHSEG ( POLY , 1, "", x1, y1 - 3, x1, y1 + 3 ) +# +# else : +# value = data[2*(j + 8*k + l)+1] +# +# if ( value>>(i-32) ) % 2 == 0 : LV_name.PHSEG ( NTRANS, 1, "", x1, y1 - 3, x1, y1 + 3 ) +# else : LV_name.PHSEG ( POLY , 1, "", x1, y1 - 3, x1, y1 + 3 ) + + + + +########## ROM_VHDL ########## +############################## +def ROM_VHDL () : + global nbit + global LV_flags + global LV_ModelName + global nword + + print "ROM behavior not yet implemented" + +# fileName = LV_ModelName + ".vbe" +# +# file = open ( fileName, "w+" ) +# +# if nword == 64 : adrange = 6 +# elif nword == 128 : adrange = 7 +# elif nword == 256 : adrange = 8 +# elif nword == 512 : adrange = 9 +# elif nword == 1024 : adrange = 10 +# +# sBusWide0 = VHDL_BUS_WIDE ( nbit - 1, 0, nbit, LV_flags ) +# sBusWide1 = VHDL_BUS_WIDE ( adrange - 1, 0, nbit, LV_flags ) +# +# ## Entity description ## +# file.write ( "\nENTITY %s IS\n PORT (\n" % LV_ModelName ) +# +# file.write ( "%14s : in BIT;\n" % "ck" ) +# file.write ( "%14s : in BIT;\n" % "selrom" ) +# file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "ad", sBusWide1 ) ) +# file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "data", sBusWide0 ) ) +# +# ## Power supplies terminals ## +# file.write ( "%14s : in BIT;\n" % "vdd" ) +# file.write ( "%14s : in BIT\n" % "vss" ) +# +# ## End of entity description ## +# file.write ( " );\nEND %s;\n\n\n" % LV_ModelName ) +# +# ## Architecture description ## +# file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % LV_ModelName ) +# +# ## Signals ## +# +# +# +# ## Behavior ## +# file.write ( "\nBEGIN\n\n" ) +# +# +# +# +# +# ## Assert ## +# file.write ( " ASSERT (vdd = '1')\n" ) +# file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % LV_modelName ) +# file.write ( " SEVERITY WARNING;\n\n" ) +# +# +# file.write ( " ASSERT (vss = '0')\n" ) +# file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % LV_modelName ) +# file.write ( " SEVERITY WARNING;\n\n" ) +# +# ## End of Architectural description ## +# file.write ( "END VBE;\n" ) +# +# file.close () diff --git a/stratus1/src/dpgen/dpgen_ADSB2F.py b/stratus1/src/dpgen/dpgen_ADSB2F.py new file mode 100644 index 00000000..2a061fb2 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_ADSB2F.py @@ -0,0 +1,362 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_ADSB2F.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class DpgenAdsb2f ( Model ) : + + ## Interface ## + ############### + def Interface ( self ) : + global add_sub, c30, c31, i0, i1, q, vdd, vss + + self._nbit = self._param['nbit'] + + add_sub = SignalIn ( "add_sub", 1 ) + c30 = SignalOut ( "c30", 1 ) + c31 = SignalOut ( "c31", 1 ) + + i0 = SignalIn ( "i0", self._nbit ) + i1 = SignalIn ( "i1", self._nbit ) + q = SignalOut ( "q", self._nbit ) + + vdd = VddIn ( "vdd" ) + vss = VssIn ( "vss" ) + + ## Netlist ## + ############# + def Netlist ( self ) : + + # Liste des signaux internes + xorb = Signal ( "xorb", self._nbit ) + c = Signal ( "c", self._nbit ) + + pi = [] + gi = [] + for i in range ( self._nbit ) : + pi_bis = [] + gi_bis = [] + for j in range ( self._nbit ) : + pi_bis += [Signal("pi_%d_%d" % (i, j), 1 )] + gi_bis += [Signal("gi_%d_%d" % (i, j), 1 )] + pi += [pi_bis] + gi += [gi_bis] + + c30.Alias ( c[self._nbit-2] ) + c31.Alias ( c[self._nbit-1] ) + + # Ligne des XOR + self.Xorb = {} + for i in range ( self._nbit ) : + self.Xorb[i] = Inst ( "xr2_x1" + , "xorb%d" % i + , map = { 'i0' : add_sub + , 'i1' : i1[i] + , 'q' : xorb[i] + , 'vdd' : vdd + , 'vss' : vss + } + ) + + # Ligne des PIGI + self.Pigi = {} + for i in range ( 1, self._nbit ) : + self.Pigi[i] = Inst ( "halfadder_x2" + , "pigi%d" % i + , map = { 'a' : i0[i] + , 'b' : xorb[i] + , 'cout' : gi[0][i] + , 'sout' : pi[0][i] + , 'vdd' : vdd + , 'vss' : vss + } + ) + + # Ligne des PG + self.PgI1 = {} + self.PgI2 = {} + + for n in range ( 1, ilog2(self._nbit) + 1 ) : + + self.I1Bis = {} + self.I2Bis = {} + + for ipg in range ( iexp2(n) + iexp2(n-1), self._nbit, iexp2(n) ) : + inpg = ipg + + for npg in range ( iexp2(n-1) ) : + if inpg >= self._nbit : break + + self.I1Bis[inpg] = Inst ( "a2_x2" + , "pg_i1_%d_%d" % ( n, inpg ) + , map = { 'i0' : pi[n-1][ipg-1] + , 'i1' : pi[ilog2(npg)][inpg ] + , 'q' : pi[n][inpg ] + , 'vdd' : vdd + , 'vss' : vss + } + ) + + self.I2Bis[inpg] = Inst ( "oa22_x2" + , "pg_i2_%d_%d" % ( n, inpg ) + , map = { 'i0' : pi[ilog2(npg)][inpg ] + , 'i1' : gi[n-1 ][ipg-1] + , 'i2' : gi[ilog2(npg)][inpg ] + , 'q' : gi[n ][inpg ] + , 'vdd' : vdd + , 'vss' : vss + } + ) + + inpg += 1 + + self.PgI1[n] = self.I1Bis + self.PgI2[n] = self.I2Bis + + # Calcul des retenues + p = 2 + self.R = {} + for n in range ( 1, ilog2 ( self._nbit ) + 1 ) : + for isr in range ( iexp2 ( n - 1 ) ) : + if iexp2 ( n - 1 ) + isr >= self._nbit : break + + self.R[p] = Inst ( "oa22_x2" + , "r%d" % p + , map = { 'i0' : pi[ilog2(isr)][iexp2(n-1) + isr] + , 'i1' : c[iexp2(n-1) - 1] + , 'i2' : gi[ilog2(isr)][iexp2(n-1) + isr] + , 'q' : c[iexp2(n-1) + isr] + , 'vdd' : vdd + , 'vss' : vss + } + ) + p += 1 + + + # Calcul des sommes + self.S = {} + + for i in range ( 1, self._nbit ) : + self.S[i] = Inst ( "xr2_x1" + , "s%d" % i + , map = { 'i0' : pi[0][i] + , 'i1' : c[i-1] + , 'q' : q[i] + , 'vdd' : vdd + , 'vss' : vss + } + ) + + # Calcul somme et retenue du LSB + self.S[0] = Inst ( "fulladder_x2" + , "s0" + , map = { 'a1' : i0[0] + , 'a2' : i0[0] + , 'a3' : i0[0] + , 'a4' : i0[0] + , 'b1' : xorb[0] + , 'b2' : xorb[0] + , 'b3' : xorb[0] + , 'b4' : xorb[0] + , 'cin1' : add_sub + , 'cin2' : add_sub + , 'cin3' : add_sub + , 'cout' : c[0] + , 'sout' : q[0] + , 'vdd' : vdd + , 'vss' : vss + } + ) + + + ## Layout ## + ############ + def Layout ( self ) : + + twostage = -1 + + # Ligne des XOR + Place ( self.Xorb[0], NOSYM, XY ( 0, 0 ) ) + + for i in range ( 1, self._nbit ) : + if i % 2 == 0 : sym = NOSYM + else : sym = SYM_Y + PlaceTop ( self.Xorb[i], sym ) + + # Ligne des PIGI + if self._nbit > 1 : Place ( self.Pigi[1], SYM_Y, XY ( 45, 50 ) ) + + for i in range ( 2, self._nbit ) : + if i % 2 == 0 : sym = NOSYM + else : sym = SYM_Y + PlaceTop ( self.Pigi[i], sym ) + + # Ligne des PG + for n in range ( 1, ilog2(self._nbit) + 1, 2 ) : + twostage += 1 + pi = self._nbit - 1 + + for i in range ( self._nbit - 1, 0, -1 ) : + if i >= iexp2(n) + iexp2(n-1) and i & ( 1 << (n-1) ) : + + if pi % 2 == 0 : sym = NOSYM + else : sym = SYM_Y + + Place ( self.PgI1[n][i], sym, XY ( 125 + 55 * twostage, pi * 50 ) ) + Place ( self.PgI2[n][i], sym, XY ( 150 + 55 * twostage, pi * 50 ) ) + + pi -= 1 + + if i >= iexp2(n+1) + iexp2(n) and i & ( 1 << n ) : + + if pi % 2 == 0 : sym = NOSYM + else : sym = SYM_Y + Place ( self.PgI1[n+1][i], sym, XY ( 125 + 55 * twostage, pi * 50 ) ) + Place ( self.PgI2[n+1][i], sym, XY ( 150 + 55 * twostage, pi * 50 ) ) + + pi -= 1 + + # nbit n'est pas une puissance entiere de 2 + if self._nbit % ( iexp2 ( ilog2 ( self._nbit ) - 1 ) ) : twostage += 1 + + # Ligne retenue + for n in range ( 2, self._nbit + 1 ) : + if ( n - 1 ) % 2 == 0 : sym = NOSYM + else : sym = SYM_Y + Place ( self.R[n], sym, XY ( 125 + 55 * twostage, ( n - 1 ) * 50 ) ) + + + # Calcul des sommes + if self._nbit > 1 : Place ( self.S[1], NOSYM, XY ( 155 + 55 * twostage, 0 ) ) + + for i in range ( 2, self._nbit ) : + if ( i - 1 ) % 2 == 0 : sym = NOSYM + else : sym = SYM_Y + PlaceTop ( self.S[i], sym ) + + + # Calcul somme et retenue du LSB + Place ( self.S[0], NOSYM, XY ( 45, 0 ) ) + + + ########## VHDL ########## + ########################## + def Vbe ( self ) : + + name = self._name + + LV_flags = self._param['flags'] + + fileName = name + ".vbe" + + file = open ( fileName, "w+" ) + + sBusWide0 = VHDL_BUS_WIDE ( self._nbit - 1, 0, self._nbit, LV_flags ) + sBusWide1 = VHDL_BUS_WIDE ( self._nbit , 1, self._nbit, LV_flags ) + sBusWide2 = VHDL_BUS_WIDE ( self._nbit , 0, self._nbit, LV_flags ) + + ## Entity description ## + file.write ( "\nENTITY %s IS\n PORT (\n" % name ) + + file.write ( "%14s : in BIT;\n" % "add_sub" ) + file.write ( "%14s : out BIT;\n" % "c31" ) + file.write ( "%14s : out BIT;\n" % "c30" ) + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i0", sBusWide0 ) ) + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i1", sBusWide0 ) ) + file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "q", sBusWide0 ) ) + + ## Power supplies terminals ## + file.write ( "%14s : in BIT;\n" % "vdd" ) + file.write ( "%14s : in BIT\n" % "vss" ) + + ## End of entity description ## + file.write ( " );\nEND %s;\n\n\n" % name ) + + ## Architecture description ## + file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % name ) + + ## Signals ## + file.write ( " SIGNAL %20s : BIT_VECTOR %s;\n" % ( "carry", sBusWide2 ) ) + file.write ( " SIGNAL %20s : BIT_VECTOR %s;\n" % ( "xor_b", sBusWide0 ) ) + + ## Behavior ## + file.write ( "\nBEGIN\n\n" ) + + for i in range ( self._nbit - 1, -1, -1 ) : + file.write ( " xor_b(%ld) <= i1(%ld) xor add_sub;\n" % ( i, i ) ) + + file.write ( "\n" ) + + file.write ( " carry(0) <= add_sub;\n\n" ) + + file.write ( " q <= i0\n" ) + file.write ( " xor xor_b\n" ) + file.write ( " xor carry%s;\n\n" % sBusWide0 ) + + file.write ( " c31 <= carry(%ld);\n" % self._nbit ) + file.write ( " c30 <= carry(%ld);\n\n" % ( self._nbit - 1 ) ) + + file.write ( " carry%s <= ( i0 and xor_b)\n" % sBusWide1 ) + file.write ( " or ( i0 and carry%s)\n" % sBusWide0 ) + file.write ( " or (xor_b and carry%s);\n\n\n" % sBusWide0 ) + + ## Assert ## + file.write ( " ASSERT (vdd = '1')\n" ) + file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + file.write ( " ASSERT (vss = '0')\n" ) + file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + ## End of Architectural description ## + file.write ( "END VBE;\n" ) + + file.close () diff --git a/stratus1/src/dpgen/dpgen_Nul.py b/stratus1/src/dpgen/dpgen_Nul.py new file mode 100644 index 00000000..98928c86 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_Nul.py @@ -0,0 +1,406 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_Nul.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class DpgenNul ( Model ) : + + ## Interface ## + ############### + def Interface ( self ) : + + self._nbit = self._param['nbit'] + + self._i0 = SignalIn ( "i0", self._nbit ) + self._nul = SignalOut ( "nul", 1 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + + ## Netlist ## + ############# + def Netlist ( self ) : + global LV_prevTreeOut + global LV_oneShift + + global nul + + LV_prevTreeOut = -1 + LV_oneShift = 0 + + offset = 0 + depthNext = get_depth ( self._nbit, 0 ) + + nul = [] + for i in range ( self._nbit ) : + nul += [Signal ( "nul_%d" % i, 1 )] + + self.Nul = {} + + while ( 1 ) : + depth = depthNext + depthNext = get_depth ( self._nbit, depth + 1 ) + + offset = self.create_Netlist_Tree ( offset, depth, depthNext ) + + if depthNext == 0 : break # Simulation d'une boucle do ... while + + + + ########## Layout ########## + ############################ + def Layout ( self ) : + global LV_prevTreeOut + global LV_oneShift + + mDepth = ilog2 ( self._nbit ) + + LV_prevTreeOut = -1 + LV_oneShift = 0 + + offset = 0 + depthNext = get_depth ( self._nbit, 0 ) + + while ( 1 ) : + depth = depthNext + depthNext = get_depth ( self._nbit, depth + 1 ) + + offset = self.create_Layout_Tree ( offset, depth, depthNext ) + + if depthNext == 0 : break + + + + ########## VBE ########## + ######################### + def Vbe ( self ) : + + flags = self._param['flags'] + + fileName = self._name + ".vbe" + + file = open ( fileName, "w+" ) + + sBusWide = VHDL_BUS_WIDE ( self._nbit - 1, 0, self._nbit, flags ) + + ## Entity description ## + file.write ( "\nENTITY %s IS\n PORT (\n" % self._name ) + + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i0", sBusWide ) ) + file.write ( "%14s : out BIT;\n" % "nul" ) + + file.write ( "%14s : in BIT;\n" % "vdd" ) + file.write ( "%14s : in BIT\n" % "vss" ) + + ## End of entity description ## + file.write ( " );\nEND %s;\n\n\n" % self._name ) + + ## Architecture description ## + file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % self._name ) + + file.write ( "BEGIN\n\n" ) + + xl_zero = newxl () + xl_zero._size = self._nbit + + file.write ( " nul <= \'1\' WHEN (i0 = %s)\n" % xl_zero.xltovhdl () ) + file.write ( " ELSE \'0\';\n\n\n" ) + + ## Assert ## + file.write ( " ASSERT (vdd = '1')\n" ) + file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % self._name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + file.write ( " ASSERT (vss = '0')\n" ) + file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % self._name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + ## End of architecture description ## + file.write ( "END VBE;\n" ) + + file.close () + + + + + ########## create_Netlist_Tree ########## + ######################################### + def create_Netlist_Tree ( self, aOffset, amDepth, amDepthNext ) : + global LV_prevTreeOut + global LV_oneShift + + global nul + + if amDepthNext > 0 : polarity = amDepthNext % 2 + else : polarity = amDepth % 2 + + if not ( amDepth ) : + if not ( amDepthNext ) : + # Pathological case : the zero detect is reduced to only one bit! This is only a inversor. + self.Nul[aOffset] = Inst ( "inv_x4" + , "nul_%ld" % aOffset + , map = { 'i' : self._i0[aOffset] + , 'nq' : self._nul + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + LV_prevTreeOut = aOffset + + if ( amDepth % 2 ) == polarity : + # This branch will skip an even number of layer, we keep the same polarity. + self._i0[aOffset].Alias ( nul[aOffset] ) + else : + # There is a polarity inversion. + self.Nul[aOffset] = Inst ( "inv_x4" + , "nul_%ld" % aOffset + , map = { 'i' : self._i0[aOffset] + , 'nq' : nul[aOffset] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + LV_oneShift = 1 + aOffset += 1 + + aOffset += 1 + return aOffset + + + # Build the tree. + for depth in range ( amDepth ) : + mk = iexp2 ( amDepth - depth - 1 ) + + for k in range ( mk ) : + if depth : i_offset = iexp2 ( depth - 1 ) - 1 + else : i_offset = 0 + + cell_index = iexp2 ( depth + 1 ) * k + iexp2 ( depth ) - 1 + aOffset + + i1_index = iexp2 ( depth + 1 ) * k + iexp2 ( depth ) + i_offset + aOffset + i0_index = iexp2 ( depth + 1 ) * k + i_offset + aOffset + + if depth % 2 : sModel = "na2_x1" + else : sModel = "no2_x1" + + thisMap = {} + + thisMap['nq'] = nul[cell_index] + + if depth : + thisMap['i0'] = nul[i0_index] + thisMap['i1'] = nul[i1_index] + else : + thisMap['i0'] = self._i0[i0_index - LV_oneShift] + thisMap['i1'] = self._i0[i1_index - LV_oneShift] + + # Special case of the last layer. + if mk == 1 and LV_prevTreeOut < 0 : + if not ( amDepthNext ) : + # This is the only tree in the operator. + if depth % 2 : + sModel = "a2_x4" + + thisMap['q'] = self._nul + if thisMap.has_key('nq') : del thisMap['nq'] + else : + sModel = "no2_x4" + thisMap['nq'] = self._nul + + else : + if depth % 2 == polarity : + # Only for the first tree : adjust the polarity. + if depth % 2 : sModel = "a2_x2" + else : sModel = "o2_x2" + + if thisMap.has_key('nq') : del thisMap['nq'] + thisMap['q'] = nul[cell_index] + + thisMap['vdd'] = self._vdd + thisMap['vss'] = self._vss + + self.Nul[cell_index] = Inst ( sModel + , "nul_%ld" % cell_index + , map = thisMap + ) + + depth += 1 # Attention : difference entre les boucles en c et les boucles en python + + # Check if there is a ripple part. + if LV_prevTreeOut < 0 : + LV_prevTreeOut = cell_index + + return ( aOffset + iexp2 ( amDepth ) ) + + # Add the ripple part. + cell_index = aOffset - 1 + + thisMap = {} + + if not ( amDepthNext ) : + if depth % 2 : + sModel = "a2_x4" + thisMap['q'] = self._nul + else : + sModel = "no2_x4" + thisMap['nq'] = self._nul + + else : + if depth % 2 : sModel = "na2_x1" + else : sModel = "no2_x1" + + if depth % 2 != polarity : + thisMap['nq'] = nul[cell_index] + else : + thisMap['q'] = nul[cell_index] + + if depth % 2 == polarity : + if depth % 2 : sModel = "a2_x2" + else : sModel = "o2_x2" + + i1_index = iexp2 ( amDepth - 1 ) - 1 + aOffset + i0_index = LV_prevTreeOut + + thisMap['i0'] = nul[i0_index] + thisMap['i1'] = nul[i1_index] + + thisMap['vdd'] = self._vdd + thisMap['vss'] = self._vss + + self.Nul[aOffset-1] = Inst ( sModel + , "nul_%ld" % ( aOffset - 1 ) + , map = thisMap + ) + + LV_prevTreeOut = cell_index + + return ( aOffset + iexp2 ( amDepth ) ) + + + + ########## create_Layout_Tree ########## + ######################################## + def create_Layout_Tree ( self, aOffset, amDepth, amDepthNext ) : + global LV_oneShift + global LV_prevTreeOut + + if amDepthNext > 0 : polarity = amDepthNext % 2 + else : polarity = amDepth % 2 + + if not ( amDepth ) : + if not ( amDepthNext ) : + # Cas pathologique : detection a un seul bit : c'est un inverseur + dpgen_place ( self.Nul[aOffset], 0, aOffset * 50 ) + else : + LV_prevTreeOut = aOffset + + if ( amDepth % 2 ) != polarity : dpgen_place ( self.Nul[aOffset], 0, aOffset * 50 ) + + LV_oneShift = 1 + aOffset += 1 + + aOffset += 1 + + return aOffset + + + # Build the tree. + for depth in range ( amDepth ) : + mk = iexp2 ( amDepth - depth - 1 ) + + for k in range ( mk ) : + cell_index = iexp2 ( depth + 1 ) * k + iexp2 ( depth ) - 1 + aOffset + + if depth % 2 : sModel = "na2_x1" + else : sModel = "no2_x1" + + # Special case of the last layer. + if mk == 1 and LV_prevTreeOut < 0 : + if not ( amDepthNext ) : + # This is the only tree in the operator. + if depth % 2 : sModel = "a2_x4" + else : sModel = "no2_x4" + + else : + if depth % 2 == polarity : + # Only for the first tree : adjust the polarity. + if depth % 2 : sModel = "a2_x2" + else : sModel = "o2_x2" + + dpgen_place ( self.Nul[cell_index], 0, cell_index * 50 ) + + if LV_prevTreeOut < 0 : + LV_prevTreeOut = cell_index + + return ( aOffset + iexp2 ( amDepth ) ) + + + if not ( amDepthNext ) : + if depth % 2 : sModel = "a2_x4" + else : sModel = "no2_x4" + + else : + if depth % 2 : sModel = "na2_x1" + else : sModel = "no2_x1" + + if depth % 2 == polarity : + if depth % 2 : sModel = "a2_x2" + else : sModel = "o2_x2" + + cell_index = aOffset - 1 + + dpgen_place ( self.Nul[aOffset-1], 0, ( aOffset - 1 ) * 50 ) + + LV_prevTreeOut = cell_index + + return ( aOffset + iexp2 ( amDepth ) ) diff --git a/stratus1/src/dpgen/dpgen_RAM.py b/stratus1/src/dpgen/dpgen_RAM.py new file mode 100644 index 00000000..939e4847 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_RAM.py @@ -0,0 +1,675 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_RAM.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class DpgenRam ( Model ) : + + ## Interface ## + ############### + def Interface ( self ) : + global adrange + + self._nbit = self._param['nbit'] + self._nmot = self._param['nword'] + + if self._nbit % 2 == 1 or self._nbit > 64 or self._nbit < 2 : + print "Error in DpgenRam : the bit number must be even and no larger than 64\n" + sys.exit ( 3 ) + + if self._nmot % 8 != 0 or self._nmot > 256 or self._nmot < 32 : + print "Error in instanciaton of DpgenRam" + print "The word number (nword = %d) " % self._nmot, "must be multiple of 8, at least 32 and no larger than 256.\n" + sys.exit ( 3 ) + + if self._nmot > 128 : adrange = 8 + elif self._nmot > 64 : adrange = 7 + elif self._nmot > 32 : adrange = 6 + else : adrange = 5 + + # Connecteurs externes + self._ck = SignalIn ( "ck", 1 ) + self._w = SignalIn ( "w", 1 ) + self._selram = SignalIn ( "selram", 1 ) + + self._ad = SignalIn ( "ad", adrange ) + self._datain = SignalIn ( "datain", self._nbit ) + + self._dataout = TriState ( "dataout", self._nbit ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + + ## Netlist ## + ############# + def Netlist ( self ) : + + # Signaux + prech = Signal ( "prech", 1 ) + prechbis = Signal ( "prechbis", 1 ) + + ad0x = Signal ( "ad0x", 1 ) + nad0x = Signal ( "nad0x", 1 ) + + nsense = Signal ( "nsense", 1 ) + sensex = Signal ( "sensex", 1 ) + nsensex = Signal ( "nsensex", 1 ) + + selramx = Signal ( "selramx", 1 ) + + nwrite = Signal ( "nwrite", 1 ) + writex = Signal ( "writex", 1 ) + + ndec00 = Signal ( "ndec00", 1 ) + ndec01 = Signal ( "ndec01", 1 ) + ndec10 = Signal ( "ndec10", 1 ) + ndec11 = Signal ( "ndec11", 1 ) + + nck = Signal ( "nck", 1 ) + nckx = Signal ( "nckx", 1 ) + nckxbis = Signal ( "nckxbis", 1 ) + + ad3x = Signal ( "ad3x", 1 ) + nad3x = Signal ( "nad3x", 1 ) + ad4x = Signal ( "ad4x", 1 ) + nad4x = Signal ( "nad4x", 1 ) + if adrange > 5 : + ad5x = Signal ( "ad5x", 1 ) + nad5x = Signal ( "nad5x", 1 ) + if adrange > 6 : + ad6x = Signal ( "ad6x", 1 ) + nad6x = Signal ( "nad6x", 1 ) + if adrange > 7 : + ad7x = Signal ( "ad7x", 1 ) + nad7x = Signal ( "nad7x", 1 ) + + bus0 = [] + nbus0 = [] + bus1 = [] + nbus1 = [] + + sel = [] + nsel = [] + selx = [] + + ndeca = [] + ndecb = [] + for i in range ( self._nbit ) : + bus0 += [Signal ( "bus0_%d" % i, 1 )] + nbus0 += [Signal ( "nbus0_%d" % i, 1 )] + bus1 += [Signal ( "bus1_%d" % i, 1 )] + nbus1 += [Signal ( "nbus1_%d" % i, 1 )] + + for i in range ( self._nmot ) : + sel += [Signal ( "sel%d" % i, 1 )] + nsel += [Signal ( "nsel%d" % i, 1 )] + selx += [Signal ( "selx%d" % i, 1 )] + + ndeca += [Signal ( "ndeca%d" % i, 1 )] + ndecb += [Signal ( "ndecb%d" % i, 1 )] + + + # Lignes de bit + self.Prech = {} + self.Bit = {} + self.Sense = {} + + bottom = 0 + for i in range ( self._nbit ) : + self.Prech[i] = Inst ( "ram_prech_data" + , "prech%d" % i + , map = { 'prech' : prech + , 'bit0' : bus0[i] + , 'nbit0' : nbus0[i] + , 'bit1' : bus1[i] + , 'nbit1' : nbus1[i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.BitBis = {} + for j in range ( 0, self._nmot, 4 ) : + + self.BitBis[j] = Inst ( "ram_mem_data" + , "bit_%d_%d" % ( i, j ) + , map = { 'selxi' : selx[j] + , 'bit0' : bus0[i] + , 'nbit0' : nbus0[i] + , 'bit1' : bus1[i] + , 'nbit1' : nbus1[i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.BitBis[j+2] = Inst ( "ram_mem_data" + , "bit_%d_%d" % ( i, j + 2 ) + , map = { 'selxi' : selx[j+2] + , 'bit0' : bus0[i] + , 'nbit0' : nbus0[i] + , 'bit1' : bus1[i] + , 'nbit1' : nbus1[i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Bit[i] = self.BitBis + + self.Sense[i] = Inst ( "ram_sense_data" + , "sense%d" % i + , map = { 'bit0' : bus0[i] + , 'nbit0' : nbus0[i] + , 'bit1' : bus1[i] + , 'nbit1' : nbus1[i] + , 'ad0x' : ad0x + , 'nad0x' : nad0x + , 'sensex' : sensex + , 'nsensex' : nsensex + , 'prechx' : prechbis + , 'writex' : writex + , 'din' : self._datain[i] + , 'dout' : self._dataout[i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Premiere ligne de la zone des buffers + self.PrechBuf0 = Inst ( "ram_prech_buf0" + , "prechbuf0" + , map = { 'i' : nckx + , 'nq' : prech + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Buf0 = {} + for j in range ( 0, self._nmot, 4 ) : + self.Buf0[j] = Inst ( "ram_mem_buf0" + , "buf0_%d" % j + , map = { 'i' : nsel[j] + , 'nq' : selx[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Buf0[j+2] = Inst ( "ram_mem_buf0" + , "buf0_%d" % ( j + 2 ) + , map = { 'i' : nsel[j+2] + , 'nq' : selx[j+2] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SenseBuf0 = Inst ( "ram_sense_buf0" + , "sensebuf0" + , map = { 'ad0' : self._ad[0] + , 'nsense' : nsense + , 'nckx' : nckxbis + , 'nwrite' : nwrite + , 'ad0x' : ad0x + , 'nad0x' : nad0x + , 'sensex' : sensex + , 'nsensex' : nsensex + , 'prech' : prechbis + , 'writex' : writex + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Deuxieme ligne de la zone des buffers + self.PrechBuf1 = Inst ( "ram_prech_buf1" + , "prechbuf1" + , map = { 'nck' : nck + , 'nckx' : nckx + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Buf1 = {} + for j in range ( 0, self._nmot, 4 ) : + self.Buf1[j] = Inst ( "ram_mem_buf1" + , "buf1_%d" % j + , map = { 'seli' : sel[j] + , 'nck' : nck + , 'selramx' : selramx + , 'nseli' : nsel[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Buf1[j+2] = Inst ( "ram_mem_buf1" + , "buf1_%d" % ( j + 2 ) + , map = { 'seli' : sel[j+2] + , 'nck' : nck + , 'selramx' : selramx + , 'nseli' : nsel[j+2] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SenseBuf1 = Inst ( "ram_sense_buf1" + , "sensebuf1" + , map = { 'ck' : self._ck + , 'selram' : self._selram + , 'w' : self._w + , 'nck' : nck + , 'selramx' : selramx + , 'nsense' : nsense + , 'nwrite' : nwrite + , 'nckx' : nckxbis + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Premiere ligne de la zone du decodeur + self.PrechDecB = Inst ( "ram_prech_dec0" + ,"prechdecb" + , map = { 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Dec = {} + for j in range ( 0, self._nmot, 8 ) : + self.Dec[j] = Inst ( "ram_mem_deci" + , "dec_%d" % j + , map = { 'i0' : ndeca[j] + , 'i1' : ndecb[j] + , 'i2' : ndec00 + , 'seli' : sel[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Dec[j+2] = Inst ( "ram_mem_deci" + , "dec_%d" % ( j + 2 ) + , map = { 'i0' : ndeca[j] + , 'i1' : ndecb[j] + , 'i2' : ndec01 + , 'seli' : sel[j+2] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Dec[j+4] = Inst ( "ram_mem_deci" + , "dec_%d" % ( j + 4 ) + , map = { 'i0' : ndeca[j] + , 'i1' : ndecb[j] + , 'i2' : ndec10 + , 'seli' : sel[j+4] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Dec[j+6] = Inst ( "ram_mem_deci" + , "dec_%d" % ( j + 6 ) + , map = { 'i0' : ndeca[j] + , 'i1' : ndecb[j] + , 'i2' : ndec11 + , 'seli' : sel[j+6] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SenseDecAd12 = Inst ( "ram_sense_decad12" + , "sensedecad12" + , map = { 'ad1' : self._ad[1] + , 'ad2' : self._ad[2] + , 'ndec00' : ndec00 + , 'ndec01' : ndec01 + , 'ndec10' : ndec10 + , 'ndec11' : ndec11 + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Deuxieme ligne de la zone du decodeur + if adrange == 8 : # adresse sur 8 bits : on decode 5 bits + self.PrechDecU = Inst ( "ram_prech_dec0" + , "prechdecu" + , map = { 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.MemDec = {} + for j in range ( 0, self._nmot, 8 ) : + thisMap = { 'ndeca' : ndeca[j] + , 'ndecb' : ndecb[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if ( j >> 3 ) % 2 == 0 : thisMap['i0'] = nad3x + else : thisMap['i0'] = ad3x + + if ( j >> 4 ) % 2 == 0 : thisMap['i1'] = nad4x + else : thisMap['i1'] = ad4x + + if ( j >> 5 ) % 2 == 0 : thisMap['i2'] = nad5x + else : thisMap['i2'] = ad5x + + if ( j >> 6 ) % 2 == 0 : thisMap['i3'] = nad6x + else : thisMap['i3'] = ad6x + + if ( j >> 7 ) % 2 == 0 : thisMap['i4'] = nad7x + else : thisMap['i4'] = ad7x + + self.MemDec[j] = Inst ( "ram_mem_dec5" + , "memdec%d" % j + , map = thisMap + ) + + self.SenseDecAd = Inst ( "ram_sense_decad5" + , "sensedecad" + , map = { 'ad3' : self._ad[3] + , 'ad4' : self._ad[4] + , 'ad5' : self._ad[5] + , 'ad6' : self._ad[6] + , 'ad7' : self._ad[7] + , 'ad3x' : ad3x + , 'nad3x' : nad3x + , 'ad4x' : ad4x + , 'nad4x' : nad4x + , 'ad5x' : ad5x + , 'nad5x' : nad5x + , 'ad6x' : ad6x + , 'nad6x' : nad6x + , 'ad7x' : ad7x + , 'nad7x' : nad7x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 7 : # adresse sur 7 bits : on decode 4 bits + self.PrechDecU = Inst ( "ram_prech_dec0" + , "prechdecu" + , map = { 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.MemDec = {} + for j in range ( 0, self._nmot, 8 ) : + thisMap = { 'ndeca' : ndeca[j] + , 'ndecb' : ndecb[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if ( j >> 3 ) % 2 == 0 : thisMap['i0'] = nad3x + else : thisMap['i0'] = ad3x + + if ( j >> 4 ) % 2 == 0 : thisMap['i1'] = nad4x + else : thisMap['i1'] = ad4x + + if ( j >> 5 ) % 2 == 0 : thisMap['i2'] = nad5x + else : thisMap['i2'] = ad5x + + if ( j >> 6 ) % 2 == 0 : thisMap['i3'] = nad6x + else : thisMap['i3'] = ad6x + + self.MemDec[j] = Inst ( "ram_mem_dec4" + , "memdec%d" % j + , map = thisMap + ) + + self.SenseDecAd = Inst ( "ram_sense_decad4" + , "sensedecad" + , map = { 'ad3' : self._ad[3] + , 'ad4' : self._ad[4] + , 'ad5' : self._ad[5] + , 'ad6' : self._ad[6] + , 'ad3x' : ad3x + , 'nad3x' : nad3x + , 'ad4x' : ad4x + , 'nad4x' : nad4x + , 'ad5x' : ad5x + , 'nad5x' : nad5x + , 'ad6x' : ad6x + , 'nad6x' : nad6x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 6 : # adresse sur 6 bits : on decode 3 bits + self.PrechDecU = Inst ( "ram_prech_dec0" + , "prechdecu" + , map = { 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.MemDec = {} + for j in range ( 0, self._nmot, 8 ) : + thisMap = { 'ndeca' : ndeca[j] + , 'ndecb' : ndecb[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if ( j >> 3 ) % 2 == 0 : thisMap['i0'] = nad3x + else : thisMap['i0'] = ad3x + + if ( j >> 4 ) % 2 == 0 : thisMap['i1'] = nad4x + else : thisMap['i1'] = ad4x + + if ( j >> 5 ) % 2 == 0 : thisMap['i2'] = nad5x + else : thisMap['i2'] = ad5x + + self.MemDec[j] = Inst ( "ram_mem_dec3" + , "memdec%d" % j + , map = thisMap + ) + + self.SenseDecAd = Inst ( "ram_sense_decad3" + , "sensedecad" + , map = { 'ad3' : self._ad[3] + , 'ad4' : self._ad[4] + , 'ad5' : self._ad[5] + , 'ad3x' : ad3x + , 'nad3x' : nad3x + , 'ad4x' : ad4x + , 'nad4x' : nad4x + , 'ad5x' : ad5x + , 'nad5x' : nad5x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 5 : # adresse sur 5 bits : on decode 2 bits + self.PrechDecU = Inst ( "ram_prech_dec0" + , "prechdecu" + , map = { 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.MemDec = {} + for j in range ( 0, self._nmot, 8 ) : + thisMap = { 'ndeca' : ndeca[j] + , 'ndecb' : ndecb[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if ( j >> 3 ) % 2 == 0 : thisMap['i0'] = nad3x + else : thisMap['i0'] = ad3x + + if ( j >> 4 ) % 2 == 0 : thisMap['i1'] = nad4x + else : thisMap['i1'] = ad4x + + self.MemDec[j] = Inst ( "ram_mem_dec2" + , "memdec%d" % j + , map = thisMap + ) + + self.SenseDecAd = Inst ( "ram_sense_decad2" + , "sensedecad" + , map = { 'ad3' : self._ad[3] + , 'ad4' : self._ad[4] + , 'ad3x' : ad3x + , 'nad3x' : nad3x + , 'ad4x' : ad4x + , 'nad4x' : nad4x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ########## Layout ########## + ############################ + def Layout ( self ) : + + HCELL = 50 + + # Lignes de bit + bottom = 0 + + for i in range ( self._nbit ) : + if i % 2 : # lignes impaires + sym1 = SYM_Y + sym2 = SYMXY + else : # lignes paires + sym1 = NOSYM + sym2 = SYM_X + + Place ( self.Prech[i], sym1, XY ( 0, bottom + i * HCELL ) ) + + for j in range ( 0, self._nmot, 4 ) : + PlaceRight ( self.Bit[i][j], sym2 ) + PlaceRight ( self.Bit[i][j+2], sym1 ) + + PlaceRight ( self.Sense[i], sym1 ) + + # Premiere ligne de la zone des buffers + bottom = self._nbit * HCELL + + Place ( self.PrechBuf0, NOSYM, XY ( 0, bottom ) ) + + for j in range ( 0, self._nmot, 4 ) : + PlaceRight ( self.Buf0[j], SYM_X ) + PlaceRight ( self.Buf0[j+2], NOSYM ) + + PlaceRight ( self.SenseBuf0, NOSYM ) + + # Deuxieme ligne de la zone des buffers + bottom = ( self._nbit + 1 ) * HCELL + + Place ( self.PrechBuf1, SYM_Y, XY ( 0, bottom ) ) + + for j in range ( 0, self._nmot, 4 ) : + PlaceRight ( self.Buf1[j], SYMXY ) + PlaceRight ( self.Buf1[j+2], SYM_Y ) + + PlaceRight ( self.SenseBuf1, SYM_Y ) + + # Premiere ligne de la zone du decodeur + bottom = ( self._nbit + 2 ) * HCELL + + Place ( self.PrechDecB, NOSYM, XY ( 0, bottom ) ) + + for j in range ( 0, self._nmot, 8 ) : + PlaceRight ( self.Dec[j], SYM_X ) + PlaceRight ( self.Dec[j+2], NOSYM ) + PlaceRight ( self.Dec[j+4], SYM_X ) + PlaceRight ( self.Dec[j+6], NOSYM ) + + PlaceRight ( self.SenseDecAd12, NOSYM ) + + # Deuxieme ligne de la zone du decodeur + bottom = ( self._nbit + 3 ) * HCELL + + if adrange == 8 : # adresse sur 8 bits : on decode 5 bits + Place ( self.PrechDecU, SYM_Y, XY ( 0, bottom ) ) + for j in range ( 0, self._nmot, 8 ) : PlaceRight ( self.MemDec[j], SYM_Y ) + PlaceRight ( self.SenseDecAd, SYM_Y ) + + if adrange == 7 : # adresse sur 7 bits : on decode 4 bits + Place ( self.PrechDecU, SYM_Y, XY ( 0, bottom ) ) + for j in range ( 0, self._nmot, 8 ) : PlaceRight ( self.MemDec[j], SYM_Y ) + PlaceRight ( self.SenseDecAd, SYM_Y ) + + if adrange == 6 : # adresse sur 6 bits : on decode 3 bits + Place ( self.PrechDecU, SYM_Y, XY ( 0, bottom ) ) + for j in range ( 0, self._nmot, 8 ) : PlaceRight ( self.MemDec[j], SYM_Y ) + PlaceRight ( self.SenseDecAd, SYM_Y ) + + if adrange == 5 : # adresse sur 5 bits : on decode 2 bits + Place ( self.PrechDecU, SYM_Y, XY ( 0, bottom ) ) + for j in range ( 0, self._nmot, 8 ) : PlaceRight ( self.MemDec[j], SYM_Y ) + PlaceRight ( self.SenseDecAd, SYM_Y ) + + + ## VBE ## + ######### + def Vbe () : + print "RAM behavior not yet implemented" diff --git a/stratus1/src/dpgen/dpgen_RF1.py b/stratus1/src/dpgen/dpgen_RF1.py new file mode 100644 index 00000000..d42bf426 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_RF1.py @@ -0,0 +1,1441 @@ +#!/usr/bin/pythn + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_RF1.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +# Banc de registre double acces : une lecture, une ecriture +# Le programme genere une net-list et un placement optimise. +# On peut generer trois types d'operateurs: +# - banc de registres sans decodeur +# - banc de registres avec decodeur +# - banc de registre de LV_type fifo +# +# La largeur est egale a ( nmot * 25 ) + 100 +# La hauteur est egale a ( nbit + 2 ) * 50 sans decodeur +# ( nbit + 6 ) * 50 avec decodeur +# ( nbit + 8 ) * 50 pour la fifo +# +# Pour la partie "donnees", on utilise les LV_names suivantes : +# colonne d'entree +# - rf_inmux_mem +# - rf_inmux_buf_2 +# - rf_inmux_buf_4 +# colonne centrale +# - rf_mid_mem +# - rf_mid_mem_r0 +# - rf_mid_buf_2 +# - rf_mid_buf_4 +# colonne de sortie +# - rf_out_mem +# - rf_out_buf_2 +# - rf_out_buf_4 +# +# Pour le controleur fifo, on utilise les LV_names suivantes : +# - rf_fifo_buf +# - rf_fifo_clock +# - rf_fifo_empty +# - rf_fifo_full +# - rf_fifo_inc +# - rf_fifo_nop +# - rf_fifo_ok +# - rf_fifo_orand4 +# - rf_fifo_orand5 +# - rf_fifo_ptreset +# - rf_fifo_ptset +# +# Pour le decodeur, on utilise les LV_names suivantes : +# - rf_dec_bufad0 +# - rf_dec_bufad1 +# - rf_dec_bufad2 +# - rf_dec_nbuf +# - rf_dec_nor3 +# - rf_dec_nao3 +# - rf_dec_nand2 +# - rf_dec_nand3 +# - rf_dec_nand4 + + +#---------------------------------------------------------------- +# DEBUT PROGRAMME PRINCIPAL +#---------------------------------------------------------------- +# aFunction : le type : +# DPGEN_RF1 : sans decodeur +# DPGEN_RF1R0 : sans decodeur, avec R0 colle a 0 +# DPGEN_RF1D : avec decodeur +# DPGEN_RF1DR0 : avec decodeur, avec R0 colle a 0 +# DPGEN_FIFO : une fifo +# +# Liste des parametres : +# ModelName : nom de modele. +# flags : indexation des connecteurs. +# n : nombre de bits (largeur du bus). +# nmot : nombre de mots. +# - le nombre de mots doit etre pair et =< 32 +# - le nombre de bits doit etre pair, non nul et =< 64 +#---------------------------------------------------------------- + + + +################### +##### top_RF1 ##### +################### +class top_rf1 ( Model ) : + + ## Interface ## + ############### + def Interface ( self, nbit, nword, type ) : + global nbitu, hbuf, adrange + + nbitu = 0 + + if nword % 2 == 1 or nword > 32 or nword < 4 : + print "Error in DpgenRf1 : the word number must be even larger than 4 and no larger than 32\n" + sys.exit ( 3 ) + + if nword == 4 and ( type == 2 or type == 3 ) : + print "Error in DpgenRf1 : the word number must be larger than 4\n" + sys.exit ( 3 ) + + if nbit % 2 == 1 or nbit > 64 or nbit < 2 : + print "Error in DpgenRf1 : the bit number must be even and no larger than 64\n" + sys.exit ( 3 ) + + adrange = 2 + if nword > 4 : adrange = 3 + if nword > 8 : adrange = 4 + if nword > 16 : adrange = 5 + + if type < 2 : # c'est un banc de registres sans decodeur + self._ck = SignalIn ( "ck", 1 ) + self._sel = SignalIn ( "sel", 1 ) + + self._selr = SignalIn ( "selr", nword ) + self._selw = SignalIn ( "selw", nword ) + self._datain0 = SignalIn ( "datain0", nbit ) + self._datain1 = SignalIn ( "datain1", nbit ) + self._dataout = SignalOut ( "dataout", nbit ) + + elif type < 4 : # c'est un banc de registres avec decodeur + self._ck = SignalIn ( "ck", 1 ) + self._sel = SignalIn ( "sel", 1 ) + self._wen = SignalIn ( "wen", 1 ) + self._ren = SignalIn ( "ren", 1 ) + + self._adr = SignalIn ( "adr", adrange ) + self._adw = SignalIn ( "adw", adrange ) + self._datain0 = SignalIn ( "datain0", nbit ) + self._datain1 = SignalIn ( "datain1", nbit ) + self._dataout = SignalOut ( "dataout", nbit ) + + self._selr = Signal ( "selr", nword ) + self._selw = Signal ( "selw", nword ) + + else : # c'est une fifo + self._ck = SignalIn ( "ck", 1 ) + self._reset = SignalIn ( "reset", 1 ) + self._r = SignalIn ( "r", 1 ) + self._w = SignalIn ( "w", 1 ) + self._rok = SignalInOut ( "rok", 1 ) + self._wok = SignalInOut ( "wok", 1 ) + self._sel = SignalIn ( "sel", 1 ) + + self._datain0 = SignalIn ( "datain0", nbit ) + self._datain1 = SignalIn ( "datain1", nbit ) + self._dataout = SignalOut ( "dataout", nbit ) + + self._selr = Signal ( "selr", nword ) + self._selw = Signal ( "selw", nword ) + self._ckok = Signal ( "ckok", 1 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + + ## Netlist ## + ############## + def Netlist ( self, nbit, nword, type ) : + + hbuf = 2 # hauteur des buffers (2 ou 4 slices) : non utilise + + # choix des LV_names buffer + if hbuf == 2 : # buffers sur 2 slices + cell_in_buf = "rf_inmux_buf_2" + cell_mid_buf = "rf_mid_buf_2" + cell_out_buf = "rf_out_buf_2" + + elif hbuf == 4 : # buffers sur 4 slices + cell_in_buf = "rf_inmux_buf_4" + cell_mid_buf = "rf_mid_buf_4" + cell_out_buf = "rf_out_buf_4" + + + sel0 = Signal ( "sel0", 1 ) + sel1 = Signal ( "sel1", 1 ) + xck = Signal ( "xck", 1 ) + nck = Signal ( "nck", 1 ) + + rbus = Signal ( "rbus", nbit ) + dinx = Signal ( "dinx", nbit ) + + write = [] + read = [] + for i in range ( nword ) : + write += [Signal ( "write%d" % i, 1 )] + read += [Signal ( "read%d" % i, 1 )] + + if type != 4 : + nandr = [] + for i in range ( nword >> 1 ) : + nandr += [Signal ( "nandr%d" % i, 1 )] + + cell_in_mem = "rf_inmux_mem" + cell_out_mem = "rf_out_mem" + + self.In = {} + self.Bit = {} + self.Out = {} + + for i in range ( nbit ) : + self.In[nbit-1-i] = Inst ( cell_in_mem + , "in%d" % ( nbit - 1 - i ) + , map = { 'datain0' : self._datain0[nbit - 1 - i] + , 'datain1' : self._datain1[nbit - 1 - i] + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'dinx' : dinx[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.BitBis = {} + + for j in range ( 0, nword, 2 ) : + + if j == 0 and type % 2 == 1 : cell_mid_mem = "rf_mid_mem_r0" + else : cell_mid_mem = "rf_mid_mem" + + self.BitBis[j] = Inst ( cell_mid_mem + , "bit%d_%d" % ( nbit - 1 - i, j ) + , map = { 'dinx' : dinx[nbit - 1 - i] + , 'write' : write[j] + , 'read' : read[j] + , 'rbus' : rbus[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + cell_mid_mem = "rf_mid_mem" + + self.BitBis[j+1] = Inst ( cell_mid_mem + , "bit%d_%d" % ( nbit - 1 - i, j + 1 ) + , map = { 'dinx' : dinx[nbit - 1 - i] + , 'write' : write[j + 1] + , 'read' : read[j + 1] + , 'rbus' : rbus[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Bit[nbit-1-i] = self.BitBis + + self.Out[nbit-1-i] = Inst ( cell_out_mem + , "out%d" % ( nbit - 1 - i ) + , map = { 'rbus' : rbus[nbit - 1 - i] + , 'xcks' : xck + , 'dataout' : self._dataout[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ## Placement de la ligne contenant les buffers ## + if type < 4 : + self.InBuf = Inst ( cell_in_buf + , "inbuf" + , map = { 'ck' : self._ck + , 'sel' : self._sel + , 'nck' : nck + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.InBuf = Inst ( cell_in_buf + , "inbuf" + , map = { 'ck' : self._ckok + , 'sel' : self._sel + , 'nck' : nck + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Buf = {} + + for j in range ( 0, nword, 2 ) : + self.Buf[j] = Inst ( cell_mid_buf + , "buf%d" % j + , map = { 'selr' : self._selr[j] + , 'selw' : self._selw[j] + , 'nck' : nck + , 'read' : read[j] + , 'write' : write[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + self.Buf[j+1] = Inst ( cell_mid_buf + , "buf%d" % ( j + 1 ) + , map = { 'selr' : self._selr[j + 1] + , 'selw' : self._selw[j + 1] + , 'nck' : nck + , 'read' : read[j + 1] + , 'write' : write[j + 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.OutBuf = Inst ( cell_out_buf + , "outbuf" + , map = { 'nck' : nck + , 'xcks' : xck + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ## Placement des lignes de bit au dessus des buffers ## + cell_in_mem = "rf_inmux_mem" + cell_out_mem = "rf_out_mem" + + for i in range ( nbitu ) : + self.In[nbitu-1-i] = Inst ( cell_in_mem + , "in%d" % ( nbitu - 1 - i ) + , map = { 'datain0' : datain0[nbitu - 1 - i] + , 'datain1' : datain1[nbitu - 1 - i] + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'dinx' : dinx[nbitu - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.BitBis = {} + + for j in range ( 0, nword, 2 ) : + if j == 0 and type % 2 == 1 : cell_mid_mem = "rf_mid_mem_r0" + else : cell_mid_mem = "rf_mid_mem" + + self.BitBis[j] = Inst ( cell_mid_mem + , "bit%d_%d" % ( nbitu - 1 - i, j ) + , map = { 'dinx' : dinx[nbitu - 1 - i] + , 'write' : write[j] + , 'read' : read[j] + , 'rbus' : rbus[nbitu - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + cell_mid_mem = "rf_mid_mem" + + self.BitBis[j+1] = Inst ( cell_mid_mem + , "bit%d_%d" % ( nbitu - 1 - i, j + 1 ) + , map = { 'dinx' : dinx[nbitu - 1 - i] + , 'write' : write[j + 1] + , 'read' : read[j + 1] + , 'rbus' : rbus[nbitu - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Bit[nbitu-1-i] = self.BitBis + + self.Out[nbitu-1-i] = Inst ( cell_out_mem + , "out%d" % ( nbitu - 1 - i ) + , sym1 + , map = { 'rbus' : rbus[nbitu - 1 - i] + , 'xcks' : xck + , 'dataout' : dataout[nbitu - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ## Placement des cellules du decodeur ## + if type == 2 or type == 3 : + nwen = Signal ( "nwen", 1 ) + nren = Signal ( "nren", 1 ) + + nadw0x = Signal ( "nadw0x", 1 ) + adw0x = Signal ( "adw0x", 1 ) + + adr0x = Signal ( "adr0x", 1 ) + nadr0x = Signal ( "nadr0x", 1 ) + + nandw = [] + for i in range ( nword >> 1 ) : + nandw += [Signal ( "nandw%d" % i, 1 )] + + + half = nword >> 1 + + # Premiere ligne decodeur ecriture + self.Adw0 = Inst ( "rf_dec_bufad0" + , "adw0" + , map = { 'i' : self._adw[0] + , 'nq' : nadw0x + , 'q' : adw0x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelW = {} + + for j in range ( half ) : + self.SelW[2*j] = Inst ( "rf_dec_nor3" + , "selw%d" % ( 2 * j ) + , map = { 'i0' : nandw[j] + , 'i1' : adw0x + , 'i2' : nwen + , 'nq' : self._selw[2 * j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + self.SelW[2*j+1] = Inst ( "rf_dec_nor3" + , "selw%d" % ( 2 * j + 1 ) + , map = { 'i0' : nandw[j] + , 'i1' : nadw0x + , 'i2' : nwen + , 'nq' : self._selw[2 * j + 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + self.Wen = Inst ( "rf_dec_nbuf" + , "wen" + , map = { 'i' : self._wen + , 'nq' : nwen + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Deuxieme ligne decodeur ecriture + if adrange == 5 : # adresse sur 5 bits + + nadw1x = Signal ( "nadw1x", 1 ) + adw1x = Signal ( "adw1x", 1 ) + nadw2x = Signal ( "nadw2x", 1 ) + adw2x = Signal ( "adw2x", 1 ) + adw3x = Signal ( "adw3x", 1 ) + nadw3x = Signal ( "nadw3x", 1 ) + adw4x = Signal ( "adw4x", 1 ) + nadw4x = Signal ( "nadw4x", 1 ) + + adr1x = Signal ( "adr1x", 1 ) + nadr1x = Signal ( "nadr1x", 1 ) + adr2x = Signal ( "adr2x", 1 ) + nadr2x = Signal ( "nadr2x", 1 ) + adr3x = Signal ( "adr3x", 1 ) + nadr3x = Signal ( "nadr3x", 1 ) + adr4x = Signal ( "adr4x", 1 ) + nadr4x = Signal ( "nadr4x", 1 ) + + self.Adw12 = Inst ( "rf_dec_bufad2" + , "adw12" + , map = { 'i0' : self._adw[1] + , 'i1' : self._adw[2] + , 'nq0' : nadw1x + , 'q0' : adw1x + , 'nq1' : nadw2x + , 'q1' : adw2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand4W = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandw[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadw1x + else : thisMap['i0'] = adw1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x + else : thisMap['i1'] = adw2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadw3x + else : thisMap['i2'] = adw3x + if ( j >> 3 ) % 2 == 0 : thisMap['i3'] = nadw4x + else : thisMap['i3'] = adw4x + + self.Nand4W[j] = Inst ( "rf_dec_nand4" + , "nand4w%d" % j + , map = thisMap + ) + + self.Adw34 = Inst ( "rf_dec_bufad2" + , "adw34" + , map = { 'i0' : self._adw[3] + , 'i1' : self._adw[4] + , 'nq0' : nadw3x + , 'q0' : adw3x + , 'nq1' : nadw4x + , 'q1' : adw4x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif adrange == 4 : # adresse sur 4 bits + + nadw1x = Signal ( "nadw1x", 1 ) + adw1x = Signal ( "adw1x", 1 ) + nadw2x = Signal ( "nadw2x", 1 ) + adw2x = Signal ( "adw2x", 1 ) + adw3x = Signal ( "adw3x", 1 ) + nadw3x = Signal ( "nadw3x", 1 ) + + adr1x = Signal ( "adr1x", 1 ) + nadr1x = Signal ( "nadr1x", 1 ) + adr2x = Signal ( "adr2x", 1 ) + nadr2x = Signal ( "nadr2x", 1 ) + adr3x = Signal ( "adr3x", 1 ) + nadr3x = Signal ( "nadr3x", 1 ) + + self.Adw12 = Inst ( "rf_dec_bufad2" + , "adw12" + , map = { 'i0' : self._adw[1] + , 'i1' : self._adw[2] + , 'nq0' : nadw1x + , 'q0' : adw1x + , 'nq1' : nadw2x + , 'q1' : adw2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand3W = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandw[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadw1x + else : thisMap['i0'] = adw1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x + else : thisMap['i1'] = adw2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadw3x + else : thisMap['i2'] = adw3x + + self.Nand3W[j] = Inst ( "rf_dec_nand3" + , "nand3w%d" % j + , map = thisMap + ) + + self.Adw3 = Inst ( "rf_dec_bufad1" + , "adw3" + , map = { 'i' : self._adw[3] + , 'nq' : nadw3x + , 'q' : adw3x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif adrange == 3 : # adresse sur 3 bits + + nadw1x = Signal ( "nadw1x", 1 ) + adw1x = Signal ( "adw1x", 1 ) + nadw2x = Signal ( "nadw2x", 1 ) + adw2x = Signal ( "adw2x", 1 ) + + adr1x = Signal ( "adr1x", 1 ) + nadr1x = Signal ( "nadr1x", 1 ) + adr2x = Signal ( "adr2x", 1 ) + nadr2x = Signal ( "nadr2x", 1 ) + + self. Adw1 = Inst ( "rf_dec_bufad1" + , "adw1" + , map = { 'i' : self._adw[1] + , 'nq' : nadw1x + , 'q' : adw1x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand2W = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandw[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadw1x + else : thisMap['i0'] = adw1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x + else : thisMap['i1'] = adw2x + + self.Nand2W[j] = Inst ( "rf_dec_nand2" + , "nand2w%d" % j + , map = thisMap + ) + + self.Adw2 = Inst ( "rf_dec_bufad1" + , "adw2" + , map = { 'i' : self._adw[2] + , 'nq' : nadw2x + , 'q' : adw2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Premiere ligne decodeur lecture + self.Adr0 = Inst ( "rf_dec_bufad0" + , "adr0" + , map = { 'i' : self._adr[0] + , 'nq' : nadr0x + , 'q' : adr0x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelR = {} + + for j in range ( half ) : + if j == 0 : + self.SelR[2*j] = Inst ( "rf_dec_nao3" + , "selr%d" % ( 2 * j ) + , map = { 'i0' : nandr[j] + , 'i1' : adr0x + , 'i2' : self._ren + , 'nq' : self._selr[2 * j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.SelR[2*j] = Inst ( 'rf_dec_nor3' + , 'selr%d' % ( 2 * j ) + , map = { 'i0' : nandr[j] + , 'i1' : adr0x + , 'i2' : nren + , 'nq' : self._selr[2 * j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelR[2*j+1] = Inst ( "rf_dec_nor3" + , 'selr%d' % ( 2 * j + 1 ) + , map = { 'i0' : nandr[j] + , 'i1' : nadr0x + , 'i2' : nren + , 'nq' : self._selr[2 * j + 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Ren = Inst ( 'rf_dec_nbuf' + , 'ren' + , map = { 'i' : self._ren + , 'nq' : nren + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Deuxieme ligne decodeur lecture + if adrange == 5 : # adresse sur 5 bits + self.Adr12 = Inst ( 'rf_dec_bufad2' + , 'adr12' + , map = { 'i0' : self._adr[1] + , 'i1' : self._adr[2] + , 'nq0' : nadr1x + , 'q0' : adr1x + , 'nq1' : nadr2x + , 'q1' : adr2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand4R = {} + + for j in range ( half ) : + thisMap = { 'nq': nandr[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadr1x + else : thisMap['i0'] = adr1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadr2x + else : thisMap['i1'] = adr2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadr3x + else : thisMap['i2'] = adr3x + if ( j >> 3 ) % 2 == 0 : thisMap['i3'] = nadr4x + else : thisMap['i3'] = adr4x + + self.Nand4R[j] = Inst ( 'rf_dec_nand4' + , 'nand4r%d' % j + , map = thisMap + ) + + self.Adr34 = Inst ( 'rf_dec_bufad2' + , 'adr34' + , map = { 'i0' : self._adr[3] + , 'i1' : self._adr[4] + , 'nq0' : nadr3x + , 'q0' : adr3x + , 'nq1' : nadr4x + , 'q1' : adr4x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 4 : # adresse sur 4 bits + self.Adr12 = Inst ( 'rf_dec_bufad2' + , 'adr12' + , map = { 'i0' : self._adr[1] + , 'i1' : self._adr[2] + , 'nq0' : nadr1x + , 'q0' : adr1x + , 'nq1' : nadr2x + , 'q1' : adr2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand3R = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandr[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadr1x + else : thisMap['i0'] = adr1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadr2x + else : thisMap['i1'] = adr2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadr3x + else : thisMap['i2'] = adr3x + + self.Nand3R[j] = Inst ( 'rf_dec_nand3' + , 'nand3r%d' % j + , map = thisMap + ) + + self.Adr3 = Inst ( 'rf_dec_bufad1' + , 'adr3' + , map = { 'i' : self._adr[3] + , 'nq' : nadr3x + , 'q' : adr3x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 3 : # adresse sur 3 bits + self.Adr1 = Inst ( 'rf_dec_bufad1' + , 'adr1' + , map = { 'i' : self._adr[1] + , 'nq' : nadr1x + , 'q' : adr1x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand2R = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandr[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadr1x + else : thisMap['i0'] = adr1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadr2x + else : thisMap['i1'] = adr2x + + self.Nand2R[j] = Inst ( 'rf_dec_nand2' + , 'nand2r%d' % j + , map = thisMap + ) + + self.Adr2 = Inst ( 'rf_dec_bufad1' + , 'adr2' + , map = { 'i' : self._adr[2] + , 'nq' : nadr2x + , 'q' : adr2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + +# end if type == 2 or type == 3 + + ## Placement des cellules du controleur FIFO ## + if type == 4 : + ckm = Signal ( "ckm", 1 ) + cks = Signal ( "cks", 1 ) + nreset = Signal ( "nreset", 1 ) + nwval = Signal ( "nwval", 1 ) + pwnop = Signal ( "pwnop", 1 ) + pwinc = Signal ( "pwinc", 1 ) + prnop = Signal ( "prnop", 1 ) + princ = Signal ( "princ", 1 ) + xreset = Signal ( "xreset", 1 ) + xckm = Signal ( "xckm", 1 ) + xcks = Signal ( "xcks", 1 ) + nr = Signal ( "nr", 1 ) + nw = Signal ( "nw", 1 ) + full = Signal ( "full", 1 ) + fullnext = Signal ( "fullnext", 1 ) + empty = Signal ( "empty", 1 ) + emptynext = Signal ( "emptynext", 1 ) + nrval = Signal ( "nrval", 1 ) + + orfull = [] + orempty = [] + for i in range ( nword >> 1 ) : + orfull += [Signal ( "orfull%d" % i, 1 )] + orempty += [Signal ( "orempty%d" % i, 1 )] + + + half = nword >> 1 + + # Premiere ligne + self.Inspwnop = Inst ( 'rf_fifo_nop' + , 'inspwnop' + , map = { 'ckm' : ckm + , 'nreset' : nreset + , 'rw' : self._w + , 'rwok' : self._wok + , 'nval' : nwval + , 'nop' : pwnop + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Pw = {} + + self.Pw[0] = Inst ( 'rf_fifo_ptset' + , 'pw0' + , map = { 'nop' : pwnop + , 'inc' : pwinc + , 'cks' : xcks + , 'nreset' : nreset + , 'ptm1' : self._selw[nword - 1] + , 'pt' : self._selw[0] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + for j in range ( 1, half, 1 ) : + self.Pw[j] = Inst ( 'rf_fifo_ptreset' + , 'pw%d' % j + , map = { 'nop' : pwnop + , 'inc' : pwinc + , 'cks' : xcks + , 'reset' : xreset + , 'ptm1' : self._selw[j - 1] + , 'pt' : self._selw[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.FifoBuf = Inst ( 'rf_fifo_buf' + , 'fifo_buf' + , map = { 'cks' : cks + , 'ckm' : ckm + , 'r' : self._r + , 'w' : self._w + , 'reset' : self._reset + , 'xcks' : xcks + , 'xckm' : xckm + , 'nr' : nr + , 'nw' : nw + , 'xreset' : xreset + , 'nreset' : nreset + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Deuxieme ligne + self.Inspwinc = Inst ( 'rf_fifo_inc' + , 'inspwinc' + , map = { 'ckm' : ckm + , 'nreset' : nreset + , 'nval' : nwval + , 'inc' : pwinc + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + for j in range ( half ) : + self.Pw[nword-1-j] = Inst ( 'rf_fifo_ptreset' + , 'pw%d' % ( nword - 1 - j ) + , map = { 'nop' : pwnop + , 'inc' : pwinc + , 'cks' : xcks + , 'reset' : xreset + , 'ptm1' : self._selw[nword - 2 - j] + , 'pt' : self._selw[nword - 1 - j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Troisieme ligne + self.InsWok = Inst ( 'rf_fifo_ok' + , 'inswok' + , map = { 'rw' : self._w + , 'ripple' : orfull[0] + , 'nrw' : nr + , 'prev' : full + , 'nextval' : fullnext + , 'ok' : self._wok + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.InsOrFull = {} + + for j in range ( half - 1 ) : + self.InsOrFull[j] = Inst ( 'rf_fifo_orand5' + , 'insorfull%d' % j + , map = { 'a0' : self._selw[j] + , 'b0' : self._selr[j + 1] + , 'a1' : self._selw[nword - 1 - j] + , 'b1' : self._selr[( nword - j ) % nword] + , 'ripplein' : orfull[j + 1] + , 'rippleout' : orfull[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.InsOrFull[half-1] = Inst ( 'rf_fifo_orand4' + , 'insorfull%d' % ( half - 1 ) + , map = { 'a0' : self._selw[half - 1] + , 'b0' : self._selr[half] + , 'a1' : self._selw[half] + , 'b1' : self._selr[half + 1] + , 'rippleout' : orfull[half - 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.InsEmpty = Inst ( 'rf_fifo_empty' + , 'insempty' + , map = { 'ckm' : xckm + , 'nreset' : nreset + , 'emptynext' : emptynext + , 'cks' : xcks + , 'empty' : empty + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Quatrieme ligne + self.InsFull = Inst ( 'rf_fifo_full' + , 'insfull' + , map = { 'ckm' : xckm + , 'reset' : xreset + , 'fullnext' : fullnext + , 'cks' : xcks + , 'full' : full + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.InsOrEmpty = {} + + self.InsOrEmpty[0] = Inst ( 'rf_fifo_orand4' + , 'insorempty0' + , map = { 'a0' : self._selr[0] + , 'b0' : self._selw[1] + , 'a1' : self._selr[nword - 1] + , 'b1' : self._selw[0] + , 'rippleout' : orempty[0] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + for j in range ( 1, half ) : + self.InsOrEmpty[j] = Inst ( 'rf_fifo_orand5' + , 'insorempty%d' % j + , map = { 'a0' : self._selr[j] + , 'b0' : self._selw[j + 1] + , 'a1' : self._selr[nword - 1 - j] + , 'b1' : self._selw[nword - j] + , 'ripplein' : orempty[j - 1] + , 'rippleout' : orempty[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.InsRok = Inst ( 'rf_fifo_ok' + , 'insrok' + , map = { 'rw' : self._r + , 'ripple' : orempty[half - 1] + , 'nrw' : nw + , 'prev' : empty + , 'nextval' : emptynext + , 'ok' : self._rok + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Cinquieme ligne + self.InsClock = Inst ( 'rf_fifo_clock' + , 'insclock' + , map = { 'ck' : self._ck + , 'wok' : self._wok + , 'cks' : cks + , 'ckm' : ckm + , 'ckok' : self._ckok + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Pr = {} + + self.Pr[0] = Inst ( 'rf_fifo_ptset' + , 'pr0' + , map = { 'nop' : prnop + , 'inc' : princ + , 'cks' : xcks + , 'nreset' : nreset + , 'ptm1' : self._selr[nword - 1] + , 'pt' : self._selr[0] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + for j in range ( 1, half ) : + self.Pr[j] = Inst ( 'rf_fifo_ptreset' + , 'pr%d' % j + , map = { 'nop' : prnop + , 'inc' : princ + , 'cks' : xcks + , 'reset' : xreset + , 'ptm1' : self._selr[j - 1] + , 'pt' : self._selr[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.InsPrNop = Inst ( 'rf_fifo_nop' + , 'insprnop' + , map = { 'ckm' : ckm + , 'nreset' : nreset + , 'rw' : self._r + , 'rwok' : self._rok + , 'nval' : nrval + , 'nop' : prnop + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Sixieme ligne + self.Pr[nword-1] = Inst ( 'rf_fifo_ptreset' + , 'pr%d' % ( nword - 1 ) + , map = { 'nop' : prnop + , 'inc' : princ + , 'cks' : xcks + , 'reset' : xreset + , 'ptm1' : self._selr[nword - 2] + , 'pt' : self._selr[nword - 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + for j in range ( 1, half ) : + self.Pr[nword-1-j] = Inst ( 'rf_fifo_ptreset' + , 'pr%d' % ( nword - 1 - j ) + , map = { 'nop' : prnop + , 'inc' : princ + , 'cks' : xcks + , 'reset' : xreset + , 'ptm1' : self._selr[nword - 2 - j] + , 'pt' : self._selr[nword - 1 - j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.InsPrinc= Inst ( 'rf_fifo_inc' + , 'insprinc' + , map = { 'ckm' : ckm + , 'nreset' : nreset + , 'nval' : nrval + , 'inc' : princ + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) +# end if type == 4 + + + ## Layout ## + ############ + def Layout ( self, nbit, nword, type ) : + + hbuf = 2 # hauteur des buffers (2 ou 4 slices) : non utilise + + HCELL = 50 + + ## Placement des lignes de bit en dessous des buffers ## + bottom = 0 + + sym1 = NOSYM + sym2 = SYM_X + + for i in range ( nbit ) : + if i % 2 : # lignes paires + sym1 = NOSYM + sym2 = SYM_X + else : # lignes impaires + sym1 = SYM_Y + sym2 = SYMXY + + Place ( self.In[nbit - 1 - i], sym1, XY ( 0, bottom + ( nbit - 1 - i ) * HCELL ) ) + + for j in range ( 0, nword, 2 ) : + PlaceRight ( self.Bit[nbit - 1 - i][j], sym1 ) + PlaceRight ( self.Bit[nbit - 1 - i][j + 1], sym2 ) + + PlaceRight ( self.Out[nbit - 1 - i] , sym1 ) + + ## Placement de la ligne contenant les buffers ## + bottom = nbit * HCELL + + Place ( self.InBuf, NOSYM, XY ( 0, bottom ) ) + + for j in range ( 0, nword, 2 ) : + PlaceRight ( self.Buf[j], NOSYM ) + PlaceRight ( self.Buf[j + 1], SYM_X ) + + PlaceRight ( self.OutBuf, NOSYM ) + + ## Placement des lignes de bit au dessus des buffers ## + bottom = ( nbit + hbuf ) * HCELL + + for i in range ( nbitu ) : + if i % 2 : # lignes impaires + sym1 = SYM_Y + sym2 = SYMXY + else : # lignes paires + sym1 = NOSYM + sym2 = SYM_X + + Place ( self.In[nbitu - 1 - i], sym1, XY ( 0, bottom + i * HCELL ) ) + + for j in range ( 0, nword, 2 ) : + PlaceRight ( self.Bit[nbitu - 1 - i][j], sym1 ) + PlaceRight ( self.Bit[nbitu - 1 - i][j + 1], sym2 ) + + PlaceRight ( self.Out[nbitu - 1 - i], sym1 ) + + ## Placement des cellules du decodeur ## + if type == 2 or type == 3 : + half = nword >> 1 + + # Premiere ligne decodeur ecriture + bottom = ( nbit + nbitu + hbuf + 2 ) * HCELL + + Place ( self.Adw0, NOSYM, XY ( 0, bottom ) ) + + for j in range ( half ) : + PlaceRight ( self.SelW[2 * j], SYM_X ) + PlaceRight ( self.SelW[2 * j + 1], NOSYM ) + + PlaceRight ( self.Wen, NOSYM ) + + # Deuxieme ligne decodeur ecriture + bottom = ( nbit + nbitu + hbuf + 3 ) * HCELL + + if adrange == 5 : # adresse sur 5 bits + Place ( self.Adw12, SYM_Y, XY ( 0, bottom ) ) + + for j in range ( half ) : PlaceRight ( self.Nand4W[j], SYM_Y ) + + PlaceRight ( self.Adw34, SYMXY ) + + if adrange == 4 : # adresse sur 4 bits + Place ( self.Adw12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand3W[j], SYM_Y ) + PlaceRight ( self.Adw3, SYMXY ) + + if adrange == 3 : # adresse sur 3 bits + Place ( self.Adw1, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand2W[j], SYM_Y ) + PlaceRight ( self.Adw2, SYMXY ) + + # Premiere ligne decodeur lecture + bottom = ( nbit + nbitu + hbuf ) * HCELL + + Place ( self.Adr0, NOSYM, XY ( 0, bottom ) ) + + for j in range ( half ) : + if j == 0 : PlaceRight ( self.SelR[2 * j], NOSYM ) + else : PlaceRight ( self.SelR[2 * j], NOSYM ) + PlaceRight ( self.SelR[2 * j + 1], SYM_X ) + + PlaceRight ( self.Ren, NOSYM ) + + # Deuxieme ligne decodeur lecture + bottom = ( nbit + nbitu + hbuf + 1 ) * HCELL + + if adrange == 5 : # adresse sur 5 bits + Place ( self.Adr12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand4R[j], SYM_Y ) + PlaceRight ( self.Adr34, SYMXY ) + + if adrange == 4 : # adresse sur 4 bits + Place ( self.Adr12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand3R[j], SYM_Y ) + PlaceRight ( self.Adr3, SYMXY ) + + if adrange == 3 : # adresse sur 3 bits + Place ( self.Adr1, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand2R[j], SYM_Y ) + PlaceRight ( self.Adr2, SYMXY ) + + ## Placement des cellules du controleur FIFO ## + if type == 4 : + half = nword >> 1 + + # Premiere ligne + bottom = ( nbit + nbitu + hbuf ) * HCELL + Place ( self.Inspwnop, SYM_X, XY ( 0, bottom ) ) + PlaceRight ( self.Pw[0], NOSYM ) + + for j in range ( 1, half, 1 ) : PlaceRight ( self.Pw[j], NOSYM ) + + PlaceRight ( self.FifoBuf, SYM_X ) + + # Deuxieme ligne + bottom = ( nbit + nbitu + hbuf + 1 ) * HCELL + + Place ( self.Inspwinc, SYMXY, XY ( 0, bottom ) ) + + for j in range ( half ) : PlaceRight ( self.Pw[nword - 1 - j], SYMXY ) + + # Troisieme ligne + bottom = ( nbit + nbitu + hbuf + 2 ) * HCELL + + Place ( self.InsWok, NOSYM, XY ( 0, bottom ) ) + + for j in range ( half - 1 ) : PlaceRight ( self.InsOrFull[j], NOSYM ) + + PlaceRight ( self.InsOrFull[half - 1], NOSYM ) + PlaceRight ( self.InsEmpty, SYM_X ) + + # Quatrieme ligne + bottom = ( nbit + nbitu + hbuf + 3 ) * HCELL + + Place ( self.InsFull, SYM_Y, XY ( 0, bottom ) ) + PlaceRight ( self.InsOrEmpty[0], SYMXY ) + + for j in range ( 1, half ) : PlaceRight ( self.InsOrEmpty[j], SYMXY ) + + PlaceRight ( self.InsRok, SYMXY ) + + # Cinquieme ligne + bottom = ( nbit + nbitu + hbuf + 4 ) * HCELL + + Place ( self.InsClock, NOSYM, XY ( 0, bottom ) ) + PlaceRight ( self.Pr[0], NOSYM ) + + for j in range ( 1, half ) : PlaceRight ( self.Pr[j], NOSYM ) + + PlaceRight ( self.InsPrNop, NOSYM ) + + # Sixieme ligne + bottom = ( nbit + nbitu + hbuf + 5 ) * HCELL + + Place ( self.Pr[nword - 1] , SYMXY, XY ( 50, bottom ) ) + + for j in range ( 1, half ) : PlaceRight ( self.Pr[nword - 1 - j], SYM_Y ) + + PlaceRight ( self.InsPrinc, SYM_Y ) + + + ## VBE ## + ######### + def Vbe ( self ) : + print "rf1 behavior not implemented" + + + +#################### +##### DpgenRf1 ##### +#################### +class DpgenRf1 ( top_rf1 ) : + + def Interface ( self ) : + top_rf1.Interface ( self, self._param['nbit'], self._param['nword'], 0 ) + + def Netlist ( self ) : + top_rf1.Netlist ( self, self._param['nbit'], self._param['nword'], 0 ) + + def Layout ( self ) : + top_rf1.Layout ( self, self._param['nbit'], self._param['nword'], 0 ) + + +###################### +##### DpgenRf1r0 ##### +###################### +class DpgenRf1r0 ( top_rf1 ) : + + def Interface ( self ) : + top_rf1.Interface ( self, self._param['nbit'], self._param['nword'], 1 ) + + def Netlist ( self ) : + top_rf1.Netlist ( self, self._param['nbit'], self._param['nword'], 1 ) + + def Layout ( self ) : + top_rf1.Layout ( self, self._param['nbit'], self._param['nword'], 1 ) + + +##################### +##### DpgenRf1d ##### +##################### +class DpgenRf1d ( top_rf1 ) : + + def Interface ( self ) : + top_rf1.Interface ( self, self._param['nbit'], self._param['nword'], 2 ) + + def Netlist ( self ) : + top_rf1.Netlist ( self, self._param['nbit'], self._param['nword'], 2 ) + + def Layout ( self ) : + top_rf1.Layout ( self, self._param['nbit'], self._param['nword'], 2 ) + + +####################### +##### DpgenRf1dr0 ##### +####################### +class DpgenRf1dr0 ( top_rf1 ) : + + def Interface ( self ) : + top_rf1.Interface ( self, self._param['nbit'], self._param['nword'], 3 ) + + def Netlist ( self ) : + top_rf1.Netlist ( self, self._param['nbit'], self._param['nword'], 3 ) + + def Layout ( self ) : + top_rf1.Layout ( self, self._param['nbit'], self._param['nword'], 3 ) + + +##################### +##### DpgenFifo ##### +##################### +class DpgenFifo ( top_rf1 ) : + + def Interface ( self ) : + top_rf1.Interface ( self, self._param['nbit'], self._param['nword'], 4 ) + + def Netlist ( self ) : + top_rf1.Netlist ( self, self._param['nbit'], self._param['nword'], 4 ) + + def Layout ( self ) : + top_rf1.Layout ( self, self._param['nbit'], self._param['nword'], 4 ) diff --git a/stratus1/src/dpgen/dpgen_RF2.py b/stratus1/src/dpgen/dpgen_RF2.py new file mode 100644 index 00000000..10d77216 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_RF2.py @@ -0,0 +1,1145 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_RF2.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +# Banc de registre triple acces : deux lectures, une ecriture +# Le programme genere une net-list et un placement optimise. +# +# La largeur est egale a (nmot * 35) + 150 +# La hauteur est egale a (nbit + 8) * 50 +# +# Pour la partie "donnees", on utilise les cellules suivantes : +# colonne d'entree +# - rf2_inmux_mem +# - rf2_inmux_buf +# colonne centrale +# - rf2_mid_mem +# - rf2_mid_mem_r0 +# - rf2_mid_buf +# colonne de sortie +# - rf2_out_mem +# - rf2_out_buf +# +# Pour le decodeur, on utilise les cellules suivantes : +# - rf2_dec_bufad0 +# - rf2_dec_bufad1_l +# - rf2_dec_bufad2_l +# - rf2_dec_bufad1_r +# - rf2_dec_bufad2_r +# - rf2_dec_nbuf +# - rf2_dec_nor3 +# - rf2_dec_nao3 +# - rf2_dec_nand2 +# - rf2_dec_nand3 +# - rf2_dec_nand4 + + +#---------------------------------------------------------------- +# DEBUT PROGRAMME PRINCIPAL +#---------------------------------------------------------------- +# aFunction : le type : +# DPGEN_RF2 (sans decodeur) +# DPGEN_RF2R0 (sans decodeur, avec R0 colle a 0) +# DPGEN_RF2D (avec decodeur) +# DPGEN_RF2DR0 (avec decodeur, avec R0 colle a 0) +# +# aAL : liste des parametres : +# Model_name : nom de modele. +# flags : indexation des connecteurs. +# nbit : nombre de bits (largeur du bus). +# nmot : nombre de mots. +# - le nombre de mots doit etre pair, 6 =< nmot =< 32 +# - le nombre de bits doit etre pair, 2 =< nbit =< 64 +#---------------------------------------------------------------- + + + +################################# +##### Classe mere : top_rf2 ##### +################################# +class top_rf2 ( Model ) : + + ## Interface ## + ############### + def Interface ( self, nbit, nword, type ) : + global adrange + + if nword % 2 == 1 or nword > 32 or nword < 4 : + print "Error in DpgenRf2 : the word number must be even, larger than 4 and no larger than 32\n" + sys.exit ( 1 ) + + if nword == 4 and ( type == 2 or type == 3 ) : + print "Error in DpgenRf2 : the word number must be larger than 4\n" + sys.exit ( 1 ) + + if nbit % 2 == 1 or nbit > 64 or nbit < 2 : + print "Error in DpgenRf2 : the bit number must be even and no larger than 64\n" + sys.exit ( 1 ) + + adrange = 2 + if nword > 4 : adrange = 3 + if nword > 8 : adrange = 4 + if nword > 16 : adrange = 5 + + if type < 2 : # c'est un banc de registres sans decodeur + self._ck = SignalIn ( "ck", 1 ) + self._sel = SignalIn ( "sel", 1 ) + + self._sela = SignalIn ( "sela", nword ) + self._selb = SignalIn ( "selb", nword ) + self._selw = SignalIn ( "selw", nword ) + self._datain0 = SignalIn ( "datain0", nbit ) + self._datain1 = SignalIn ( "datain1", nbit ) + + self._dataouta = SignalOut ( "dataouta", nbit ) + self._dataoutb = SignalOut ( "dataoutb", nbit ) + + else : # c'est un banc de registres avec decodeur + self._ck = SignalIn ( "ck", 1 ) + self._sel = SignalIn ( "sel", 1 ) + self._wen = SignalIn ( "wen", 1 ) + self._rena = SignalIn ( "rena", 1 ) + self._renb = SignalIn ( "renb", 1 ) + + self._adra = SignalIn ( "adra", adrange ) + self._adrb = SignalIn ( "adrb", adrange ) + self._adw = SignalIn ( "adw" , adrange ) + + self._datain0 = SignalIn ( "datain0", nbit ) + self._datain1 = SignalIn ( "datain1", nbit ) + + self._dataouta = SignalOut ( "dataouta", nbit ) + self._dataoutb = SignalOut ( "dataoutb", nbit ) + + self._selw = Signal ( "selw", nword ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + + ## Netlist ## + ############# + def Netlist ( self, nbit, nword, type ) : + global adrange + + # Signaux + sel0 = Signal ( "sel0", 1 ) + sel1 = Signal ( "sel1", 1 ) + xcks = Signal ( "xcks", 1 ) + nck = Signal ( "nck", 1 ) + nwen = Signal ( "nwen", 1 ) + nrena = Signal ( "nrena", 1 ) + nrenb = Signal ( "nrenb", 1 ) + + adw0x = Signal ( "adw0x", 1 ) + nadw0x = Signal ( "nadw0x", 1 ) + adw1x = Signal ( "adw1x", 1 ) + nadw1x = Signal ( "nadw1x", 1 ) + adw2x = Signal ( "adw2x", 1 ) + nadw2x = Signal ( "nadw2x", 1 ) + adw3x = Signal ( "adw3x", 1 ) + nadw3x = Signal ( "nadw3x", 1 ) + adw4x = Signal ( "adw4x", 1 ) + nadw4x = Signal ( "nadw4x", 1 ) + + adra0x = Signal ( "adra0x", 1 ) + nadra0x = Signal ( "nadra0x", 1 ) + adra1x = Signal ( "adra1x", 1 ) + nadra1x = Signal ( "nadra1x", 1 ) + adra2x = Signal ( "adra2x", 1 ) + nadra2x = Signal ( "nadra2x", 1 ) + adra3x = Signal ( "adra3x", 1 ) + nadra3x = Signal ( "nadra3x", 1 ) + adra4x = Signal ( "adra4x", 1 ) + nadra4x = Signal ( "nadra4x", 1 ) + + adrb0x = Signal ( "adrb0x", 1 ) + nadrb0x = Signal ( "nadrb0x", 1 ) + adrb1x = Signal ( "adrb1x", 1 ) + nadrb1x = Signal ( "nadrb1x", 1 ) + adrb2x = Signal ( "adrb2x", 1 ) + nadrb2x = Signal ( "nadrb2x", 1 ) + adrb3x = Signal ( "adrb3x", 1 ) + nadrb3x = Signal ( "nadrb3x", 1 ) + adrb4x = Signal ( "adrb4x", 1 ) + nadrb4x = Signal ( "nadrb4x", 1 ) + + dinx = Signal ( "dinx", nbit ) + busa = Signal ( "busa", nbit ) + busb = Signal ( "busb", nbit ) + + if type >= 2 : + self._sela = Signal ( "sela", nword ) + self._selb = Signal ( "selb", nword ) + + write = [] + reada = [] + readb = [] + for i in range ( nword ) : + write += [Signal ( "write%d" % i, 1 )] + reada += [Signal ( "reada%d" % i, 1 )] + readb += [Signal ( "readb%d" % i, 1 )] + + nandw = [] + nandra = [] + nandrb = [] + for i in range ( nword >> 1 ) : + nandw += [Signal ( "nandw%d" % i, 1 )] + nandra += [Signal ( "nandra%d" % i, 1 )] + nandrb += [Signal ( "nandrb%d" % i, 1 )] + + + # placement des lignes de bit en dessous des buffers + self.In = {} + self.Bit = {} + self.Out = {} + + for i in range ( nbit ) : + self.In[nbit-1-i] = Inst ( 'rf2_inmux_mem' + , 'in%d' % ( nbit - 1 - i ) + , map = { 'datain0' : self._datain0[nbit - 1 - i] + , 'datain1' : self._datain1[nbit - 1 - i] + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'dinx' : dinx[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.BitBis = {} + + for j in range ( 0, nword, 2 ) : + if j == 0 and ( type == 1 or type == 3 ) : + self.BitBis[j] = Inst ( 'rf2_mid_mem_r0' + , 'bit%d_%d' % ( nbit - 1 - i , j ) + , map = { 'dinx' : dinx[nbit - 1 - i] + , 'write' : write[j] + , 'reada' : reada[j] + , 'readb' : readb[j] + , 'busa' : busa[nbit - 1 - i] + , 'busb' : busb[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.BitBis[j] = Inst ( 'rf2_mid_mem' + , 'bit%d_%d' % ( nbit - 1 - i, j ) + , map = { 'dinx' : dinx[nbit - 1 - i] + , 'write' : write[j] + , 'reada' : reada[j] + , 'readb' : readb[j] + , 'busa' : busa[nbit - 1 - i] + , 'busb' : busb[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.BitBis[j+1] = Inst ( 'rf2_mid_mem' + , 'bit%d_%d' % ( nbit - 1 - i, j + 1 ) + , map = { 'dinx' : dinx[nbit - 1 - i] + , 'write' : write[j + 1] + , 'reada' : reada[j + 1] + , 'readb' : readb[j + 1] + , 'busa' : busa[nbit - 1 - i] + , 'busb' : busb[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Bit[nbit-1-i] = self.BitBis + + self.Out[nbit-1-i] = Inst ( 'rf2_out_mem' + , 'out%d' % ( nbit - 1 - i ) + , map = { 'busa' : busa[nbit - 1 - i] + , 'busb' : busb[nbit - 1 - i] + , 'xcks' : xcks + , 'dataouta' : self._dataouta[nbit - 1 - i] + , 'dataoutb' : self._dataoutb[nbit - 1 - i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # placement de la ligne contenant les buffers + self.InBuf = Inst ( 'rf2_inmux_buf' + , 'inbuf' + , map = { 'sel' : self._sel + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Buf = {} + + for j in range ( 0, nword, 2 ) : + self.Buf[j] = Inst ( 'rf2_mid_buf' + , 'buf%d' % j + , map = { 'selra' : self._sela[j] + , 'selrb' : self._selb[j] + , 'selw' : self._selw[j] + , 'nck' : nck + , 'reada' : reada[j] + , 'readb' : readb[j] + , 'write' : write[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Buf[j+1] = Inst ( 'rf2_mid_buf' + , 'buf%d' % ( j + 1 ) + , map = { 'selra' : self._sela[j + 1] + , 'selrb' : self._selb[j + 1] + , 'selw' : self._selw[j + 1] + , 'nck' : nck + , 'reada' : reada[j + 1] + , 'readb' : readb[j + 1] + , 'write' : write[j + 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.OutBuf = Inst ( 'rf2_out_buf' + , 'outbuf' + , map = { 'ck' : self._ck + , 'nck' : nck + , 'xcks' : xcks + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # placement des cellules du decodeur ecriture + if type == 2 or type == 3 : + half = nword >> 1 + + # Premiere ligne decodeur ecriture + self.Adw0 = Inst ( 'rf2_dec_bufad0' + , 'adw0' + , map = { 'i' : self._adw[0] + , 'nq' : nadw0x + , 'q' : adw0x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelW = {} + + for j in range ( half ) : + self.SelW[2*j] = Inst ( 'rf2_dec_nor3' + , 'selw%d' % ( 2 * j ) + , map = { 'i0' : nandw[j] + , 'i1' : adw0x + , 'i2' : nwen + , 'nq' : self._selw[2 * j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelW[2*j+1] = Inst ( 'rf2_dec_nor3' + , 'selw%d' % ( 2 * j + 1 ) + , map = { 'i0' : nandw[j] + , 'i1' : nadw0x + , 'i2' : nwen + , 'nq' : self._selw[2 * j + 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Wen = Inst ( 'rf2_dec_nbuf' + , 'wen' + , map = { 'i' : self._wen + , 'nq' : nwen + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Deuxieme ligne decodeur ecriture + if adrange == 5 : # adresse sur 5 bits + self.Adw12 = Inst ( 'rf2_dec_bufad2_l' + , 'adw12' + , map = { 'i0' : self._adw[1] + , 'i1' : self._adw[2] + , 'nq0' : nadw1x + , 'q0' : adw1x + , 'nq1' : nadw2x + , 'q1' : adw2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand4W = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandw[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadw1x + else : thisMap['i0'] = adw1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x + else : thisMap['i1'] = adw2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadw3x + else : thisMap['i2'] = adw3x + if ( j >> 3 ) % 2 == 0 : thisMap['i3'] = nadw4x + else : thisMap['i3'] = adw4x + + self.Nand4W[j] = Inst ( 'rf2_dec_nand4' + , 'nand4w%d' % j + , map = thisMap + ) + + self.Adw34 = Inst ( 'rf2_dec_bufad2_l' + , 'adw34' + , map = { 'i0' : self._adw[3] + , 'i1' : self._adw[4] + , 'nq0' : nadw3x + , 'q0' : adw3x + , 'nq1' : nadw4x + , 'q1' : adw4x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 4 : # adresse sur 4 bits + self.Adw12 = Inst ( 'rf2_dec_bufad2_l' + , 'adw12' + , map = { 'i0' : self._adw[1] + , 'i1' : self._adw[2] + , 'nq0' : nadw1x + , 'q0' : adw1x + , 'nq1' : nadw2x + , 'q1' : adw2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand3W = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandw[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadw1x + else : thisMap['i0'] = adw1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x + else : thisMap['i1'] = adw2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadw3x + else : thisMap['i2'] = adw3x + + self.Nand3W[j] = Inst ( 'rf2_dec_nand3' + , 'nand3w%d' % j + , map = thisMap + ) + + self.Adw3 = Inst ( 'rf2_dec_bufad1_r' + , 'adw3' + , map = { 'i' : self._adw[3] + , 'nq' : nadw3x + , 'q' : adw3x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 3 : # adresse sur 3 bits + self.Adw1 = Inst ( 'rf2_dec_bufad1_l' + , 'adw1' + , map = { 'i' : self._adw[1] + , 'nq' : nadw1x + , 'q' : adw1x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand2W = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandw[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadw1x + else : thisMap['i0'] = adw1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadw2x + else : thisMap['i1'] = adw2x + + self.Nand2W[j] = Inst ( 'rf2_dec_nand2' + , 'nand2w%d' % j + , map = thisMap + ) + + self.Adw2 = Inst ( 'rf2_dec_bufad1_r' + , 'adw2' + , map = { 'i' : self._adw[2] + , 'nq' : nadw2x + , 'q' : adw2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # placement des cellules du decodeur lecture A + if type == 2 or type == 3 : + half = nword >> 1 + + # Premiere ligne decodeur lecture A + self.Adra0 = Inst ( 'rf2_dec_bufad0' + , 'adra0' + , map = { 'i' : self._adra[0] + , 'nq' : nadra0x + , 'q' : adra0x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelRa = {} + + for j in range ( half ) : + if j == 0 : + self.SelRa[2*j] = Inst ( 'rf2_dec_nao3' + , 'sela%d' % ( 2 * j ) + , map = { 'i0' : nandra[j] + , 'i1' : adra0x + , 'i2' : self._rena + , 'nq' : self._sela[2 * j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.SelRa[2*j] = Inst ( 'rf2_dec_nor3' + , 'sela%d' % ( 2 * j ) + , map = { 'i0' : nandra[j] + , 'i1' : adra0x + , 'i2' : nrena + , 'nq' : self._sela[2 * j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelRa[2*j+1] = Inst ( 'rf2_dec_nor3' + , 'sela%d' % ( 2 * j + 1 ) + , map = { 'i0' : nandra[j] + , 'i1' : nadra0x + , 'i2' : nrena + , 'nq' : self._sela[2 * j + 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.RenA = Inst ( 'rf2_dec_nbuf' + , 'rena' + , map = { 'i' : self._rena + , 'nq' : nrena + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Deuxieme ligne decodeur lecture A + if adrange == 5 : # adresse sur 5 bits + self.Adra12 = Inst ( 'rf2_dec_bufad2_l' + , 'adra12' + , map = { 'i0' : self._adra[1] + , 'i1' : self._adra[2] + , 'nq0' : nadra1x + , 'q0' : adra1x + , 'nq1' : nadra2x + , 'q1' : adra2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand4Ra = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandra[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadra1x + else : thisMap['i0'] = adra1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadra2x + else : thisMap['i1'] = adra2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadra3x + else : thisMap['i2'] = adra3x + if ( j >> 3 ) % 2 == 0 : thisMap['i3'] = nadra4x + else : thisMap['i3'] = adra4x + + self.Nand4Ra[j] = Inst ( 'rf2_dec_nand4' + , 'nand4ra%d' % j + , map = thisMap + ) + + self.Adra34 = Inst ( 'rf2_dec_bufad2_r' + , 'adra34' + , map = { 'i0' : self._adra[3] + , 'i1' : self._adra[4] + , 'nq0' : nadra3x + , 'q0' : adra3x + , 'nq1' : nadra4x + , 'q1' : adra4x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 4 : # adresse sur 4 bits + self.Adra12 = Inst ( 'rf2_dec_bufad2_l' + , 'adra12' + , map = { 'i0' : self._adra[1] + , 'i1' : self._adra[2] + , 'nq0' : nadra1x + , 'q0' : adra1x + , 'nq1' : nadra2x + , 'q1' : adra2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand3Ra = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandra[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadra1x + else : thisMap['i0'] = adra1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadra2x + else : thisMap['i1'] = adra2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadra3x + else : thisMap['i2'] = adra3x + + self.Nand3Ra[j] = Inst ( 'rf2_dec_nand3' + , 'nand3ra%d' % j + , map = thisMap + ) + + self.Adra3 = Inst ( 'rf2_dec_bufad1_r' + , 'adra3' + , map = { 'i' : self._adra[3] + , 'nq' : nadra3x + , 'q' : adra3x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 3 : # adresse sur 3 bits + self.Adra1 = Inst ( 'rf2_dec_bufad1_l' + , 'adra1' + , map = { 'i' : self._adra[1] + , 'nq' : nadra1x + , 'q' : adra1x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand2Ra = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandra[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadra1x + else : thisMap['i0'] = adra1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadra2x + else : thisMap['i1'] = adra2x + + self.Nand2Ra[j] = Inst ( 'rf2_dec_nand2' + , 'nand2ra%d' % j + , map = thisMap + ) + + self.Adra2 = Inst ( 'rf2_dec_bufad1_r' + , 'adra2' + , map = { 'i' : self._adra[2] + , 'nq' : nadra2x + , 'q' : adra2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # placement des cellules du decodeur lecture B + if type == 2 or type == 3 : + half = nword >> 1 + + # Premiere ligne decodeur lecture A + self.Adrb0 = Inst ( 'rf2_dec_bufad0' + , 'adrb0' + , map = { 'i' : self._adrb[0] + , 'nq' : nadrb0x + , 'q' : adrb0x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelRb = {} + + for j in range ( half ) : + if j == 0 : + self.SelRb[2*j] = Inst ( 'rf2_dec_nao3' + , 'selb%d' % ( 2 * j ) + , map = { 'i0' : nandrb[j] + , 'i1' : adrb0x + , 'i2' : self._renb + , 'nq' : self._selb[2 * j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.SelRb[2*j] = Inst ( 'rf2_dec_nor3' + , 'selb%d' % ( 2 * j ) + , map = { 'i0' : nandrb[j] + , 'i1' : adrb0x + , 'i2' : nrenb + , 'nq' : self._selb[2 * j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.SelRb[2*j+1] = Inst ( 'rf2_dec_nor3' + , 'selb%d' % ( 2 * j + 1 ) + , map = { 'i0' : nandrb[j] + , 'i1' : nadrb0x + , 'i2' : nrenb + , 'nq' : self._selb[2 * j + 1] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.RenB = Inst ( 'rf2_dec_nbuf' + , 'renb' + , map = { 'i' : self._renb + , 'nq' : nrenb + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Deuxieme ligne decodeur lecture A + if adrange == 5 : # adresse sur 5 bits + self.Adrb12 = Inst ( 'rf2_dec_bufad2_l' + , 'adrb12' + , map = { 'i0' : self._adrb[1] + , 'i1' : self._adrb[2] + , 'nq0' : nadrb1x + , 'q0' : adrb1x + , 'nq1' : nadrb2x + , 'q1' : adrb2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand4Rb = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandrb[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + if j % 2 == 0 : thisMap['i0'] = nadrb1x + else : thisMap['i0'] = adrb1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadrb2x + else : thisMap['i1'] = adrb2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadrb3x + else : thisMap['i2'] = adrb3x + if ( j >> 3 ) % 2 == 0 : thisMap['i3'] = nadrb4x + else : thisMap['i3'] = adrb4x + + self.Nand4Rb[j] = Inst ( 'rf2_dec_nand4' + , 'nand4rb%d' % j + , map = thisMap + ) + + self.Adrb34 = Inst ( 'rf2_dec_bufad2_r' + ,'adrb34' + , map = { 'i0' : self._adrb[3] + , 'i1' : self._adrb[4] + , 'nq0' : nadrb3x + , 'q0' : adrb3x + , 'nq1' : nadrb4x + , 'q1' : adrb4x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 4 : # adresse sur 4 bits + self.Adrb12 = Inst ( 'rf2_dec_bufad2_l' + , 'adrb12' + , map = { 'i0' : self._adrb[1] + , 'i1' : self._adrb[2] + , 'nq0' : nadrb1x + , 'q0' : adrb1x + , 'nq1' : nadrb2x + , 'q1' : adrb2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand3Rb = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandrb[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadrb1x + else : thisMap['i0'] = adrb1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadrb2x + else : thisMap['i1'] = adrb2x + if ( j >> 2 ) % 2 == 0 : thisMap['i2'] = nadrb3x + else : thisMap['i2'] = adrb3x + + self.Nand3Rb[j] = Inst ( 'rf2_dec_nand3' + , 'nand3rb%d' % j + , map = thisMap + ) + + self.Adrb3 = Inst ( 'rf2_dec_bufad1_r' + , 'adrb3' + , map = { 'i' : self._adrb[3] + , 'nq' : nadrb3x + , 'q' : adrb3x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + if adrange == 3 : # adresse sur 3 bits + self.Adrb1 = Inst ( 'rf2_dec_bufad1_l' + , 'adrb1' + , map = { 'i' : self._adrb[1] + , 'nq' : nadrb1x + , 'q' : adrb1x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.Nand2Rb = {} + + for j in range ( half ) : + thisMap = { 'nq' : nandrb[j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j % 2 == 0 : thisMap['i0'] = nadrb1x + else : thisMap['i0'] = adrb1x + if ( j >> 1 ) % 2 == 0 : thisMap['i1'] = nadrb2x + else : thisMap['i1'] = adrb2x + + self.Nand2Rb[j] = Inst ( 'rf2_dec_nand2' + , 'nand2rb%d' % j + , map = thisMap + ) + + self.Adrb2 = Inst ( 'rf2_dec_bufad1_r' + , 'adrb2' + , map = { 'i' : self._adrb[2] + , 'nq' : nadrb2x + , 'q' : adrb2x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ## Layout ## + ############ + def Layout ( self, nbit, nword, type ) : + global adrange + + HCELL = 50 + + # placement des lignes de bit en dessous des buffers + bottom = 0 + + sym1 = NOSYM + sym2 = SYM_X + for i in range ( nbit ) : + if i % 2 : # lignes impaires + sym1 = SYM_Y + sym2 = SYMXY + else : # lignes paires + sym1 = NOSYM + sym2 = SYM_X + + Place ( self.In[i], sym1, XY ( 0, bottom + i * HCELL ) ) + + for j in range ( 0, nword, 2 ) : + if j == 0 and ( type == 1 or type == 3 ) : PlaceRight ( self.Bit[i][j], sym1 ) + else : PlaceRight ( self.Bit[i][j], sym1 ) + + PlaceRight ( self.Bit[i][j + 1], sym2 ) + + PlaceRight ( self.Out[i], sym1 ) + + # s_placement de la ligne contenant les buffers + bottom = nbit * HCELL + + Place ( self.InBuf, NOSYM, XY ( 0, bottom ) ) + + for j in range ( 0, nword, 2 ) : + PlaceRight ( self.Buf[j], NOSYM ) + PlaceRight ( self.Buf[j + 1], SYM_X ) + + PlaceRight ( self.OutBuf, NOSYM ) + + # s_placement des cellules du decodeur ecriture + if type == 2 or type == 3 : + half = nword >> 1 + + # Premiere ligne decodeur ecriture + bottom = ( nbit + 2 ) * HCELL + + Place ( self.Adw0, NOSYM, XY ( 0, bottom ) ) + + for j in range ( half ) : + PlaceRight ( self.SelW[2 * j], SYM_X ) + PlaceRight ( self.SelW[2 * j + 1], NOSYM ) + + PlaceRight ( self.Wen, NOSYM ) + + # Deuxieme ligne decodeur ecriture + bottom = ( nbit + 3 ) * HCELL + + if adrange == 5 : # adresse sur 5 bits + Place ( self.Adw12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand4W[j], SYM_Y, FIXED ) + PlaceRight ( self.Adw34, SYMXY ) + + if adrange == 4 : # adresse sur 4 bits + Place ( self.Adw12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand3W[j], SYM_Y ) + PlaceRight ( self.Adw3, SYMXY ) + + if adrange == 3 : # adresse sur 3 bits + Place ( self.Adw1, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand2W[j], SYM_Y ) + PlaceRight ( self.Adw2, SYMXY ) + + # s_placement des cellules du decodeur lecture A + if type == 2 or type == 3 : + half = nword >> 1 + + # Premiere ligne decodeur lecture A + bottom = ( nbit + 4 ) * HCELL + + Place ( self.Adra0, NOSYM, XY ( 0, bottom ) ) + + for j in range ( half ) : + PlaceRight ( self.SelRa[2 * j], NOSYM ) + PlaceRight ( self.SelRa[2 * j + 1], SYM_X ) + + PlaceRight ( self.RenA, NOSYM ) + + # Deuxieme ligne decodeur lecture A + bottom = ( nbit + 5 ) * HCELL + + if adrange == 5 : # adresse sur 5 bits + Place ( self.Adra12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand4Ra[j], SYM_Y ) + PlaceRight ( self.Adra34, SYMXY ) + + if adrange == 4 : # adresse sur 4 bits + Place ( self.Adra12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand3Ra[j], SYM_Y ) + PlaceRight ( self.Adra3, SYMXY ) + + if adrange == 3 : # adresse sur 3 bits + Place ( self.Adra1, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand2Ra[j], SYM_Y ) + PlaceRight ( self.Adra2, SYMXY ) + + # s_placement des cellules du decodeur lecture B + if type == 2 or type == 3 : + half = nword >> 1 + + # Premiere ligne decodeur lecture A + bottom = ( nbit + 6 ) * HCELL + + Place ( self.Adrb0, NOSYM, XY ( 0, bottom ) ) + + for j in range ( half ) : + PlaceRight ( self.SelRb[2 * j], NOSYM ) + PlaceRight ( self.SelRb[2 * j + 1], SYM_X ) + + PlaceRight ( self.RenB, NOSYM ) + + # Deuxieme ligne decodeur lecture A + bottom = ( nbit + 7 ) * HCELL + + if adrange == 5 : # adresse sur 5 bits + Place ( self.Adrb12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand4Rb[j], SYM_Y ) + PlaceRight ( self.Adrb34, SYMXY ) + + if adrange == 4 : # adresse sur 4 bits + Place ( self.Adrb12, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand3Rb[j], SYM_Y ) + PlaceRight ( self.Adrb3, SYMXY ) + + if adrange == 3 : # adresse sur 3 bits + Place ( self.Adrb1, SYM_Y, XY ( 0, bottom ) ) + for j in range ( half ) : PlaceRight ( self.Nand2Rb[j], SYM_Y ) + PlaceRight ( self.Adrb2, SYMXY ) + + + + ## VBE ## + ######### + def Vbe ( self ) : + print 'RF2 behavior not implemented' + + + + + +##################### +##### DPGEN_RF2 ##### +##################### +class DpgenRf2 ( top_rf2 ) : + + def Interface ( self ) : + top_rf2.Interface ( self, self._param['nbit'], self._param['nword'], 0 ) + + def Netlist ( self ) : + top_rf2.Netlist ( self, self._param['nbit'], self._param['nword'], 0 ) + + def Layout ( self ) : + top_rf2.Layout ( self, self._param['nbit'], self._param['nword'], 0 ) + + +####################### +##### DPGEN_RF2R0 ##### +####################### +class DpgenRf2r0 ( top_rf2 ) : + + def Interface ( self ) : + top_rf2.Interface ( self, self._param['nbit'], self._param['nword'], 1 ) + + def Netlist ( self ) : + top_rf2.Netlist ( self, self._param['nbit'], self._param['nword'], 1 ) + + def Layout ( self ) : + top_rf2.Layout ( self, self._param['nbit'], self._param['nword'], 1 ) + + +###################### +##### DPGEN_RF2D ##### +###################### +class DpgenRf2d ( top_rf2 ) : + + def Interface ( self ) : + top_rf2.Interface ( self, self._param['nbit'], self._param['nword'], 2 ) + + def Netlist ( self ) : + top_rf2.Netlist ( self, self._param['nbit'], self._param['nword'], 2 ) + + def Layout ( self ) : + top_rf2.Layout ( self, self._param['nbit'], self._param['nword'], 2 ) + + +######################## +##### DPGEN_RF2DR0 ##### +######################## +class DpgenRf2dr0 ( top_rf2 ) : + + def Interface ( self ) : + top_rf2.Interface ( self, self._param['nbit'], self._param['nword'], 3 ) + + def Netlist ( self ) : + top_rf2.Netlist ( self, self._param['nbit'], self._param['nword'], 3 ) + + def Layout ( self ) : + top_rf2.Layout ( self, self._param['nbit'], self._param['nword'], 3 ) diff --git a/stratus1/src/dpgen/dpgen_ROM.py b/stratus1/src/dpgen/dpgen_ROM.py new file mode 100644 index 00000000..9f300ba6 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_ROM.py @@ -0,0 +1,937 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_ROM.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +# Le nombre de mots peut prendre cinq valeurs : 64, 128, 256, 512, 1024 +# Le nombre de bits est un multiple de 4 et doit etre inferieur ou egal a 64 +# On peut avoir une sortie tri-state en option (pour construire des ROMs +# de capacite superieure a 1024 mots. +# La largeur est egale a ( nmot / 64 * 50) + 150 (+ 20 si option tristate) +# La hauteur est egale a ( nbit + 8) * 50 pour 64 ou 128 mots +# ( nbit + 9) * 50 pour 256, 512 ou 1024 mots +# +# Les valeurs a encoder dans la ROM sont recuperees dans le tableau data[2048] +# qui contient des "mots" de 32 bits : une valeur est stockee dans deux cases +# consecutives de ce tableau, ce qui permet d'avoir des mots de 64 bits. +# Les poids faibles de la valeur i sont a l'adresse data[2*i] +# Les poids forts de la valeur i sont a l'adresse data[2*i+1] +# +# Les lignes de bit horizontales en ALU2 sont hors grilles et pre-routees +# la ROM respecte le gabarit SXLIB pour ce qui concerne les caissons et les +# alimentations en ALU1 sur les faces est et ouest, mais il n'y a pas +# de continuite des alimentations en ALU1 dans la zone data. +# Pour la partie "donnees", on utilise les cellules suivantes : +# - rom_data_invss +# - rom_data_insel +# - rom_data_midvss +# - rom_data_midsel +# - rom_data_outvss +# - rom_data_outsel +# - rom_data_outvss_ts +# - rom_data_outsel_ts +# +# Pour le decodeur, on utilise les cellules suivantes : +# - rom_dec_adbuf +# - rom_dec_nop +# - rom_dec_prech +# - rom_dec_col2 +# - rom_dec_col3 +# - rom_dec_col4 +# - rom_dec_colbuf +# - rom_dec_line01 +# - rom_dec_line23 +# - rom_dec_line45 +# - rom_dec_line67 +# - rom_dec_selmux01 +# - rom_dec_selmux23 +# - rom_dec_selmux45 +# - rom_dec_selmux67 +# - rom_dec_selmux67_128 +# - rom_dec_selmux01_ts +# - rom_dec_selmux23_ts +# - rom_dec_selmux45_ts +# - rom_dec_selmux67_ts +# - rom_dec_selmux67_128_ts + +class TopRom ( Model ) : + + def Interface ( self ) : + self.nbit = self._param['nbit'] + self.nword = self._param['nword'] + + if self.nword == 64 : adrange = 6 + elif self.nword == 128 : adrange = 7 + elif self.nword == 256 : adrange = 8 + elif self.nword == 512 : adrange = 9 + elif self.nword == 1024 : adrange = 10 + else : + print "Error : DPGEN_ROM" + print "The word number (nword := %d) ", nword, "can only takes values : 64, 128, 256, 512 or 1024.\n" + sys.exit ( 3 ) + + if self.nbit % 4 != 0 or self.nbit > 64 or self.nbit < 4 : + raise "\n[Stratus ERROR] DPGEN_ROM : The bus width (nbit := %d) ", nbit, "must be multiple of 4 and no larger than 64.\n" + + self.ck = SignalIn ( "ck", 1 ) + self.selrom = SignalIn ( "selrom", 1 ) + + self.ad = SignalIn ( "ad", adrange ) + self.data = SignalOut ( "data", self.nbit ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self, type ) : + + ### Acquisition du tableau des valeurs a encoder ### +# ICI IL FAUT APPELER LE PARSER +# for(i=0 ; i<1024 ; i++) { +# data[2*i] = i; +# data[2*i+1] = 1024 - i; +# } +# dpgen_ROM_code ( LV_name, self.nbit, self.nword, 0, 0, data ) + + # Signaux internes + nck = Signal ( "nck", 1 ) + + prech = Signal ( "prech", 1 ) + nprech = Signal ( "nprech", 1 ) + + mux0 = Signal ( "mux0", 1 ) + mux1 = Signal ( "mux1", 1 ) + mux2 = Signal ( "mux2", 1 ) + mux3 = Signal ( "mux3", 1 ) + mux4 = Signal ( "mux4", 1 ) + mux5 = Signal ( "mux5", 1 ) + mux6 = Signal ( "mux6", 1 ) + mux7 = Signal ( "mux7", 1 ) + + sel0 = Signal ( "sel0", 1 ) + sel1 = Signal ( "sel1", 1 ) + sel2 = Signal ( "sel2", 1 ) + sel3 = Signal ( "sel3", 1 ) + sel4 = Signal ( "sel4", 1 ) + sel5 = Signal ( "sel5", 1 ) + sel6 = Signal ( "sel6", 1 ) + sel7 = Signal ( "sel7", 1 ) + + bit0 = Signal ( "bit0", self.nbit ) + bit1 = Signal ( "bit1", self.nbit ) + bit2 = Signal ( "bit2", self.nbit ) + bit3 = Signal ( "bit3", self.nbit ) + bit4 = Signal ( "bit4", self.nbit ) + bit5 = Signal ( "bit5", self.nbit ) + bit6 = Signal ( "bit6", self.nbit ) + bit7 = Signal ( "bit7", self.nbit ) + line0 = Signal ( "line0", self.nbit ) + line1 = Signal ( "line1", self.nbit ) + line2 = Signal ( "line2", self.nbit ) + line3 = Signal ( "line3", self.nbit ) + line4 = Signal ( "line4", self.nbit ) + line5 = Signal ( "line5", self.nbit ) + line6 = Signal ( "line6", self.nbit ) + line7 = Signal ( "line7", self.nbit ) + + mux0 = Signal ( "mux0", 1 ) + mux1 = Signal ( "mux1", 1 ) + mux2 = Signal ( "mux2", 1 ) + mux3 = Signal ( "mux3", 1 ) + mux4 = Signal ( "mux4", 1 ) + mux5 = Signal ( "mux5", 1 ) + mux6 = Signal ( "mux6", 1 ) + mux7 = Signal ( "mux7", 1 ) + + a0 = Signal ( "a0", 1 ) + na0 = Signal ( "na0", 1 ) + a1 = Signal ( "a1", 1 ) + na1 = Signal ( "na1", 1 ) + a2 = Signal ( "a2", 1 ) + na2 = Signal ( "na2", 1 ) + a3 = Signal ( "a3", 1 ) + na3 = Signal ( "na3", 1 ) + a4 = Signal ( "a4", 1 ) + na4 = Signal ( "na4", 1 ) + a5 = Signal ( "a5", 1 ) + na5 = Signal ( "na5", 1 ) + a6x = Signal ( "a6x", 1 ) + na6x = Signal ( "na6x", 1 ) + a7x = Signal ( "a7x", 1 ) + na7x = Signal ( "na7x", 1 ) + a8x = Signal ( "a8x", 1 ) + na8x = Signal ( "na8x", 1 ) + a9x = Signal ( "a9x", 1 ) + na9x = Signal ( "na9x", 1 ) + + col = Signal ( "col", self.nbit ) + + In = {} + Bit = {} + Out = {} + for i in range ( self.nbit ) : + valeur = i % 4 + if valeur == 0 : + cellin = "rom_data_invss" + cellmid = "rom_data_midvss" + if type == 0 : cellout = "rom_data_outvss" + else : cellout = "rom_data_outvss_ts" + elif valeur == 1 : + cellin = "rom_data_insel" + cellmid = "rom_data_midsel" + if type == 0 : cellout = "rom_data_outsel" + else : cellout = "rom_data_outsel_ts" + elif valeur == 2: + cellin = "rom_data_insel" + cellmid = "rom_data_midsel" + if type == 0 : cellout = "rom_data_outsel" + else : cellout = "rom_data_outsel_ts" + elif valeur == 3 : + cellin = "rom_data_invss" + cellmid = "rom_data_midvss" + if type == 0 : cellout = "rom_data_outvss" + else : cellout = "rom_data_outvss_ts" + + In[i] = Inst ( cellin + , "in%d" % i + , map = { 'prech' : prech + , 'bit0' : bit0[i] + , 'bit1' : bit1[i] + , 'bit2' : bit2[i] + , 'bit3' : bit3[i] + , 'bit4' : bit4[i] + , 'bit5' : bit5[i] + , 'bit6' : bit6[i] + , 'bit7' : bit7[i] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + BitBis = {} + Bit[i] = BitBis + for j in range ( 0, self.nword, 64 ) : + Bit[i][j] = Inst ( cellmid + , "bit%d_%d" % ( i, j ) + , map = { 'sela' : line0[j] + , 'selb' : line2[j] + , 'selc' : line4[j] + , 'seld' : line6[j] + , 'bit0' : bit0 [i] + , 'bit1' : bit1 [i] + , 'bit2' : bit2 [i] + , 'bit3' : bit3 [i] + , 'bit4' : bit4 [i] + , 'bit5' : bit5 [i] + , 'bit6' : bit6 [i] + , 'bit7' : bit7 [i] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + Bit[i][j+32] = Inst ( cellmid + , "bit%d_%d" % ( i, j+32 ) + , map = { 'sela' : line1[j] + , 'selb' : line3[j] + , 'selc' : line5[j] + , 'seld' : line7[j] + , 'bit0' : bit0 [i] + , 'bit1' : bit1 [i] + , 'bit2' : bit2 [i] + , 'bit3' : bit3 [i] + , 'bit4' : bit4 [i] + , 'bit5' : bit5 [i] + , 'bit6' : bit6 [i] + , 'bit7' : bit7 [i] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + thisMap = { 'nprech' : nprech + , 'mux0' : mux0 + , 'mux1' : mux1 + , 'mux2' : mux2 + , 'mux3' : mux3 + , 'mux4' : mux4 + , 'mux5' : mux5 + , 'mux6' : mux6 + , 'mux7' : mux7 + , 'bit0' : bit0[i] + , 'bit1' : bit1[i] + , 'bit2' : bit2[i] + , 'bit3' : bit3[i] + , 'bit4' : bit4[i] + , 'bit5' : bit5[i] + , 'bit6' : bit6[i] + , 'bit7' : bit7[i] + , 'q' : data[i] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if type == 1 : + thisMap['enx'] = enx + thisMap['nenx'] = nenx + Out[i] = Inst ( cellout + , "out%d" % i + , map = thisMap + ) + + ## Cellules decodeur ## + # Lignes 0 et 1 + Prech = Inst ( "rom_dec_prech" + , "prech" + , map = { 'nck' : nck + , 'prech' : prech + , 'nprech' : nprech + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + And01 = {} + for j in range ( 0, self.nword, 64 ) : + thisMap = { 'nck0' : nck + , 'nck1' : nck + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'line0' : line0[j] + , 'line1' : line1[j] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if self.nword != 64 : thisMap['col'] = col[j] + else : thisMap['col'] = One ( 1 ) + And01[j] = Inst ( "rom_dec_line01" + , "and01_%d" % j + , map = thisMap + ) + + if type == 0 : model = "rom_dec_selmux01" + else : model = "rom_dec_selmux01_rs" + thisMap = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'ck' : self.ck + , 'selrom' : self.selrom + , 'nck' : nck + , 'mux0' : mux0 + , 'sel0' : sel0 + , 'mux1' : mux1 + , 'sel1' : sel1 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if type == 1 : + thisMap['enx'] = enx + thisMap['nenx'] = nenx + Selmux01 = Inst ( model + , "selmux01" + , map = thisMap + ) + + # Lignes 2 et 3 + Ad4 = Inst ( "rom_dec_adbuf" + , "ad4" + , map = { 'ad' : self.ad[4] + , 'adx' : a4 + , 'nadx' : na4 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + Ad5 = Inst ( "rom_dec_adbuf" + , "ad5" + , map = { 'ad' : self.ad[5] + , 'adx' : a5 + , 'nadx' : na5 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + And23 = {} + for j in range ( 0, self.nword, 64 ) : + thisMap = { 'nck2' : nck + , 'nck3' : nck + , 'sel2' : sel2 + , 'sel3' : sel3 + , 'line2' : line2[j] + , 'line3' : line3[j] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if self.nword != 64 : thisMap['col'] = col[j] + else : thisMap['col'] = One ( 1 ) + And23[j] = Inst ( "rom_dec_line23" + , "and23_%d" % j + , map = thisMap + ) + + if type == 0 : model = "rom_dec_selmux23" + else : model = "rom_dec_selmux23_rs" + thisMap = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'ck' : self.ck + , 'selrom' : self.selrom + , 'nck' : nck + , 'mux2' : mux2 + , 'sel2' : sel2 + , 'mux3' : mux3 + , 'sel3' : sel3 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if type == 1 : + thisMap['enx'] = enx + thisMap['nenx'] = nenx + Selmux23 = Inst ( "rom_dec_selmux23" + , "selmux23" + , map = thisMap + ) + + # Lignes 4 et 5 + Ad2 = Inst ( "rom_dec_adbuf" + , "ad2" + , map = { 'ad' : self.ad[2] + , 'adx' : a2 + , 'nadx' : na2 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + Ad3 = Inst ( "rom_dec_adbuf" + , "ad3" + , map = { 'ad' : self.ad[3] + , 'adx' : a3 + , 'nadx' : na3 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + And45 = {} + for j in range ( 0, self.nword, 64 ) : + thisMap = { 'nck4' : nck + , 'nck5' : nck + , 'sel4' : sel4 + , 'sel5' : sel5 + , 'line4' : line4[j] + , 'line5' : line5[j] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if self.nword != 64 : thisMap['col'] = col[j] + else : thisMap['col'] = One ( 1 ) + And45[j] = Inst ( "rom_dec_line45" + , "and45_%d" % j + , map = thisMap + ) + + if type == 0 : model = "rom_dec_selmux45" + else : model = "rom_dec_selmux45_rs" + thisMap = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'ck' : self.ck + , 'selrom' : self.selrom + , 'nck' : nck + , 'mux4' : mux4 + , 'sel5' : sel4 + , 'mux5' : mux5 + , 'sek5' : sel5 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if type == 1 : + thisMap['enx'] = enx + thisMap['nenx'] = nenx + Selmux45 = Inst ( model + , "selmux23" + , map = thisMap + ) + + # Lignes 6 et 7 + Ad0 = Inst ( "rom_dec_adbuf" + , "ad0" + , map = { 'ad' : self.ad[0] + , 'adx' : a0 + , 'nadx' : na0 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + Ad1 = Inst ( "rom_dec_adbuf" + , "ad1" + , map = { 'ad' : self.ad[1] + , 'adx' : a1 + , 'nadx' : na1 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + And67 = {} + for j in range ( 0, self.nword, 64 ) : + thisMap = { 'nck6' : nck + , 'nck7' : nck + , 'sel6' : sel6 + , 'sel7' : sel7 + , 'line6' : line6[j] + , 'line7' : line7[j] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if self.nword != 64 : thisMap['col'] = col[j] + else : thisMap['col'] = One ( 1 ) + And67[j] = Inst ( "rom_dec_line67" + , "and67_%d" % j + , map = thisMap + ) + + if self.nword != 128 : # pas de sortie tristate + if type == 0 : model = "rom_dec_selmux67" + else : model = "rom_dec_selmux67_ts" + thisMap = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'ck' : self.ck + , 'selrom' : self.selrom + , 'nck' : nck + , 'mux6' : mux6 + , 'sel6' : sel6 + , 'mux7' : mux7 + , 'sel7' : sel7 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if type == 1 : + thisMap['enx'] = enx + thisMap['nenx'] = nenx + Selmux67 = Inst ( model + , "selmux67" + , map = thisMap + ) + else : # pas de sortie tristate - 128 mots + if type == 0 : model = "rom_dec_selmux128" + else : model = "rom_dec_selmux128_ts" + thisMap = { 'a0' : a0 + , 'na0' : na0 + , 'a1' : a1 + , 'na1' : na1 + , 'a2' : a2 + , 'na2' : na2 + , 'a3' : a3 + , 'na3' : na3 + , 'a4' : a4 + , 'na4' : na4 + , 'a5' : a5 + , 'na5' : na5 + , 'a6' : self.ad[6] + , 'selrom' : self.selrom + , 'a6x' : col[64] + , 'na6x' : col[0] + , 'mux6' : mux6 + , 'sel6' : sel6 + , 'mux7' : mux7 + , 'sel7' : sel7 + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if type == 1 : + thisMap['enx'] = enx + thisMap['nenx'] = nenx + Selmux67 = Inst ( model + , "selmux67" + , map = thisMap + ) + + # Ligne 9 dans le cas 1024 mots + if self.nword == 1024 : + Nop = Inst ( "rom_dec_nop" + , "nop" + , map = { 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + Col = {} + for j in range ( 0, self.nword, 64 ) : + thisMap = { 'q' : col[j] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if ( j >> 6 ) % 2 == 0 : thisMap['i0'] = na6x + else : thisMap['i0'] = a6x + if ( j >> 7 ) % 2 == 0 : thisMap['i1'] = na7x + else : thisMap['i1'] = a7x + if ( j >> 8 ) % 2 == 0 : thisMap['i2'] = na8x + else : thisMap['i2'] = a8x + if ( j >> 9 ) % 2 == 0 : thisMap['i3'] = na9x + else : thisMap['i3'] = a9x + Col[j] = Inst ( "rom_dec_col4" + , "col_%d" % j + , map = thisMap + ) + + ColBuf6 = Inst ( "rom_dec_colbuf" + , "colbuf6" + , map = { 'a' : self.ad[6] + , 'ax' : a6x + , 'nax' : na6x + , 'vdd' : self.vdd + , 'vss' : self.vss + ) + ColBuf7 = Inst ( "rom_dec_colbuf" + , "colbuf7" + , map = { 'a' : self.ad[7] + , 'ax' : a7x + , 'nax' : na7x + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + ColBuf8 = Inst ( "rom_dec_colbuf" + , "colbuf8" + , map = { 'a' : self.ad[8] + , 'ax' : a8x + , 'nax' : na8x + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + ColBuf9 = Inst ( "rom_dec_colbuf" + , "colbuf9" + , map = { 'a' : self.ad[9] + , 'ax' : a9x + , 'nax' : na9x + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + # Ligne 9 dans le cas 512 mots + if self.nword == 512 : + Nop = Inst ( "rom_dec_nop" + , "nop" + , map = { 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + for j in range ( 0, self.nword, 64 ) : + thisMap = { 'q' : col[j] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if ( j >> 6 ) % 2 == 0 : thisMap['i0'] = na6x + else : thisMap['i0'] = a6x + if ( j >> 7 ) % 2 == 0 : thisMap['i1'] = na7x + else : thisMap['i1'] = a7x + if ( j >> 8 ) % 2 == 0 : thisMap['i2'] = na8x + else : thisMap['i2'] = a8x + Col[j] = Inst ( "rom_dec_col3" + , "col_%d" % j + , map = thisMap + ) + + Colbuf6 = Inst ( "rom_dec_colbuf" + , "colbuf6" + , map = { 'a' : ad[6] + , 'ax' : a6x + , 'nax' : na6x + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + Colbuf7 = Inst ( "rom_dec_colbuf" + , "colbuf7" + , map = { 'a' : ad[7] + , 'ax' : a7x + , 'nax' : na7x + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + Colbuf8 = Inst ( "rom_dec_colbuf" + , "colbuf8" + , map = { 'a' : ad[8] + , 'ax' : a8x + , 'nax' : na8x + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + # Ligne 9 dans le cas 256 mots + if self.nword == 256 : + Nop = Inst ( "rom_dec_nop" + , "nop" + , map = { 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + Col = {} + for j in range ( 0, self.nword, 64 ) : + thisMap = { 'q' : col[j] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + if ( j >> 6 ) % 2 == 0 : thisMap['i0'] = na6x + else : thisMap['i0'] = a6x + if ( j >> 7 ) % 2 == 0 : thisMap['i1'] = na7x + else : thisMap['i1'] = a7x + Col[j] = Inst ( "rom_dec_col2" + , "col_%d" % j + , map = thisMap + ) + + Colbuf6 = Inst ( "rom_dec_colbuf" + , "colbuf6" + , map = { 'a' : ad[6] + , 'ax' : a6x + , 'nax' : na6x + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + ColBuf7 = Inst ( "rom_dec_colbuf" + , "colbuf7" + , map = { 'a' : ad[7] + , 'ax' : a7x + , 'nax' : na7x + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def Layout ( self ) : + ## Placement des lignes du plan memoire ## + for i in range ( self.nbit ) : + val = i % 4 + if val == 0 : sym = NOSYM + elif val == 1 : sym = SYM_Y + elif val == 2 : sym = NOSYM + elif val == 3 : sym = SYM_Y + + Place ( In(i], sym, 0, i*HCELL ) + + for j in range ( 0, self.nword, 64 ) : + PlaceRight ( Bit[i][j], sym ) + PlaceRight ( Bit[i][j+32], sym ) + + PlaceRight ( Out[i], sym ) + + ## Placement des cellules decodeur ## + + # Lignes 0 et 1 + Place ( Prech, NOSYM, 0, nbit*HCELL ) + for j in range ( 0, self.nword, 64 ) : PlaceRight ( And01[j], NOSYM ) + PlaceRight ( Selmux01, NOSYM ) + + # Lignes 2 et 3 + Place ( Ad4, SYM_Y, 0, (nbit+3)*HCELL ) + Place ( Ad5, NOSYM, 0, (nbit+2)*HCELL ) + for j in range ( 0, self.nword, 64 ) : PlaceRight ( And23[j], NOSYM ) + PlaceRight ( Selmux23, NOSYM ) + + # Lignes 4 et 5 + Place ( Ad2, SYM_Y, 0, (nbit+5)*HCELL ) + Place ( Ad3, NOSYM, 0, (nbit+4)*HCELL ) + for j in range ( 0, self.nword, 64 ) : PlaceRight ( And45[j], NOSYM ) + Place ( Selmux45, NOSYM ) + + # Lignes 6 et 7 + Place ( Ad0, SYM_Y, 0, (nbit+7)*HCELL ) + Place ( Ad1, NOSYM, 0, (nbit+6)*HCELL ) + for j in range ( 0, self.nword, 64 ) : PlaceRight ( And67[j], NOSYM ) + PlaceRight ( Selmux67, NOSYM ) + + # Ligne 9 dans le cas 1024 mots + if self.nword == 1024 : + Place ( Nop, NOSYM, 0, (nbit+8)*HCELL ) + for j in range ( 0, self.nword, 64 ) : PlaceRight ( Col, NOSYM ) + PlaceRight ( ColBuf6, NOSYM ) + PlaceRight ( ColBuf7, NOSYM ) + PlaceRight ( ColBuf8, NOSYM ) + PlaceRight ( ColBuf9, NOSYM ) + # Ligne 9 dans le cas 512 mots + elif self.nword == 512 : + Place ( Nop, NOSYM, 0, (nbit+8)*HCELL ) + for j in range ( 0, self.nword, 64 ) : PlaceRight ( Col[j], NOSYM ) + PlaceRight ( ColBuf6, NOSYM ) + PlaceRight ( ColBuf7, NOSYM ) + PlaceRight ( ColBuf8, NOSYM ) + # Ligne 9 dans le cas 256 mots + elif self.nword == 256 : + Place ( Nop, NOSYM, 0, (nbit+8)*HCELL ) + for j in range ( 0, self.nword, 64 ) : PlaceRight ( Col[j], NOSYM ) + PlaceRight ( ColBuf6, NOSYM ) + PlaceRight ( ColBuf7, NOSYM ) + + def ROM_VHDL ( self ) : + global LV_flags + global LV_ModelName + + pass +# fileName = LV_ModelName + ".vbe" +# +# file = open ( fileName, "w+" ) +# +# if self.nword == 64 : adrange = 6 +# elif self.nword == 128 : adrange = 7 +# elif self.nword == 256 : adrange = 8 +# elif self.nword == 512 : adrange = 9 +# elif self.nword == 1024 : adrange = 10 +# +# sBusWide0 = VHDL_BUS_WIDE ( self.nbit - 1, 0, self.nbit, LV_flags ) +# sBusWide1 = VHDL_BUS_WIDE ( adrange - 1, 0, self.nbit, LV_flags ) +# +# ## Entity description ## +# file.write ( "\nENTITY %s IS\n PORT (\n" % LV_ModelName ) +# +# file.write ( "%14s : in BIT;\n" % "ck" ) +# file.write ( "%14s : in BIT;\n" % "selrom" ) +# file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "ad", sBusWide1 ) ) +# file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "data", sBusWide0 ) ) +# +# ## Power supplies terminals ## +# file.write ( "%14s : in BIT;\n" % "vdd" ) +# file.write ( "%14s : in BIT\n" % "vss" ) +# +# ## End of entity description ## +# file.write ( " );\nEND %s;\n\n\n" % LV_ModelName ) +# +# ## Architecture description ## +# file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % LV_ModelName ) +# +# ## Signals ## +# +# +# +# ## Behavior ## +# file.write ( "\nBEGIN\n\n" ) +# +# +# +# +# +# ## Assert ## +# file.write ( " ASSERT (vdd = '1')\n" ) +# file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % LV_modelName ) +# file.write ( " SEVERITY WARNING;\n\n" ) +# +# +# file.write ( " ASSERT (vss = '0')\n" ) +# file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % LV_modelName ) +# file.write ( " SEVERITY WARNING;\n\n" ) +# +# ## End of Architectural description ## +# file.write ( "END VBE;\n" ) +# +# file.close () + +#################### +##### DpgenROM ##### +#################### +class DpgenROM ( TopRom ) : + + def Interface ( self ) : TopRom.Interface ( self ) + def Netlist ( self ) : TopRom.Netlist ( self, 0 ) + def Layout ( self ) : topRom.Layout ( self ) + def Vbe ( self ) : topRom.Vbe ( self ) + + +###################### +##### DpgenROMTS ##### +###################### +class DpgenROMTS ( TopRom ) : + + def Interface ( self ) : TopRom.Interface ( self ) + def Netlist ( self ) : TopRom.Netlist ( self, 1 ) + def Layout ( self ) : topRom.Layout ( self ) + def Vbe ( self ) : topRom.Vbe ( self ) diff --git a/stratus1/src/dpgen/dpgen_ROM2.py b/stratus1/src/dpgen/dpgen_ROM2.py new file mode 100644 index 00000000..2550b934 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_ROM2.py @@ -0,0 +1,226 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_ROM2.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class DpgenRom2 ( Model ) : + + ## Interface ## + ############### + def Interface ( self ) : + + self._nbit = self._param['nbit'] + + self._sel0 = SignalIn ( "sel0", 1 ) + self._q = SignalOut ( "q", self._nbit ) + + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + + ## Netlist ## + ################## + def Netlist ( self ) : + global LV_xl0, LV_xl1, LV_iLeafCell + + val = [] + val.append ( self._param['val0'] ) + val.append ( self._param['val1'] ) + + # Parses the constants + LV_xl0 = newxl () + LV_xl0.atoxl ( val[0] ) + LV_xl0._size = self._nbit + + LV_xl1 = newxl () + LV_xl1.atoxl ( val[1] ) + LV_xl1._size = self._nbit + + LV_iLeafCell = 0 + + # Signal + ni0x = Signal ( "ni0x", 1 ) + + + # Loop for all the data slices + self.Cell = {} + + for iSlice in range ( self._nbit ) : + iCell = get_index_Cell ( iSlice, DPGEN_ROM2, LV_xl0, LV_xl1 ) + sModel = get_model_Cell ( iSlice, DPGEN_ROM2, iCell, LV_iLeafCell ) + + if iCell == 0 : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'nq' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif iCell == 3 : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif iCell == 1 : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : ni0x + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif iCell == 2 : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : ni0x + , 'nq' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Add the buffer + if iSlice % 2 : iSlice += 1 + + sModel = get_model_Buffer ( DPGEN_ROM2, LV_iLeafCell ) + + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : self._sel0 + , 'nix' : ni0x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ## Layout ## + ############ + def Layout ( self ) : + + # Loop for all the data slices + for iSlice in range ( self._nbit ) : + Place ( self.Cell[iSlice] + , slice_to_sym ( iSlice ) + , XY ( 0, slice_to_y ( iSlice ) ) + ) + + # Add the buffer cell + if iSlice % 2 : iSlice += 1 + + Place ( self.Cell[iSlice] + , slice_to_sym ( iSlice ) + , XY ( 0, slice_to_y ( iSlice ) ) + ) + + + ########## uROM_VHDL ########## + ############################### + def Vbe ( self ) : + global LV_xl0 + global LV_xl1 + global LV_xl2 + global LV_xl3 + + flags = self._param['flags'] + + fileName = self._name + ".vbe" + + file = open ( fileName, "w+" ) + + sBusWide = VHDL_BUS_WIDE ( self._nbit - 1, 0, self._nbit, flag ) + + ## Entity description ## + file.write ( "\nENTITY %s IS\n PORT (\n" % self._name ) + + file.write ( "%14s : in BIT;\n" % "sel0" ) + + ## Output data bus ## + file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "q", sBusWide ) ) + + ## Power supplies terminals ## + file.write ( "%14s : in BIT;\n" % "vdd" ) + file.write ( "%14s : in BIT\n" % "vss" ) + + ## End of entity description ## + file.write ( " );\nEND %s;\n\n\n" % self._name ) + + ## Architecture description ## + file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % self._name ) + + file.write ( "BEGIN\n\n") + + ## Behavior ## + file.write ( " WITH sel0 SELECT\n" ) + file.write ( " q <= %s WHEN \'0\',\n" % LV_xl0.xltovhdl () ) + file.write ( " %s WHEN \'1\';\n\n" % LV_xl1.xltovhdl () ) + + ## Assert ## + file.write ( " ASSERT (vdd = '1')\n" ) + file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % self._name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + file.write ( " ASSERT (vss = '0')\n" ) + file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % self._name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + ## End of architecture description ## + file.write ( "END VBE;\n" ) + + file.close () diff --git a/stratus1/src/dpgen/dpgen_ROM4.py b/stratus1/src/dpgen/dpgen_ROM4.py new file mode 100644 index 00000000..ba3e4154 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_ROM4.py @@ -0,0 +1,294 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_ROM4.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class DpgenRom4 ( Model ) : + + ## Interface ## + ############### + def Interface ( self ) : + + self._nbit = self._param['nbit'] + + self._sel0 = SignalIn ( "sel0", 1 ) + self._sel1 = SignalIn ( "sel1", 1 ) + + self._q = SignalOut ( "q", self._nbit ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + ## Netlist ## + ############# + def Netlist ( self ) : + global LV_xl0, LV_xl1, LV_xl2, LV_xl3, LV_iLeafCell + + # Parses the constants + LV_xl0 = newxl () + LV_xl0.atoxl ( self._param['val0'] ) + LV_xl0._size = self._nbit + + LV_xl1 = newxl () + LV_xl1.atoxl ( self._param['val1'] ) + LV_xl1._size = self._nbit + + LV_xl2 = newxl () + LV_xl2.atoxl ( self._param['val2'] ) + LV_xl2._size = self._nbit + + LV_xl3 = newxl () + LV_xl3.atoxl ( self._param['val3'] ) + LV_xl3._size = self._nbit + + + LV_iLeafCell = CELLS_ROM2 + + + # Signal + i0x = Signal ( "i0x", 1 ) + ni0x = Signal ( "ni0x", 1 ) + i1x = Signal ( "i1x", 1 ) + ni1x = Signal ( "ni1x", 1 ) + + sI0 = Signal ( "si0" ) + sI1 = Signal ( "si1" ) + + + # Loop for all the data slices + self.Cell = {} + + for iSlice in range ( self._nbit ) : + iCell = get_index_Cell ( iSlice, DPGEN_ROM4, LV_xl0, LV_xl1, LV_xl2, LV_xl3 ) + sModel = get_model_Cell ( iSlice, DPGEN_ROM4, iCell, LV_iLeafCell ) + + sI0 = i0x + sI1 = i1x + + # Select the inputs + if iCell == 8 or iCell == 9 or iCell == 10 or iCell == 14 : + sI0 = i0x + sI1 = i1x + elif iCell == 2 or iCell == 11 : + sI0 = i0x + sI1 = ni1x + elif iCell == 4 or iCell == 13 : + sI0 = ni0x + sI1 = i1x + elif iCell == 1 or iCell == 5 or iCell == 6 or iCell == 7 : + sI0 = ni0x + sI1 = ni1x + elif iCell == 3 : + sI0 = ni1x + elif iCell == 12 : + sI0 = i1x + + # Select the gate + if sModel[0:4] == "zero" : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'nq' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif sModel[0:3] == "one" : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif sModel[0:3] == "buf" : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : sI0 + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif sModel[0:3] == "inv" : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : sI0 + , 'nq' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif sModel[0:2] in ( "a2", "o2" ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0' : sI0 + , 'i1' : sI1 + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif sModel[0:11] == "dp_rom4_xr2" or sModel[0:12] == "dp_rom4_nxr2" : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0x' : i0x + , 'i1x' : i1x + , 'ni0x' : ni0x + , 'ni1x' : ni1x + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + # Add the buffer + if iSlice % 2 : iSlice += 1 + + sModel = get_model_Buffer ( DPGEN_ROM4, LV_iLeafCell ) + + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0' : self._sel0 + , 'i1' : self._sel1 + , 'i0x' : i0x + , 'i1x' : i1x + , 'ni0x' : ni0x + , 'ni1x' : ni1x + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ## Layout ## + ############ + def Layout (self ) : + + # Loop for all the data slices + for iSlice in range ( self._nbit ) : + Place ( self.Cell[iSlice] + , slice_to_sym ( iSlice ) + , XY ( 0, slice_to_y ( iSlice ) ) + ) + + # Add the buffer cell + if iSlice % 2 : iSlice += 1 + + Place ( self.Cell[iSlice] + , slice_to_sym ( iSlice ) + , XY ( 0, slice_to_y ( iSlice ) ) + ) + + + ## VBE ## + ######### + def Vbe ( self ) : + global LV_xl0 + global LV_xl1 + global LV_xl2 + global LV_xl3 + + flags = self._param['flags'] + + fileName = self._name + ".vbe" + + file = open ( fileName, "w+" ) + + sBusWide = VHDL_BUS_WIDE ( self._nbit - 1, 0, self._nbit, flag ) + + ## Entity description ## + file.write ( "\nENTITY %s IS\n PORT (\n" % self._name ) + + ## Controls Terminals ## + file.write ( "%14s : in BIT;\n" % "sel1" ) + + file.write ( "%14s : in BIT;\n" % "sel0" ) + + ## Output data bus ## + file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "q", sBusWide ) ) + + ## Power supplies terminals ## + file.write ( "%14s : in BIT;\n" % "vdd" ) + file.write ( "%14s : in BIT\n" % "vss" ) + + ## End of entity description ## + file.write ( " );\nEND %s;\n\n\n" % self._name ) + + ## Architecture description ## + file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % self._name ) + + file.write ( "BEGIN\n\n") + + ## Behavior ## + file.write ( " WITH sel1 & sel0 SELECT\n" ) + file.write ( " q <= %s WHEN B\"00\",\n" % LV_xl0.xltovhdl () ) + file.write ( " %s WHEN B\"01\",\n" % LV_xl1.xltovhdl () ) + file.write ( " %s WHEN B\"10\",\n" % LV_xl2.xltovhdl () ) + file.write ( " %s WHEN B\"11\";\n\n" % LV_xl3.xltovhdl () ) + + ## Assert ## + file.write ( " ASSERT (vdd = '1')\n" ) + file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % self._name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + file.write ( " ASSERT (vss = '0')\n" ) + file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % self._name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + ## End of architecture description ## + file.write ( "END VBE;\n" ) + + file.close () diff --git a/stratus1/src/dpgen/dpgen_Regular.py b/stratus1/src/dpgen/dpgen_Regular.py new file mode 100644 index 00000000..7945bb09 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_Regular.py @@ -0,0 +1,1463 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_Regular.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + + +# Local constants +MAX_TDRIVE = 8 +ERROR_INDEX = 4096 +SIZE_SNAME = 1024 + + +# Local variables (prefix "LV_") +LV_ttDrive = [] +LV_ttDrive.append ( [1, 0, 0, 0, 0, 0, 0, 0] ) +LV_ttDrive.append ( [1, 2, 4, 8, 0, 0, 0, 0] ) +LV_ttDrive.append ( [2, 4, 8, 0, 0, 0, 0, 0] ) +LV_ttDrive.append ( [1, 4, 0, 0, 0, 0, 0, 0] ) +LV_ttDrive.append ( [2, 4, 0, 0, 0, 0, 0, 0] ) +LV_ttDrive.append ( [4, 8, 0, 0, 0, 0, 0, 0] ) + +LV_tsLeafCell = [] +LV_tsLeafCell.append ( "inv_x1" ) +LV_tsLeafCell.append ( "inv_x2" ) +LV_tsLeafCell.append ( "inv_x4" ) +LV_tsLeafCell.append ( "inv_x8" ) +LV_tsLeafCell.append ( "buf_x2" ) +LV_tsLeafCell.append ( "buf_x4" ) +LV_tsLeafCell.append ( "buf_x8" ) +LV_tsLeafCell.append ( "na2_x1" ) +LV_tsLeafCell.append ( "na2_x4" ) +LV_tsLeafCell.append ( "na3_x1" ) +LV_tsLeafCell.append ( "na3_x4" ) +LV_tsLeafCell.append ( "na4_x1" ) +LV_tsLeafCell.append ( "na4_x4" ) +LV_tsLeafCell.append ( "a2_x2" ) +LV_tsLeafCell.append ( "a2_x4" ) +LV_tsLeafCell.append ( "a3_x2" ) +LV_tsLeafCell.append ( "a3_x4" ) +LV_tsLeafCell.append ( "a4_x2" ) +LV_tsLeafCell.append ( "a4_x4" ) +LV_tsLeafCell.append ( "no2_x1" ) +LV_tsLeafCell.append ( "no2_x4" ) +LV_tsLeafCell.append ( "no3_x1" ) +LV_tsLeafCell.append ( "no3_x4" ) +LV_tsLeafCell.append ( "no4_x1" ) +LV_tsLeafCell.append ( "no4_x4" ) +LV_tsLeafCell.append ( "o2_x2" ) +LV_tsLeafCell.append ( "o2_x4" ) +LV_tsLeafCell.append ( "o3_x2" ) +LV_tsLeafCell.append ( "o3_x4" ) +LV_tsLeafCell.append ( "o4_x2" ) +LV_tsLeafCell.append ( "o4_x4" ) +LV_tsLeafCell.append ( "nxr2_x1" ) +LV_tsLeafCell.append ( "nxr2_x4" ) +LV_tsLeafCell.append ( "xr2_x1" ) +LV_tsLeafCell.append ( "xr2_x4" ) +LV_tsLeafCell.append ( "dp_nmux_x1_buf" ) +LV_tsLeafCell.append ( "dp_nmux_x1" ) +LV_tsLeafCell.append ( "dp_mux_x2_buf" ) +LV_tsLeafCell.append ( "dp_mux_x2" ) +LV_tsLeafCell.append ( "dp_mux_x4_buf" ) +LV_tsLeafCell.append ( "dp_mux_x4" ) +LV_tsLeafCell.append ( "dp_nts_x2_buf" ) +LV_tsLeafCell.append ( "dp_nts_x2" ) +LV_tsLeafCell.append ( "dp_ts_x4_buf" ) +LV_tsLeafCell.append ( "dp_ts_x4" ) +LV_tsLeafCell.append ( "dp_ts_x8_buf" ) +LV_tsLeafCell.append ( "dp_ts_x8" ) +LV_tsLeafCell.append ( "inv_x8" ) +LV_tsLeafCell.append ( "na2_x4" ) +LV_tsLeafCell.append ( "inv_x4" ) +LV_tsLeafCell.append ( "buf_x8" ) +LV_tsLeafCell.append ( "inv_x4" ) +LV_tsLeafCell.append ( "no2_x4" ) +LV_tsLeafCell.append ( "buf_x8" ) +LV_tsLeafCell.append ( "inv_x4" ) +LV_tsLeafCell.append ( "nxr2_x4" ) +LV_tsLeafCell.append ( "zero_x0" ) +LV_tsLeafCell.append ( "one_x0" ) +LV_tsLeafCell.append ( "dp_dff_x4_buf" ) +LV_tsLeafCell.append ( "dp_dff_x4" ) +LV_tsLeafCell.append ( "dp_dff_scan_x4_buf" ) +LV_tsLeafCell.append ( "dp_dff_scan_x4" ) +LV_tsLeafCell.append ( "dp_sff_x4_buf" ) +LV_tsLeafCell.append ( "dp_sff_x4" ) +LV_tsLeafCell.append ( "dp_sff_scan_x4_buf" ) +LV_tsLeafCell.append ( "dp_sff_scan_x4" ) + +########################### +## Functions Definitions ## +########################### + +################### +def set_tDrive ( LV_Function ) : + global LV_tDrive + global LV_ttDrive + + + if LV_Function == DPGEN_INV : LV_tDrive = LV_ttDrive[1] + elif LV_Function == DPGEN_BUFF : LV_tDrive = LV_ttDrive[2] + elif LV_Function == DPGEN_NAND2 : LV_tDrive = LV_ttDrive[3] + elif LV_Function == DPGEN_NAND3 : LV_tDrive = LV_ttDrive[3] + elif LV_Function == DPGEN_NAND4 : LV_tDrive = LV_ttDrive[3] + elif LV_Function == DPGEN_NOR2 : LV_tDrive = LV_ttDrive[3] + elif LV_Function == DPGEN_NOR3 : LV_tDrive = LV_ttDrive[3] + elif LV_Function == DPGEN_NOR4 : LV_tDrive = LV_ttDrive[3] + elif LV_Function == DPGEN_XNOR2 : LV_tDrive = LV_ttDrive[3] + elif LV_Function == DPGEN_XOR2 : LV_tDrive = LV_ttDrive[3] + elif LV_Function == DPGEN_AND2 : LV_tDrive = LV_ttDrive[4] + elif LV_Function == DPGEN_AND3 : LV_tDrive = LV_ttDrive[4] + elif LV_Function == DPGEN_AND4 : LV_tDrive = LV_ttDrive[4] + elif LV_Function == DPGEN_OR2 : LV_tDrive = LV_ttDrive[4] + elif LV_Function == DPGEN_OR3 : LV_tDrive = LV_ttDrive[4] + elif LV_Function == DPGEN_OR4 : LV_tDrive = LV_ttDrive[4] + elif LV_Function == DPGEN_MUX2 : LV_tDrive = LV_ttDrive[4] + elif LV_Function == DPGEN_BUSE : LV_tDrive = LV_ttDrive[5] + elif LV_Function == DPGEN_NMUX2 : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_NBUSE : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_NAND2MASK : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_NOR2MASK : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_XNOR2MASK : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_CONST : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_DFF : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_DFFT : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_SFF : LV_tDrive = LV_ttDrive[0] + elif LV_Function == DPGEN_SFFT : LV_tDrive = LV_ttDrive[0] + else : LV_tDrive = LV_ttDrive[0] + +###################### +def set_iLeafCell ( LV_Function ) : + global LV_iLeafCell + + LV_iLeafCell = 0 + + if LV_Function == DPGEN_SFFT : LV_iLeafCell += 64 + elif LV_Function == DPGEN_SFF : LV_iLeafCell += 62 + elif LV_Function == DPGEN_DFFT : LV_iLeafCell += 60 + elif LV_Function == DPGEN_DFF : LV_iLeafCell += 58 + elif LV_Function == DPGEN_CONST : LV_iLeafCell += 56 + elif LV_Function == DPGEN_XNOR2MASK : LV_iLeafCell += 53 + elif LV_Function == DPGEN_NOR2MASK : LV_iLeafCell += 50 + elif LV_Function == DPGEN_NAND2MASK : LV_iLeafCell += 47 + elif LV_Function == DPGEN_BUSE : LV_iLeafCell += 43 + elif LV_Function == DPGEN_NBUSE : LV_iLeafCell += 41 + elif LV_Function == DPGEN_MUX2 : LV_iLeafCell += 37 + elif LV_Function == DPGEN_NMUX2 : LV_iLeafCell += 35 + elif LV_Function == DPGEN_XOR2 : LV_iLeafCell += 33 + elif LV_Function == DPGEN_XNOR2 : LV_iLeafCell += 31 + elif LV_Function == DPGEN_OR4 : LV_iLeafCell += 29 + elif LV_Function == DPGEN_OR3 : LV_iLeafCell += 27 + elif LV_Function == DPGEN_OR2 : LV_iLeafCell += 25 + elif LV_Function == DPGEN_NOR4 : LV_iLeafCell += 23 + elif LV_Function == DPGEN_NOR3 : LV_iLeafCell += 21 + elif LV_Function == DPGEN_NOR2 : LV_iLeafCell += 19 + elif LV_Function == DPGEN_AND4 : LV_iLeafCell += 17 + elif LV_Function == DPGEN_AND3 : LV_iLeafCell += 15 + elif LV_Function == DPGEN_AND2 : LV_iLeafCell += 13 + elif LV_Function == DPGEN_NAND4 : LV_iLeafCell += 11 + elif LV_Function == DPGEN_NAND3 : LV_iLeafCell += 9 + elif LV_Function == DPGEN_NAND2 : LV_iLeafCell += 7 + elif LV_Function == DPGEN_BUFF : LV_iLeafCell += 4 + +################################## +def init_Generator ( aFunction ) : + global LV_Function + + # Set the function once and for all. + LV_Function = aFunction + + set_tDrive ( LV_Function ) + set_iLeafCell ( LV_Function ) + +################### +def has_Buffer ( LV_Function ) : + + if LV_Function in ( DPGEN_INV, DPGEN_BUFF, DPGEN_NAND2, DPGEN_NAND3, DPGEN_NAND4, DPGEN_AND2, DPGEN_AND3, DPGEN_AND4, DPGEN_NOR2, DPGEN_NOR3, DPGEN_NOR4, DPGEN_OR2, DPGEN_OR3, DPGEN_OR4, DPGEN_XNOR2, DPGEN_XOR2, DPGEN_CONST ) : + return 0 + + elif LV_Function in ( DPGEN_NMUX2, DPGEN_NBUSE, DPGEN_DFF, DPGEN_DFFT, DPGEN_SFF, DPGEN_SFFT, DPGEN_BUSE, DPGEN_MUX2, DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + return 1 + + return 0 + +################################ +def get_Model_Cell ( aiSlice ) : + global LV_Function + global LV_iLeafCell + global LV_tsLeafCell + global LV_macroDrive + global LV_xl + + index = ERROR_INDEX + + if LV_Function in ( DPGEN_INV, DPGEN_BUFF, DPGEN_NAND2, DPGEN_NAND3, DPGEN_NAND4, DPGEN_AND2, DPGEN_AND3, DPGEN_AND4, DPGEN_NOR2, DPGEN_NOR3, DPGEN_NOR4, DPGEN_OR2, DPGEN_OR3, DPGEN_OR4, DPGEN_XNOR2, DPGEN_XOR2 ) : + index = LV_iLeafCell + LV_macroDrive + + elif LV_Function in ( DPGEN_NMUX2, DPGEN_NBUSE, DPGEN_DFF, DPGEN_DFFT, DPGEN_SFF, DPGEN_SFFT ) : + index = LV_iLeafCell + 1 + + elif LV_Function in ( DPGEN_MUX2, DPGEN_BUSE ) : + index = LV_iLeafCell + ( LV_macroDrive * 2 ) + 1 # LV_macroDrive << 1 + + elif LV_Function in ( DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + index = LV_iLeafCell + 1 + LV_xl.getxlbit ( aiSlice ) + + elif LV_Function == DPGEN_CONST : + index = LV_iLeafCell + LV_xl.getxlbit ( aiSlice ) + + if ( index == ERROR_INDEX ) : return "bug_leaf" + + return LV_tsLeafCell[index] + +######################### +def get_Model_Buffer () : + global LV_Function + global LV_iLeafCell + global LV_tsLeafCell + global LV_macroDrive + + index = ERROR_INDEX + + if LV_Function in ( DPGEN_NMUX2, DPGEN_NBUSE, DPGEN_DFF, DPGEN_DFFT, DPGEN_SFF, DPGEN_SFFT, DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + index = LV_iLeafCell + + elif LV_Function in ( DPGEN_BUSE, DPGEN_MUX2 ) : + index = LV_iLeafCell + ( LV_macroDrive * 2 ) # LV_macroDrive << 1 + + if index == ERROR_INDEX : return "bug_buff" + + return LV_tsLeafCell[index] + + +################## +## DpgenRegular ## +################## +class DpgenRegular ( Model ) : + + ## Interface ## + ############### + def Interface ( self, LV_N, LV_Function ) : + + # Control terminals + if LV_Function in ( DPGEN_NMUX2, DPGEN_MUX2, DPGEN_NBUSE, DPGEN_BUSE, DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + self._cmd = SignalIn ( "cmd", 1 ) + + if LV_Function in ( DPGEN_DFF, DPGEN_DFFT, DPGEN_SFF, DPGEN_SFFT ) : + self._wen = SignalIn ( "wen", 1 ) + self._ck = SignalIn ( "ck", 1 ) + + if LV_Function in ( DPGEN_DFFT, DPGEN_SFFT ) : + self._scan = SignalIn ( "scan", 1 ) + self._scin = SignalIn ( "scin", 1 ) + + # Input data buses terminals + if LV_Function in ( DPGEN_OR4, DPGEN_NOR4, DPGEN_AND4, DPGEN_NAND4 ) : + self._i3 = SignalIn ( "i3", LV_N ) + self._i2 = SignalIn ( "i2", LV_N ) + self._i1 = SignalIn ( "i1", LV_N ) + self._i0 = SignalIn ( "i0", LV_N ) + + elif LV_Function in ( DPGEN_OR3, DPGEN_NOR3, DPGEN_AND3, DPGEN_NAND3 ) : + self._i2 = SignalIn ( "i2", LV_N ) + self._i1 = SignalIn ( "i1", LV_N ) + self._i0 = SignalIn ( "i0", LV_N ) + + elif LV_Function in ( DPGEN_MUX2, DPGEN_NMUX2, DPGEN_XOR2, DPGEN_XNOR2, DPGEN_OR2, DPGEN_NOR2, DPGEN_AND2, DPGEN_NAND2 ) : + self._i1 = SignalIn ( "i1", LV_N ) + self._i0 = SignalIn ( "i0", LV_N ) + + elif LV_Function in ( DPGEN_DFFT, DPGEN_DFF, DPGEN_SFFT, DPGEN_SFF, DPGEN_XNOR2MASK, DPGEN_NOR2MASK, DPGEN_NAND2MASK, DPGEN_BUSE, DPGEN_NBUSE, DPGEN_BUFF, DPGEN_INV ) : + self._i0 = SignalIn ( "i0", LV_N ) + + # Output data buses terminals + if LV_Function in ( DPGEN_CONST, DPGEN_MUX2, DPGEN_DFFT, DPGEN_DFF, DPGEN_SFFT, DPGEN_SFF, DPGEN_XOR2, DPGEN_OR4, DPGEN_OR3, DPGEN_OR2, DPGEN_AND4, DPGEN_AND3, DPGEN_AND2, DPGEN_BUFF ) : + self._q = SignalOut ( "q", LV_N ) + + elif LV_Function == DPGEN_BUSE: + self._q = TriState ( "q", LV_N ) + + elif LV_Function in ( DPGEN_INV, DPGEN_NAND2, DPGEN_NAND3, DPGEN_NAND4, DPGEN_NOR2, DPGEN_NOR3, DPGEN_NOR4, DPGEN_XNOR2, DPGEN_NMUX2, DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + self._nq = SignalOut ( "nq", LV_N ) + + elif LV_Function == DPGEN_NBUSE: + self._nq = TriState ( "nq", LV_N ) + + # Power terminals + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + + ## Netlist ## + ############# + def Netlist ( self, LV_N, LV_Function, *val ) : + global LV_drive, LV_macroDrive, LV_xl + + # Initializes for the requested generator + init_Generator ( LV_Function ) + + LV_drive = 1 + LV_macroDrive = 0 + + # Parses the optionals arguments + if LV_Function in ( DPGEN_INV, DPGEN_BUFF, DPGEN_NAND2, DPGEN_NAND3, DPGEN_NAND4, DPGEN_AND2, DPGEN_AND3, DPGEN_AND4, DPGEN_NOR2, DPGEN_NOR3, DPGEN_NOR4, DPGEN_OR2, DPGEN_OR3, DPGEN_OR4, DPGEN_XNOR2, DPGEN_XOR2, DPGEN_MUX2, DPGEN_BUSE ) : + LV_drive = val[0] + + elif LV_Function in ( DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK, DPGEN_CONST ) : + LV_xl = newxl () + LV_xl.atoxl ( val[0] ) + temp1 = LV_xl.xltovhdl() + LV_xl._size = LV_N + temp2 = LV_xl.xltovhdl() + + if temp1 != temp2 : + print "[Stratus Warning] : Due to its wrong size, the constant", temp1, "has been modified to :", temp2, ". Check if it's the value one wanted." + + # Check the drive argument + for iDrive in range ( MAX_TDRIVE ) : + if ( LV_tDrive[iDrive] and ( LV_tDrive[iDrive] == LV_drive ) ) : + LV_macroDrive = iDrive + break + + if iDrive == MAX_TDRIVE - 1 : iDrive += 1 + + if iDrive >= MAX_TDRIVE : + raise "\n[Stratus ERROR] Dpgen : Invalid drive value %ld.\n" % LV_drive + + # Internal signals + if LV_Function in ( DPGEN_NBUSE, DPGEN_BUSE ) : + enx = Signal ( "enx", 1 ) + nenx = Signal ( "nenx", 1 ) + elif LV_Function in ( DPGEN_DFF, DPGEN_SFF ) : + ckx = Signal ( "ckx", 1 ) + nckx = Signal ( "nckx", 1 ) + wenx = Signal ( "wenx", 1 ) + nwenx = Signal ( "nwenx", 1 ) + elif LV_Function in ( DPGEN_DFFT, DPGEN_SFFT ) : + ckx = Signal ( "ckx", 1 ) + nckx = Signal ( "nckx", 1 ) + wenx = Signal ( "wenx", 1 ) + nwenx = Signal ( "nwenx", 1 ) + scanx = Signal ( "scanx", 1 ) + nscanx = Signal ( "nscanx", 1 ) + scoutx = Signal ( "scoutx", 1 ) + elif LV_Function in ( DPGEN_MUX2, DPGEN_NMUX2 ) : + sel0 = Signal ( "sel0", 1 ) + sel1 = Signal ( "sel1", 1 ) + elif LV_Function == DPGEN_NAND2MASK : + ncmd = Signal ( "ncmd", 1 ) + elif LV_Function in ( DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + for iSlice in range ( LV_N ) : + if LV_xl.getxlbit ( iSlice ) : + bcmd = Signal ( "bcmd", 1 ) + break + + + # Loop for all the data slices + self.Cell = {} + + for iSlice in range ( LV_N ) : + sModel = get_Model_Cell ( iSlice ) + + if LV_Function == DPGEN_INV : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : self._i0[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function == DPGEN_BUFF : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : self._i0[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_NAND2, DPGEN_NOR2, DPGEN_XNOR2 ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0' : self._i0[iSlice] + , 'i1' : self._i1[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_AND2, DPGEN_OR2, DPGEN_XOR2 ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0' : self._i0[iSlice] + , 'i1' : self._i1[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_NAND3, DPGEN_NOR3 ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0' : self._i0[iSlice] + , 'i1' : self._i1[iSlice] + , 'i2' : self._i2[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_AND3, DPGEN_OR3 ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0' : self._i0[iSlice] + , 'i1' : self._i1[iSlice] + , 'i2' : self._i2[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_NAND4, DPGEN_NOR4 ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0' : self._i0[iSlice] + , 'i1' : self._i1[iSlice] + , 'i2' : self._i2[iSlice] + , 'i3' : self._i3[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_AND4, DPGEN_OR4 ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i0' : self._i0[iSlice] + , 'i1' : self._i1[iSlice] + , 'i2' : self._i2[iSlice] + , 'i3' : self._i3[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function == DPGEN_NMUX2 : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'sel0' : sel0 + , 'sel1' : sel1 + , 'i1' : self._i1[iSlice] + , 'i0' : self._i0[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function == DPGEN_MUX2 : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'sel0' : sel0 + , 'sel1' : sel1 + , 'i1' : self._i1[iSlice] + , 'i0' : self._i0[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function == DPGEN_NBUSE : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'enx' : enx + , 'nenx' : nenx + , 'i' : self._i0[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function == DPGEN_BUSE : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'enx' : enx + , 'nenx' : nenx + , 'i' : self._i0[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function == DPGEN_NAND2MASK : + if LV_xl.getxlbit ( iSlice ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : self._i0[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i1' : ncmd + , 'i0' : self._i0[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + if LV_xl.getxlbit ( iSlice ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i1' : bcmd + , 'i0' : self._i0[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : self._i0[iSlice] + , 'nq' : self._nq[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function == DPGEN_CONST : + if LV_xl.getxlbit ( iSlice ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'nq' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif ( LV_Function == DPGEN_DFF ) or ( LV_Function == DPGEN_SFF ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'ckx' : ckx + , 'nckx' : nckx + , 'wenx' : wenx + , 'nwenx' : nwenx + , 'i' : self._i0[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_DFFT, DPGEN_SFFT ) : + if iSlice == 0 : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'ckx' : ckx + , 'nckx' : nckx + , 'wenx' : wenx + , 'nwenx' : nwenx + , 'scanx' : scanx + , 'nscanx' : nscanx + , 'scin' : scoutx + , 'i' : self._i0[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + else : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'ckx' : ckx + , 'nckx' : nckx + , 'wenx' : wenx + , 'nwenx' : nwenx + , 'scanx' : scanx + , 'nscanx' : nscanx + , 'scin' : self._q[iSlice - 1] + , 'i' : self._i0[iSlice] + , 'q' : self._q[iSlice] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + iSlice += 1 # attention : difference entre les boucles en c et les boucles en python + + if has_Buffer ( LV_Function ) : + if iSlice % 2 : iSlice += 1 + + sModel = get_Model_Buffer () + + if LV_Function == DPGEN_NAND2MASK : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : self._cmd + , 'nq' : ncmd + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'i' : self._cmd + , 'q' : bcmd + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_NMUX2, DPGEN_MUX2 ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'sel' : self._cmd + , 'sel0' : sel0 + , 'sel1' : sel1 + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_NBUSE, DPGEN_BUSE ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'en' : self._cmd + , 'nenx' : nenx + , 'enx' : enx + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_DFF, DPGEN_SFF ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'ck' : self._ck + , 'wen' : self._wen + , 'ckx' : ckx + , 'nckx' : nckx + , 'wenx' : wenx + , 'nwenx' : nwenx + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + elif LV_Function in ( DPGEN_DFFT, DPGEN_SFFT ) : + self.Cell[iSlice] = Inst ( sModel + , "cell_%ld" % iSlice + , map = { 'ck' : self._ck + , 'wen' : self._wen + , 'scan' : self._scan + , 'ckx' : ckx + , 'nckx' : nckx + , 'wenx' : wenx + , 'nwenx' : nwenx + , 'scanx' : scanx + , 'nscanx' : nscanx + , 'scin' : self._scin + , 'scout' : scoutx + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ## Layout ## + ############ + def Layout ( self, LV_N, LV_Function ) : + + # Loop for all the data slices + for iSlice in range ( LV_N ) : + Place ( self.Cell[iSlice] + , slice_to_sym ( iSlice ) + , XY ( 0, slice_to_y ( iSlice ) ) + ) + + iSlice += 1 # attention : difference entre les boucles en c et les boucles en python + + # Add the buffer cell + if has_Buffer ( LV_Function ) : + if iSlice % 2 : iSlice += 1 + + Place ( self.Cell[iSlice] + , slice_to_sym ( iSlice ) + , XY ( 0, slice_to_y ( iSlice ) ) + ) + + + ## VBE ## + ######### + def Vbe ( self, LV_N, LV_flags, LV_Function ) : + + global file + + fileName = self._name + ".vbe" + + file = open ( fileName, "w+" ) + + sBusWide = VHDL_BUS_WIDE ( LV_N - 1, 0, LV_N, LV_flags ) + + ## Entity Description ## + file.write ( "\nENTITY %s IS\n PORT (\n" % self._name ) + + ## Controls Terminals ## + if LV_Function in ( DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK, DPGEN_BUSE, DPGEN_NBUSE, DPGEN_MUX2, DPGEN_NMUX2 ) : + file.write ( "%14s : in BIT;\n" % "cmd") + + if LV_Function in ( DPGEN_DFF, DPGEN_DFFT, DPGEN_SFF, DPGEN_SFFT ) : + file.write ( "%14s : in BIT;\n" % "wen" ) + file.write ( "%14s : in BIT;\n" % "ck" ) + + if LV_Function in ( DPGEN_DFFT, DPGEN_SFFT ) : + file.write ( "%14s : in BIT;\n" % "scan") + file.write ( "%14s : in BIT;\n" % "scin") + + ## Input data buses terminals ## + if LV_Function in ( DPGEN_NAND4, DPGEN_AND4, DPGEN_NOR4, DPGEN_OR4 ) : + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i3", sBusWide ) ) + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i2", sBusWide ) ) + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i1", sBusWide ) ) + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i0", sBusWide ) ) + + elif LV_Function in (DPGEN_NAND3, DPGEN_OR3, DPGEN_AND3, DPGEN_NOR3 ) : + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i2", sBusWide ) ) + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i1", sBusWide ) ) + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i0", sBusWide ) ) + + elif LV_Function in ( DPGEN_NAND2, DPGEN_AND2, DPGEN_NOR2, DPGEN_OR2, DPGEN_XNOR2, DPGEN_XOR2, DPGEN_NMUX2, DPGEN_MUX2 ) : + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i1", sBusWide ) ) + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i0", sBusWide ) ) + + elif LV_Function in ( DPGEN_INV, DPGEN_BUFF, DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK, DPGEN_NBUSE, DPGEN_BUSE, DPGEN_DFF, DPGEN_DFFT, DPGEN_SFF, DPGEN_SFFT ) : + file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "i0", sBusWide ) ) + + ## Output data buses terminals ## + if LV_Function in ( DPGEN_NAND4, DPGEN_NOR4, DPGEN_NAND3, DPGEN_NOR3, DPGEN_NAND2, DPGEN_NOR2, DPGEN_XNOR2, DPGEN_NMUX2, DPGEN_INV, DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : + file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "nq", sBusWide ) ) + + elif LV_Function == DPGEN_NBUSE : + file.write ( "%14s : out MUX_VECTOR %s BUS;\n" % ( "nq", sBusWide ) ) + + elif LV_Function in ( DPGEN_AND2, DPGEN_AND3, DPGEN_AND4, DPGEN_OR2, DPGEN_OR3, DPGEN_OR4, DPGEN_XOR2, DPGEN_MUX2, DPGEN_BUFF, DPGEN_CONST, DPGEN_DFF, DPGEN_DFFT, DPGEN_SFF, DPGEN_SFFT ) : + file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "q", sBusWide ) ) + + elif LV_Function == DPGEN_BUSE : + file.write ( "%14s : out MUX_VECTOR %s BUS;\n" % ( "q", sBusWide ) ) + + ## Power supplies terminals ## + file.write ( "%14s : in BIT;\n" % "vdd") + file.write ( "%14s : in BIT\n" % "vss") + + ## End of entity description ## + file.write ( " );\nEND %s;\n\n\n" % self._name ) + + ## Architecture description ## + file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % self._name ) + + ## Signals ## + if LV_Function in ( DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK, DPGEN_NMUX2 ) : + file.write ( " SIGNAL %20s : BIT_VECTOR %s;\n" % ( "q", sBusWide ) ) + + elif LV_Function in ( DPGEN_DFFT, DPGEN_SFFT ) : + file.write ( " SIGNAL %20s : BIT_VECTOR %s;\n" % ( "d_test", sBusWide ) ) + file.write ( " SIGNAL %20s : BIT_VECTOR %s;\n" % ( "d_wen", sBusWide ) ) + file.write ( " SIGNAL %20s : REG_VECTOR %s REGISTER;\n" % ( "ff", sBusWide ) ) + + elif LV_Function in ( DPGEN_DFF, DPGEN_SFF ) : + file.write ( " SIGNAL %20s : BIT_VECTOR %s;\n" % ( "d_wen", sBusWide ) ) + file.write ( " SIGNAL %20s : REG_VECTOR %s REGISTER;\n" % ( "ff", sBusWide ) ) + + ## Behavior ## + file.write ( "\nBEGIN\n\n" ) + + if LV_Function in ( DPGEN_NAND4, DPGEN_AND4, DPGEN_NOR4, DPGEN_OR4, DPGEN_NAND3, DPGEN_OR3, DPGEN_AND3, DPGEN_NOR3, DPGEN_NAND2, DPGEN_AND2, DPGEN_NOR2, DPGEN_OR2, DPGEN_XNOR2, DPGEN_XOR2, DPGEN_INV, DPGEN_BUFF ) : self.VHDL_boolean ( LV_Function ) + + elif LV_Function in ( DPGEN_NAND2MASK, DPGEN_NOR2MASK, DPGEN_XNOR2MASK ) : self.VHDL_mask ( LV_Function ) + + elif LV_Function in ( DPGEN_NMUX2, DPGEN_MUX2 ) : self.VHDL_mux ( LV_Function ) + + elif LV_Function in ( DPGEN_BUSE, DPGEN_NBUSE ) : self.VHDL_buse ( LV_Function ) + + elif LV_Function == DPGEN_CONST : self.VHDL_const () + + elif LV_Function in ( DPGEN_DFF, DPGEN_DFFT, DPGEN_SFF, DPGEN_SFFT ) : self.VHDL_ff ( LV_Function, LV_N, LV_flags ) + + ## Assert ## + file.write ( " ASSERT (vdd = '1')\n" ) + file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % self._name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + file.write ( " ASSERT (vss = '0')\n" ) + file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % self._name ) + file.write ( " SEVERITY WARNING;\n\n" ) + + ## End of behavioral view ## + file.write ( "END VBE;\n" ) + + file.close () + + + ## VHDL_boolean ## + ################## + def VHDL_boolean ( self, LV_Function ) : + global file + + if LV_Function == DPGEN_INV : file.write ( " nq <= not i0;\n\n" ) + elif LV_Function == DPGEN_BUFF : file.write ( " q <= i0;\n\n" ) + elif LV_Function == DPGEN_NAND2 : file.write ( " nq <= not (i0 and i1);\n\n" ) + elif LV_Function == DPGEN_AND2 : file.write ( " q <= (i0 and i1);\n\n" ) + elif LV_Function == DPGEN_NOR2 : file.write ( " nq <= not (i0 or i1);\n\n" ) + elif LV_Function == DPGEN_OR2 : file.write ( " q <= (i0 or i1);\n\n" ) + elif LV_Function == DPGEN_XNOR2 : file.write ( " nq <= not (i0 xor i1);\n\n" ) + elif LV_Function == DPGEN_XOR2 : file.write ( " q <= (i0 xor i1);\n\n" ) + elif LV_Function == DPGEN_NOR3 : file.write ( " nq <= not (i0 or i1 or i2);\n\n" ) + elif LV_Function == DPGEN_OR3 : file.write ( " q <= (i0 or i1 or i2);\n\n" ) + elif LV_Function == DPGEN_NAND3 : file.write ( " nq <= not (i0 and i1 and i2);\n\n" ) + elif LV_Function == DPGEN_AND3 : file.write ( " q <= (i0 and i1 and i2);\n\n" ) + elif LV_Function == DPGEN_NAND4 : file.write ( " nq <= not (i0 and i1 and i2 and i3);\n\n" ) + elif LV_Function == DPGEN_AND4 : file.write ( " q <= (i0 and i1 and i2 and i3);\n\n" ) + elif LV_Function == DPGEN_NOR4 : file.write ( " nq <= not (i0 or i1 or i2 or i3);\n\n" ) + elif LV_Function == DPGEN_OR4 : file.write ( " q <= (i0 or i1 or i2 or i3);\n\n" ) + + ## VHDL_mask ## + ############### + def VHDL_mask ( self, LV_Function ) : + global LV_xl + + global file + + file.write ( " WITH cmd SELECT\n" ) + file.write ( " q <= i0 WHEN \'0\',\n" ) + + if LV_Function == DPGEN_NAND2MASK : + file.write ( " (i0 and %s) WHEN \'1\';\n" % LV_xl.xltovhdl ( ) ) + + elif LV_Function == DPGEN_NOR2MASK : + file.write ( " (i0 or %s) WHEN \'1\';\n" % LV_xl.xltovhdl ( ) ) + + elif LV_Function == DPGEN_XNOR2MASK : + file.write ( " (i0 xor %s) WHEN \'1\';\n" % LV_xl.xltovhdl ( ) ) + + file.write ( "\n nq <= not q;\n\n" ) + + ## VHDL_const ## + ################ + def VHDL_const ( self ) : + global LV_xl + + global file + + file.write ( " q <= %s;\n\n" % LV_xl.xltovhdl ( ) ) + + ## VHDL_mux ## + ############## + def VHDL_mux ( self, LV_Function ) : + + global file + + if LV_Function in ( DPGEN_NMUX2, DPGEN_MUX2 ) : + file.write ( " WITH cmd SELECT\n" ) + file.write ( " q <= i0 WHEN \'0\',\n" ) + file.write ( " i1 WHEN \'1\';\n" ) + + if LV_Function == DPGEN_NMUX2 : + file.write ( "\n nq <= not q;\n" ) + + file.write ( "\n" ) + + ## VHDL_buse ## + ############### + def VHDL_buse ( self, LV_Function ) : + + global file + + file.write ( " label_buse:BLOCK(cmd = '1')\n" ) + file.write ( " BEGIN\n" ) + + if LV_Function == DPGEN_NBUSE : + file.write ( " nq <= GUARDED not i0;\n" ) + + elif LV_Function == DPGEN_BUSE : + file.write ( " q <= GUARDED i0;\n" ) + + file.write ( " END BLOCK label_buse;\n\n" ) + + ## VHDL_ff () ## + ################ + def VHDL_ff ( self, LV_Function, LV_N, LV_flags ) : + + global file + + sBusWide = VHDL_BUS_WIDE ( LV_N - 2, 0, LV_N, LV_flags ) + + dwrite = "d_wen" + + if LV_Function in ( DPGEN_DFFT, DPGEN_SFFT ) : + file.write ( " WITH scan SELECT\n" ) + file.write ( " d_test <= d_wen WHEN \'0\',\n" ) + file.write ( " q %s & scin WHEN \'1\';\n\n" % sBusWide ) + + dwrite = "d_test"; + + file.write ( " WITH wen SELECT\n" ) + file.write ( " d_wen <= q WHEN \'0\',\n" ) + file.write ( " i0 WHEN \'1\';\n\n" ) + + + elif LV_Function in ( DPGEN_DFF, DPGEN_SFF ) : + file.write ( " WITH wen SELECT\n" ) + file.write ( " d_wen <= q WHEN \'0\',\n" ) + file.write ( " i0 WHEN \'1\';\n\n" ) + + + file.write ( " label_ff:BLOCK ((ck and not (ck'STABLE)) = \'1\')\n" ) + file.write ( " BEGIN\n" ) + file.write ( " ff <= GUARDED %s;\n" % dwrite ) + file.write ( " END BLOCK label_ff;\n\n" ) + + file.write ( " q <= ff;\n\n" ) + + +########################################################################## + +## AND2 ## +class DpgenAnd2 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 2 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_AND2 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_AND2, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_AND2 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_AND2 ) + +## AND3 ## +class DpgenAnd3 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 2 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_AND3 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_AND3, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_AND3 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_AND3 ) + +## AND4 ## +class DpgenAnd4 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 2 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_AND4 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_AND4, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_AND4) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_AND4 ) + +## BUFF ## +class DpgenBuff ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 2 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_BUFF ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_BUFF, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_BUFF ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self,self._param['nbit'], self._param['flags'], DPGEN_BUFF ) + +## BUSE ## +class DpgenBuse ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 4 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_BUSE ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_BUSE, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_BUSE ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_BUSE ) + +## CONST ## +class DpgenConst ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_CONST ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_CONST, self._param['const'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_CONST ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_CONST ) + +## DFF ## +class DpgenDff ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_DFF ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_DFF, 0 ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_DFF ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_DFF ) + +## DFFT ## +class DpgenDfft ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_DFFT ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_DFFT, 0 ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_DFFT ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_DFFT ) + +## INV ## +class DpgenInv ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_INV ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_INV, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_INV ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_INV ) + +## MUX2 ## +class DpgenMux2 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 2 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_MUX2 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_MUX2, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_MUX2 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_MUX2 ) + +## NAND2 ## +class DpgenNand2 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NAND2 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NAND2, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NAND2 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NAND2 ) + +## NAND2MASK ## +class DpgenNand2mask ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NAND2MASK ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NAND2MASK, self._param['const'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NAND2MASK ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NAND2MASK ) + +## NAND3 ## +class DpgenNand3 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NAND3 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NAND3, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NAND3 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NAND3 ) + +## NAND4 ## +class DpgenNand4 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NAND4 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NAND4, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NAND4 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NAND4 ) + +## NBUSE ## +class DpgenNbuse ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NBUSE ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NBUSE ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NBUSE ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NBUSE ) + +## NMUX2 ## +class DpgenNmux2 ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NMUX2 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NMUX2 ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NMUX2 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NMUX2 ) + +## NOR2 ## +class DpgenNor2 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NOR2 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NOR2, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NOR2 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NOR2 ) + +## NOR2MASK ## +class DpgenNor2mask ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NOR2MASK ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NOR2MASK, self._param['const'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NOR2MASK ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NOR2MASK ) + +## NOR3 ## +class DpgenNor3 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NOR3 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NOR3, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NOR3 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NOR3 ) + +## NOR4 ## +class DpgenNor4 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_NOR4 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_NOR4, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_NOR4 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_NOR4 ) + +## OR2 ## +class DpgenOr2 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 2 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_OR2 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_OR2, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_OR2 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_OR2 ) + +## OR3 ## +class DpgenOr3 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 2 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_OR3 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_OR3, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_OR3 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_OR3 ) + +## OR4 ## +class DpgenOr4 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 2 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_OR4 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_OR4, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_OR4 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_OR4 ) + +## SFF ## +class DpgenSff ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_SFF ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_SFF, 0 ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_SFF ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_SFF ) + +## SFFT ## +class DpgenSfft ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_SFFT ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_SFFT, 0 ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_SFFT ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_SFFT ) + +## XNOR2 ## +class DpgenXnor2 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_XNOR2 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_XNOR2, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_XNOR2 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_XNOR2 ) + +## XNOR2MASK ## +class DpgenXnor2mask ( DpgenRegular ) : + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_XNOR2MASK ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_XNOR2MASK, self._param['const'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_XNOR2MASK ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_XNOR2MASK ) + +## XOR2 ## +class DpgenXor2 ( DpgenRegular ) : + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + if 'drive' not in param : self._param['drive'] = 1 + + def Interface ( self ) : + DpgenRegular.Interface ( self, self._param['nbit'], DPGEN_XOR2 ) + + def Netlist ( self ) : + DpgenRegular.Netlist ( self, self._param['nbit'], DPGEN_XOR2, self._param['drive'] ) + + def Layout ( self ) : + DpgenRegular.Layout ( self, self._param['nbit'], DPGEN_XOR2 ) + + def Vbe ( self ) : + DpgenRegular.Vbe ( self, self._param['nbit'], self._param['flags'], DPGEN_XOR2 ) diff --git a/stratus1/src/dpgen/dpgen_Shifter.py b/stratus1/src/dpgen/dpgen_Shifter.py new file mode 100644 index 00000000..709b5293 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_Shifter.py @@ -0,0 +1,263 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_Shifter.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class DpgenShifter ( Model ) : + + ## Interface ## + ############### + def Interface ( self ) : + global Slices + global BitIndex + + self._nbit = self._param['nbit'] + + Slices = ln2p ( self._nbit ) + + self._op = SignalIn ( "op", 2 ) + self._shamt = SignalIn ( "shamt", Slices ) + + self._i = SignalIn ( "i", self._nbit ) + + self._o = SignalOut ( "o", self._nbit ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + + ## Netlist ## + ############# + def Netlist ( self ) : + global SliceIndex + + AndIndex = 0 + + # Signals + MuxOutput = Signal ( "muxoutput", self._nbit * Slices + self._nbit ) + + c0 = Signal ( "c0", Slices ) + c1 = Signal ( "c1", Slices ) + + msb = Signal ( "msb", 1 ) + + + # Arithmetic or input extension + self.A0 = Inst ( "a2_x2" + , "a_0" + , map = { 'i0' : self._i[self._nbit-1] + , 'i1' : self._op[1] + , 'q' : msb + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + + # Normalizing the input signals names + for BitIndex in range ( self._nbit ) : self._i[BitIndex].Alias ( MuxOutput[BitIndex] ) + + self.M = {} + + # Connecting the mux matrix + for SliceIndex in range ( Slices ) : + for BitIndex in range ( self._nbit ) : + + LeftIndex = BitIndex - ( 1 << SliceIndex ) + RightIndex = BitIndex + ( 1 << SliceIndex ) + + if LeftIndex >= 0 : + if RightIndex < self._nbit : + self.M[SliceIndex*self._nbit+BitIndex] = Inst ( "mx3_x2" + , "m_%d" % ( SliceIndex * self._nbit + BitIndex ) + , map = { 'cmd0' : c0[SliceIndex] + , 'cmd1' : c1[SliceIndex] + , 'i0' : MuxOutput[SliceIndex * self._nbit + LeftIndex] + , 'i1' : MuxOutput[SliceIndex * self._nbit + BitIndex] + , 'i2' : MuxOutput[SliceIndex * self._nbit + RightIndex] + , 'q' : MuxOutput[( SliceIndex + 1 ) * self._nbit + BitIndex] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + else : + self.M[SliceIndex*self._nbit+BitIndex] = Inst ( "mx3_x2" + , "m_%d" % ( SliceIndex * self._nbit + BitIndex ) + , map = { 'cmd0' : c0[SliceIndex] + , 'cmd1' : c1[SliceIndex] + , 'i0' : MuxOutput[SliceIndex * self._nbit + LeftIndex] + , 'i1' : MuxOutput[SliceIndex * self._nbit + BitIndex] + , 'i2' : msb + , 'q' : MuxOutput[( SliceIndex + 1 ) * self._nbit + BitIndex] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + else : + if RightIndex < self._nbit : + self.M[SliceIndex*self._nbit+BitIndex] = Inst ( "mx3_x2" + , "m_%d" % ( SliceIndex * self._nbit + BitIndex ) + , map = { 'cmd0' : c0[SliceIndex] + , 'cmd1' : c1[SliceIndex] + , 'i0' : self._op[0] + , 'i1' : MuxOutput[SliceIndex * self._nbit + BitIndex] + , 'i2' : MuxOutput[SliceIndex * self._nbit + RightIndex] + , 'q' : MuxOutput[( SliceIndex + 1 ) * self._nbit + BitIndex] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + else : + self.M[SliceIndex*self._nbit+BitIndex] = Inst ( "mx3_x2" + , "m_%d" % ( SliceIndex * self._nbit + BitIndex ) + , map = { 'cmd0' : c0[SliceIndex] + , 'cmd1' : c1[SliceIndex] + , 'i0' : self._op[0] + , 'i1' : MuxOutput[SliceIndex * self._nbit + BitIndex] + , 'i2' : msb + , 'q' : MuxOutput[( SliceIndex + 1 ) * self._nbit + BitIndex] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + # Normalizing the output signals names + for BitIndex in range ( self._nbit ) : self._o[BitIndex] <= MuxOutput[Slices * self._nbit + BitIndex] + + # Building the control signals + if self._nbit < 16 : Model = "inv_x2" + elif self._nbit < 32 : Model = "inv_x4" + else : Model = "inv_x8" + + self.I = {} + self.O = {} + + for SliceIndex in range ( Slices ) : + self.I[SliceIndex] = Inst ( Model + , "i_%d" % SliceIndex + , map = { 'i' : self._shamt[SliceIndex] + , 'nq' : c1[SliceIndex] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + self.O[SliceIndex] = Inst ( "o2_x2" + , "o_%d" % SliceIndex + , map = { 'i0' : c1[SliceIndex] + , 'i1' : self._op[0] + , 'q' : c0[SliceIndex] + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + + ########## Layout ########## + ############################ + def Layout ( self ) : + global SliceIndex + global BitIndex + + Slices = ln2p ( self._nbit ) + + if self._nbit & 1 : + sym = SYM_Y + mys = NOSYM + else : + sym = NOSYM + mys = SYM_Y + + BitIndex = self._nbit - 1 + SliceIndex = 0 + + Place ( self.M[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + , XY ( 0, 0 ) + ) + + for SliceIndex in range ( 1, Slices ) : + PlaceRight ( self.M[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + ) + + for SliceIndex in range ( Slices ) : + SetRefIns ( self.M[SliceIndex * self._nbit + self._nbit - 1] ) + + for BitIndex in range ( self._nbit - 2, -1, -1 ) : + PlaceBottom ( self.M[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + ) + + + BitIndex = self._nbit # Upper line, this is necessary for the computation of the symetry + SliceIndex = 0 + + SetRefIns ( self.M[SliceIndex * self._nbit + self._nbit - 1] ) + + PlaceTop ( self.A0 + , SYM ( BitIndex, sym, mys ) + ) + + for SliceIndex in range ( Slices ) : + if SliceIndex == 0 : SetRefIns ( self.A0 ) + + + PlaceRight ( self.I[SliceIndex] + , SYM ( BitIndex, sym, mys ) + ) + + PlaceRight ( self.O[SliceIndex] + , SYM ( BitIndex, sym, mys ) + ) + + ## VBE ## + ######### + def Vbe ( self ) : + print "vbe of DpgenShifter not implemented" diff --git a/stratus1/src/dpgen/dpgen_Shrot.py b/stratus1/src/dpgen/dpgen_Shrot.py new file mode 100644 index 00000000..4b0b6050 --- /dev/null +++ b/stratus1/src/dpgen/dpgen_Shrot.py @@ -0,0 +1,343 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./dpgen_Shrot.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class DpgenShrot ( Model ) : + + ## Interface ## + ############### + def Interface ( self ) : + global Slices + global AndIndex + + self._nbit = self._param['nbit'] + + Slices = ln2p ( self._nbit ) + + self._op = SignalIn ( "op", 3 ) + self._shamt = SignalIn ( "shamt", Slices ) + + self._i = SignalIn ( "i", self._nbit ) + self._o = SignalOut ( "o", self._nbit ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + + ## Netlist ## + ############# + def Netlist ( self ) : + global Slices + + AndIndex = 0 + + # Signals + MuxOutput = Signal ( "muxoutput", self._nbit * Slices + self._nbit ) + + c0 = Signal ( "c0", Slices ) + c1 = Signal ( "c1", Slices ) + + msb = Signal ( "msb", 1 ) + op2b = Signal ( "op2b", 1 ) + + x = Signal ( "x", Slices * self._nbit ) + + MuxInput0 = Signal ( "muxinput0" ) + MuxInput2 = Signal ( "muxinput2" ) + + self.I = {} + self.A3 = {} + self.A = {} + self.OA = {} + self.O = {} + self.M = {} + self.Tie = {} + + + # Arithmetic or input extension + self.I[Slices] = Inst ( "inv_x2" + , "i_%d" % Slices + , map = { 'i' : self._op[2] + , 'nq' : op2b + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.A3[Slices] = Inst ( "a3_x2" + , "a3_%d" % Slices + , map = { 'i0' : self._i[self._nbit-1] + , 'i1' : op2b + , 'i2' : self._op[1] + , 'q' : msb + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + # Normalizing the input signals names + for BitIndex in range ( self._nbit ) : self._i[BitIndex].Alias ( MuxOutput[BitIndex] ) + + # Connecting the mux matrix + for SliceIndex in range ( Slices ) : + for BitIndex in range ( self._nbit ) : + + LeftIndex = BitIndex - ( 1 << SliceIndex ) + RightIndex = BitIndex + ( 1 << SliceIndex ) + + if LeftIndex >= 0 : +# MuxOutput[SliceIndex * self._nbit + LeftIndex].Alias ( MuxInput0 ) + MuxInput0 = MuxOutput[SliceIndex * self._nbit + LeftIndex] + else : +# x[AndIndex].Alias ( MuxInput0 ) + MuxInput0 = x[AndIndex] + + self.A[SliceIndex*self._nbit+BitIndex]= Inst ( "a2_x2" + , "a_%d" % ( SliceIndex * self._nbit + BitIndex ) + , map = { 'i0' : self._op[2] + , 'i1' : MuxOutput[SliceIndex * self._nbit + self._nbit + LeftIndex] + , 'q' : x[AndIndex] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + AndIndex += 1 + + if RightIndex < self._nbit: +# MuxOutput[SliceIndex * self._nbit + RightIndex].Alias ( MuxInput2 ) + MuxInput2 = MuxOutput[SliceIndex * self._nbit + RightIndex] + else : +# x[AndIndex].Alias ( MuxInput2 ) + MuxInput2 = x[AndIndex] + + self.OA[SliceIndex*self._nbit+BitIndex] = Inst ( "oa22_x4" + , "oa_%d" % ( SliceIndex * self._nbit + BitIndex ) + , map = { 'i0' : self._op[2] + , 'i1' : MuxOutput[SliceIndex * self._nbit + RightIndex - self._nbit] + , 'i2' : msb + , 'q' : x[AndIndex] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + AndIndex += 1 + + self.M[SliceIndex*self._nbit+BitIndex] = Inst ( "mx3_x2" + , "m_%d" % ( SliceIndex * self._nbit + BitIndex ) + , map = { 'cmd0' : c0[SliceIndex] + , 'cmd1' : c1[SliceIndex] + , 'i0' : MuxInput0 + , 'i1' : MuxOutput[SliceIndex * self._nbit + BitIndex] + , 'i2' : MuxInput2 + , 'q' : MuxOutput[( SliceIndex + 1 ) * self._nbit + BitIndex] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + # Normalizing the output signals names + for BitIndex in range ( self._nbit ) : + MuxOutput[Slices * self._nbit + BitIndex]._temp = 1 + self._o[BitIndex] <= MuxOutput[Slices * self._nbit + BitIndex] + + # Building the control signals + for SliceIndex in range ( Slices ) : + self.I[SliceIndex] = Inst ( "inv_x2" + , "i_%d" % SliceIndex + , map = { 'i' : self._shamt[SliceIndex] + , 'nq' : c1[SliceIndex] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + self.O[SliceIndex]= Inst ( "o2_x2" + , "o_%d" % SliceIndex + , map = { 'i0' : c1[SliceIndex] + , 'i1' : self._op[0] + , 'q' : c0[SliceIndex] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + for SliceIndex in range ( Slices ) : + for BitIndex in range ( self._nbit - 1, -1, -1 ) : + l = 0 + r = 0 + LeftIndex = BitIndex - ( 1 << SliceIndex ) + RightIndex = BitIndex + ( 1 << SliceIndex ) + + if RightIndex >= self._nbit : r = 1 + if LeftIndex < 0 : l = 1 + + if l == 0 and r == 0 : + self.Tie[SliceIndex*self._nbit+BitIndex] = Inst ( "tie_x0" + , "tie_%d" % ( SliceIndex * self._nbit + BitIndex ) + , map = { 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + + ########## Layout ########## + ############################ + def Layout ( self ) : + + Slices = ln2p ( self._nbit ) + + if self._nbit & 1 : + sym = SYM_Y + mys = NOSYM + else : + sym = NOSYM + mys = SYM_Y + + BitIndex = self._nbit - 1 + SliceIndex = 0 + + Place ( self.OA[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + , XY ( 0, 0 ) + ) + PlaceRight ( self.M[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + ) + + for SliceIndex in range ( 1, Slices ) : + PlaceRight ( self.OA[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + ) + + PlaceRight ( self.M[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + ) + + for SliceIndex in range ( Slices ) : + SetXYIns ( self.OA[SliceIndex * self._nbit + self._nbit - 1] ) + + for BitIndex in range ( self._nbit - 1, -1, -1 ) : + l = 0 + r = 0 + LeftIndex = BitIndex - ( 1 << SliceIndex ) + RightIndex = BitIndex + ( 1 << SliceIndex ) + + if RightIndex >= self._nbit : + if BitIndex != ( self._nbit - 1 ) : + PlaceBottom ( self.OA[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + ) + + r = 1 + + if LeftIndex < 0 : + if r == 1 : + PlaceRight ( self.A[SliceIndex * self._nbit + BitIndex ] + , SYM ( BitIndex, sym, mys ) + ) + SetXYIns ( self.OA[SliceIndex * self._nbit + BitIndex] ) + + else : + PlaceBottom ( self.A[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + ) + + l = 1 + + if l == 0 and r == 0 : + PlaceBottom ( self.Tie[SliceIndex * self._nbit + BitIndex] + , NOSYM + ) + + SetRefIns ( self.M[SliceIndex * self._nbit + self._nbit - 1] ) + + for BitIndex in range ( self._nbit - 2, -1, -1 ) : + PlaceBottom ( self.M[SliceIndex * self._nbit + BitIndex] + , SYM ( BitIndex, sym, mys ) + ) + + + BitIndex = self._nbit # Upper line, this is necessary for the computation of the symetry + SliceIndex = 0 + + SetRefIns ( self.OA[SliceIndex * self._nbit + self._nbit - 1] ) + + PlaceTop ( self.I[Slices] + , SYM ( BitIndex, sym, mys ) + ) + PlaceRight ( self.A3[Slices] + , SYM ( BitIndex, sym, mys ) + ) + + for SliceIndex in range ( Slices ) : + if SliceIndex > 0 : + SetRefIns ( self.OA[SliceIndex * self._nbit + self._nbit - 1] ) + + if SliceIndex == 0: + PlaceRight ( self.I[SliceIndex] + , SYM ( BitIndex, sym, mys ) + ) + else : + PlaceTop ( self.I[SliceIndex] + , SYM ( BitIndex, sym, mys ) + ) + + PlaceRight ( self.O[SliceIndex] + , SYM ( BitIndex, sym, mys ) + ) + + ## VBE ## + ######### + def Vbe ( self ) : + print "vbe of DpgenShrot not implemented" diff --git a/stratus1/src/lib/fulladder.vst b/stratus1/src/lib/fulladder.vst new file mode 100644 index 00000000..c01a1ef0 --- /dev/null +++ b/stratus1/src/lib/fulladder.vst @@ -0,0 +1,102 @@ +-- This file is part of the Coriolis Project. +-- Copyright (C) Laboratoire LIP6 - Departement ASIM +-- Universite Pierre et Marie Curie +-- +-- Main contributors : +-- Christophe Alexandre +-- Sophie Belloeil +-- Hugo Clement +-- Jean-Paul Chaput +-- Damien Dupuis +-- Christian Masson +-- Marek Sroka +-- +-- The Coriolis Project is free software; you can redistribute it +-- and/or modify it under the terms of the GNU General Public License +-- as published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. +-- +-- The Coriolis Project is distributed in the hope that it will be +-- useful, but WITHOUT ANY WARRANTY; without even the implied warranty +-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with the Coriolis Project; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +-- USA +-- +-- License-Tag +-- Authors-Tag +-- =================================================================== +-- +-- x-----------------------------------------------------------------x +-- | | +-- | C O R I O L I S | +-- | S t r a t u s - Netlists Description | +-- | | +-- | Author : Sophie BELLOEIL | +-- | E-mail : Sophie.Belloeil@asim.lip6.fr | +-- | =============================================================== | +-- | Vst Module : "./fulladder.vst" | +-- | *************************************************************** | +-- | U p d a t e s | +-- | | +-- x-----------------------------------------------------------------x + + +entity fulladder is + port ( + a : in bit; + b : in bit; + cin : in bit; + sout : out bit; + cout : out bit; + vdd : in bit; + vss : in bit + ); +end fulladder; + +architecture structural of fulladder is +component fulladder_x2 + port ( + a1 : in bit; + a2 : in bit; + a3 : in bit; + a4 : in bit; + b1 : in bit; + b2 : in bit; + b3 : in bit; + b4 : in bit; + cin1 : in bit; + cin2 : in bit; + cin3 : in bit; + sout : out bit; + cout : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +begin + +cell : fulladder_x2 + port map ( + a1 => a, + a2 => a, + a3 => a, + a4 => a, + b1 => b, + b2 => b, + b3 => b, + b4 => b, + cin1 => cin, + cin2 => cin, + cin3 => cin, + sout => sout, + cout => cout, + vdd => vdd, + vss => vss + ); + +end structural; diff --git a/stratus1/src/modules/CMakeLists.txt b/stratus1/src/modules/CMakeLists.txt new file mode 100644 index 00000000..fbd5d3b8 --- /dev/null +++ b/stratus1/src/modules/CMakeLists.txt @@ -0,0 +1,2 @@ + + add_subdirectory ( patterns ) diff --git a/stratus1/src/modules/patterns/CMakeLists.txt b/stratus1/src/modules/patterns/CMakeLists.txt new file mode 100644 index 00000000..874a7182 --- /dev/null +++ b/stratus1/src/modules/patterns/CMakeLists.txt @@ -0,0 +1,9 @@ + + set ( pysources ${CMAKE_CURRENT_SOURCE_DIR}/patread.py + ${CMAKE_CURRENT_SOURCE_DIR}/patterns.py + ${CMAKE_CURRENT_SOURCE_DIR}/patwrite.py + ${CMAKE_CURRENT_SOURCE_DIR}/synopsys.py + ${CMAKE_CURRENT_SOURCE_DIR}/utils.py + ) + + install ( FILES ${pysources} DESTINATION ${PYTHON_SITE_PACKAGES}/stratus ) diff --git a/stratus1/src/modules/patterns/Makefile.am b/stratus1/src/modules/patterns/Makefile.am new file mode 100644 index 00000000..ab049f29 --- /dev/null +++ b/stratus1/src/modules/patterns/Makefile.am @@ -0,0 +1,8 @@ + + patternsdir = $(pkgpyexecdir) + + patterns_PYTHON = patterns.py \ + patread.py \ + patwrite.py \ + synopsys.py \ + utils.py diff --git a/stratus1/src/modules/patterns/patread.py b/stratus1/src/modules/patterns/patread.py new file mode 100644 index 00000000..c305c83a --- /dev/null +++ b/stratus1/src/modules/patterns/patread.py @@ -0,0 +1,203 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Ludovic NOURY | +# | E-mail : Ludovic.Noury@lip6.fr | +# | =============================================================== | +# | Py Module : "./stratus.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + +# $Id: patread.py,v 1.1 2007/07/20 13:30:15 cobell Exp $ +# LIP6/ASIM ludovic.noury@lip6.fr +__all__ = ['PatRead'] + +from stratus import * + +## Read a pattern file and analyze it +# +# This class is designed to load and analyze output result test +# vectors from simulation. Currently it only supports Alliance ".pat" +# format. +# +# @remark we suppose that the source vector was created by a PatWrite +# instance (See PatWrite documentation). +# @todo also get time unit (with first pattern) +# @todo add code for '?uuuu' and 'uuuu' +# @todo replace compile regexps +# @version $Id: patread.py,v 1.1 2007/07/20 13:30:15 cobell Exp $ +class PatRead: + # Public attributes doxydoc ---------------------------- + ## @var connectors + # store input/output connectors order. + + ## @var connectors_current_values + # dictionary, key=connector_name + + ## @var current_time + # current pattern time stamp + + # Private attributes ----------------------------------- + ## @var _f + # file object linked to the output file. + ## @var _p + # Shortcut to the regular expression used to split strings + + # ------------------------------------------------------ + ## The constructor + # + # Open the pattern file, initialize instance attributes and call + # _get_interface method. + # + # @param filename Pattern to load & analyze filename + def __init__(self, filename): + # Init instance attributes + self.connectors = [] + self.connectors_current_values = {} + self.current_time = 0 + self._p=re.compile(r'\W+') + + # Open input file + self._f = open(filename, 'r') + + # Get interface + self._get_interface() + + # Regular expressions + + # used to dermine if a value can be used + self._re_valid = re.compile('[XxUu]') + + # ------------------------------------------------------ + ## Extract interface from input pattern file + # + # Read the input pattern until the line with "begin" indicating + # interface declaration end. + # For each connector (or internal signal) extracts direction, name + # and arity. + # + # @remark arity extraction suppose N+1 downto 0 declaration form + # and 'B' option. Ok, if pattern generated by PatWrite instance. + # + # @remark For signal, the direction is set to the value 'signal' + def _get_interface(self): + # Shortcuts to regexps + re_in=re.compile("^in") + re_out=re.compile("^out") + re_signal=re.compile("^signal") + + # Extract connectors data from file until "begin" line. + for line in self._f: + # Remove leading spaces + line = line.lstrip() + + # Stop if end of interface + if re.compile("^begin").search(line): + break + # Connector + if (re_in.search(line) or re_out.search(line) or re_signal.search(line)): + pieces = self._p.split(line) + connector = {} + connector['direction'] = pieces[0] + connector['name'] = pieces[1] + # (arity>1) => vector + # '' is to pass synopsys output pattern bug : + # in ck ;; instead of + # in ck B;; gives pieces[2] == '' instead of 'B' + if (pieces[2] != 'B') and (pieces[2] != ''): + connector['arity'] = int(pieces[2])-int(pieces[4])+1 + else: + connector['arity'] = 1 + #DEBUG: print '%s=>%s\n' % (line, connector) + self.connectors.append(connector) + + # ------------------------------------------------------ + ## Update current_time and connectors_current_values with next + # pattern values. + # + # @return Return True if a pattern has been loaded. Else return + # False. + # @todo call end method if end of patterns ? + def get_next_pattern(self): + for line in self._f: + # Stop if end of patterns + if re.compile("^end").search(line): + return False + # Special case, only one pattern + if re.compile("\s*:").match(line): + pieces = self._p.split(line) + # Update time + self.current_time = 0 + # Update connectors values dictionary + for pos in range(len(self.connectors)): + name = self.connectors[pos]['name'] + self.connectors_current_values[name] = pieces[pos+1] + return True + # We got a pattern + if re.compile("^<").search(line): + pieces = self._p.split(line) + # Update time + self.current_time = int(pieces[1]) + # Update connectors values dictionary + for pos in range(len(self.connectors)): + name = self.connectors[pos]['name'] + self.connectors_current_values[name] = pieces[pos+3] + return True + + + # ---------------------------------------------------------------- + ## Return true if the value is either X or U. + # + # @param signal signal name (string). + # @return True is the signal is invalid. + # + # Before trying to convert a value we need to be sure it's a valid + # value. + def is_invalid(self, signal): + # match is not ok because we wouldn't find partial invalid as '01XXX' + return self._re_valid.search(self.connectors_current_values[signal]) + + + + + # ---------------------------------------------------------------- + def __del__(self): + self._f.close() diff --git a/stratus1/src/modules/patterns/patterns.py b/stratus1/src/modules/patterns/patterns.py new file mode 100644 index 00000000..6e0e39b0 --- /dev/null +++ b/stratus1/src/modules/patterns/patterns.py @@ -0,0 +1,86 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Ludovic NOURY | +# | E-mail : Ludovic.Noury@lip6.fr | +# | =============================================================== | +# | Py Module : "./__init__.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + +# $Id: patterns.py,v 1.1 2007/07/20 13:30:16 cobell Exp $ +# LIP6/ASIM ludovic.noury@lip6.fr + +## @package patterns +# Package : regroups pattern analyzis and generation Stratus modules +# +# - PatRead module (class: patterns.patread.PatRead) +# - PatWrite module (class: patterns.patwrite.PatWrite) +# - Synopsys link module (class: patterns.synopsys.Synopsys) +# - \ref patterns_utils module (conversion fonctions and LoadSig class) +# (also see exemple section) +# - \ref patfloat module (all need for generating floating-point patterns) + +from patread import * +from patwrite import * +from utils import * +from synopsys import * + +## \example test_patterns.py +# +# This is a simple example of how to use the patterns package. +# +# To use it you need to add the to $PYTHONPATH the directory where +# "patterns" is. Exemple (if you run directly from the example dir add +# : export PYTHONPATH=../../:$PYTHONPATH) + +## \example test_patterns_fixed.py +# +# This is an example of how to use the patterns package with fixed +# point data. It's also a good exemple of PatRead class usage. +# +# To use it you need to add the to $PYTHONPATH the directory where +# "patterns" is. Exemple (if you run directly from the example dir add +# : export PYTHONPATH=../../:$PYTHONPATH) + +## \example adder.py +# +# Complete example of Synopsys class usage diff --git a/stratus1/src/modules/patterns/patwrite.py b/stratus1/src/modules/patterns/patwrite.py new file mode 100644 index 00000000..c4d5c521 --- /dev/null +++ b/stratus1/src/modules/patterns/patwrite.py @@ -0,0 +1,683 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Ludovic NOURY | +# | Roselyne CHOTIN-AVOT | +# | E-mail : Ludovic.Noury@lip6.fr | +# | =============================================================== | +# | Py Module : "./__init__.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + +# $Id: patwrite.py,v 1.6 2009/02/10 09:38:18 roselyne Exp $ +# Author: LIP6/ASIM ludovic.noury@lip6.fr +# Contributor: Roselyne.Chotin-Avot@lip6.fr +__all__ =['PatWrite'] + +from stratus import * +from utils import * +from math import ceil + +## Create new patterns +# +# This class is used to create patterns for Stratus models. Currently +# it only supports Alliance ".pat" pattern format. +# +# Patterns time stamps are in the "absolute date" format, "relative +# date" isn't allowed. Legal time unit are ps, ns, us and ms. Default +# is ps. +# +# @remark we suppose output pattern files won't be read by a +# human. So to simplify the implementation we don't provide +# hexadecimal or octal representation for signal values. All the +# signals values are written in binary. +# +# @todo add another constructor with time interval as parameter. +# @todo add checks. +# @todo add another constructor and variable to select time unit. +# @todo add automatic vdd/vss declaration and affect. (?) +# @todo modify declar() to be able to declar "name",arity,type +# +# @version $Id: patwrite.py,v 1.6 2009/02/10 09:38:18 roselyne Exp $ +class PatWrite: + + # Public attributes doxydoc ---------------------------- + ## @var connectors_list + # store input/output connectors order + + ## @var connectors_current_values + # dictionary, key=connector_name + + ## @var self.connectors_format + # dictionary, key=connector_name, value=connector format + + ## @var current_time + # auto-incremented after addpat() + + ## @var time_interval + # time interval + + ## @var time_unit + # time unit, valid values are ps, ns, us and ms. + + # Private attributes ----------------------------------- + ## @var _f + # file object linked to the output file + + ## @var _finished + # true if the pattern file has been written and closed. Used by + # the destructor. + + ## @var _cell + # Reference to the input Stratus cell. Used to be able to use + # design net by theirs string name. Value 0 indicates that the + # reference is unknown. + + # ------------------------------------------------------ + ## The constructor + # @param filename New pattern output filename (example: \c adder.pat). + # @param cell Optional, reference to Stratus cell. + def __init__(self, filename, cell=None): + # Instance attributes declaration + self._f = open(filename, 'w') + self._finished = False + self.connectors_list = [] + self.connectors_current_values = {} + self.connectors_format = {} + self.current_time = 0 + self.time_interval = 10 + self.time_unit = 'ns' + self._cell = cell + + + # ------------------------------------------------------ + ## The destructor + # + # Call pattern_end if it hasn't been called yet. + def __del__(self): + if self._finished == False: + self.pattern_end() + + # ------------------------------------------------------ + ## Get direction string from a net + # + # @param net Stratus net + # + # @remark: if InOut we default to out + # @todo add inout mode, but we can't select automagically in or out ! + # @todo add code for all modes (ask sophie) + def _get_direction(self, net): + return {'st_net.SignalIn' : 'in', + 'st_net.SignalOut' : 'out', + 'st_net.Signal' : 'out', + 'st_net.VddIn' : 'in', + 'st_net.VssIn' : 'in', + 'st_net.CkIn' : 'in', + 'st_net.Signal' : 'signal', + 'st_net.TriState' : 'out', + 'st_net.SignalInOut': 'out' + }[str(net.__class__)] + + #'st_net.SignalInOut': in ou out selon le voeux de util' + #'st_net.SignalUnknown': je sais pas quoi faire + #'st_net.TriState' : je sais pas quoi faire + # VddInFromHur, VssInFromHur, Signal_virtuel + + + # ------------------------------------------------------ + # Predicate, true of the connector is an output + # @remark: considers that SignalInOut is an output + # + # @param self object reference + # @param connector Stratus connector + def _is_output(self, connector): + return ((str(connector.__class__ ) == "st_net.SignalOut") or + (str(connector.__class__ ) == "st_net.SignalInOut")) + + # ------------------------------------------------------ + ## Adds a connector from a Stratus model to the pattern interface. + # + # Writes the corresponding connector declaration in the pattern + # file with name, arity and direction automatically extracted from + # the connector properties. + # + # Also adds the connector to \e connectors_list. It is used when + # add patterns to respect the connectors order. + # + # Supported Stratus connectors are: + # - SignalIn, + # - SignalOut (only supported if used as an output), + # - VddIn, + # - VssIn, + # - CkIn, + # - SignalInOut, + # - TriState (always an output), + # - Signals. + # + # @param connector Can either be a reference to a stratus net or a + # string containing the name of the stratus net. + # + # @param format Optional format for the connectors values into the + # pattern file, accepted values are : + # - 'B': binary (default), + # - 'X': hexadecimal, + # - 'O': octal. + # + # @remark if the connector arity is greater than 1 it will always + # be written in the form N downto 0. + # + # @remark if the connector arity is 1 the format is set 'B' even if + # the format parameter is set to another value. + # + # @remark To be able to use a string as connector parameter the + # constructor must have been given a reference to the net. + # + # @warning string connector don't seem to work for vdd/vss + # + # @todo add exception when string command and self._cell unset + # @todo add exception when string command signal not found + def declar(self, connector, format='B'): + + # 1. Check connector type: + # - if stratus net, then nothing to do + # - if string name, then search for a net with this name + from types import StringType + if type(connector) is StringType: + for net in self._cell._st_sigs: + if (net._name == connector): + connector_ref = net + else: + connector_ref = connector + + # 2.write declaration to output file + # 2.a write connector direction + self._f.write(self._get_direction(connector_ref).rjust(5) + + " " + connector_ref._name) + # 2.b write: "N downto 0" if necessary + if(connector_ref._arity != 1): + self._f.write(" (" + str(connector_ref._arity-1) + " downto 0)") + + # 2.c write format + if ((format == 'B') or (connector_ref._arity == 1)): + self._f.write(" B;;\n") + elif format == 'X': + self._f.write(" X;;\n") + elif format == 'O': + self._f.write(" O;;\n") + + # 3. add connector to list (we need an ordered connectors lists) + self.connectors_list.append(connector_ref._name) + self.connectors_format[connector_ref._name] = format + + # 4. if output connector or signal set value to any + if ((self._get_direction(connector_ref) == 'out') or + (self._get_direction(connector_ref) == 'signal')): + self.affect_any(connector_ref) + + # ------------------------------------------------------ + ## Subcomponents internal signals declaration + # + # Imported vst signals aren't in the database. Hence we can't + # easily import data. So the designer has to set all the parameter + # with this command to allow pattern check of subcomponents + # internal signals values. + # + # @param self object reference + # @param signame string with the full signal name eg: + # instance0_modpmfs8_fsm.chip_ep + # @param msb signal msb, default value 0 + # @param lsb signal lsb, default value 0 + # @param format optional, default value B, repport + # declar_interface documentation + def declar_subsig(self, signame, msb=0, lsb=0, format='B'): + self.connectors_list.append(signame) + self.connectors_format[signame] = format + + if msb == lsb : + self._f.write('signal %s %s;;\n' % \ + (signame, format)) + else: + self._f.write('signal %s (%d downto %d) %s;;\n' % \ + (signame, msb, lsb, format)) + + # create output value + any_str = '' + arity = msb-lsb+1 + if format == 'B': + any_str += arity*'*' + elif format == 'O': + any_str += int(ceil(arity/3.))*'*' + elif format == 'X': + any_str += int(ceil(arity/4.))*'*' + + # Update connectors values dictionary + self.connectors_current_values[signame] = any_str + + + + # ------------------------------------------------------ + ## Adds all the connectors from a Stratus model to the pattern + # interface. + # + # Write the corresponding connector declaration in the pattern + # file with name, arity and direction directly taken from the + # connector proprieties. + # + # Also add the connector to the connectors_list. The connector + # list is used to store the connectors order. It's used later when + # we'll write the patterns. + # + # @remark Declarare in the following order: clock, input, output, + # vdd, vss. The fixed connector order is a constraint for Synopsys + # testbench generation. + # + # @remark The only supported connectors are instance of SignalIn, + # SignalOut, VddIn, VssIn and CkIn. + # + # @remark If the connector arity is greater than 1 it will always + # be written in the form N downto 0. + # + # @param self The object pointer + # @param cell The tested Stratus model reference. Optional if a + # reference to the tested Stratus model was given during + # instanciation (patterns.patwrite.PatWrite.__init__ cell parameter). + # @param format Optional format for the connectors values into the + # pattern file, accepted values are : + # - 'B': binary (default), + # - 'X': hexadecimal, + # - 'O': octal. + # + # @remark if the conector arity is 1 the format is 'B' + # @todo use get_interface simplify + def declar_interface(self, cell=None, format='B'): + # + if (cell==None): + if self._cell == None: + raise Exception("PatWrite.declar_interface() " + "cell reference no given during PatWrite instanciation," + " thus the cell parameter is mandatory.") + else: + cell = self._cell + + # 1. Clocks + for port in cell._st_cks: + if isinstance(port, CkIn): + self.declar(port, format) + + # 2. Inputs + for port in cell._st_ports: + if isinstance(port, SignalIn): + self.declar(port, format) + + # 3. Outputs + for port in cell._st_ports: + if isinstance(port, SignalOut): + self.declar(port, format) + + # 4. VDDs + for port in cell._st_vdds: + if isinstance(port, VddIn): + self.declar(port, format) + + # 5. VSSs + for port in cell._st_vsss: + if isinstance(port, VssIn): + self.declar(port, format) + + # 6. TriState + for port in cell._st_ports: + if isinstance(port, TriState): + self.declar(port, format) + + ## Return interface connectors dictionnary where key is the conector's name + # and value the connector's format ('B' or 'X' or 'O') + # + # @param name is the tested Stratus model reference name + # @return connectors dictionnary + def get_interface_format(self, name): + file = open(name+'.pat', 'r') + dict = {} + for line in file : + # stop at end of the declaration + if re.compile(r"^begin$", re.I).search(line): + break; + # skip blank line + if re.compile(r"^ *$", re.I).search(line): + continue + # get name and format + res = re.search("[in|out]+ *(\w*).*([X|B|O]) *;*",line).group(1,2) + dict[res[0]] = res[1] + file.close() + return dict + + + ## Return interface connectors list + # + # Construct an ordered connectors list corresponding to + # declare_interface() order. + # + # @param cell tested Stratus model reference. Optional if a + # reference to the tested Stratus model was given during + # instanciation (patterns.patwrite.PatWrite.__init__ cell parameter). + # @return connectors list + def get_interface(self, cell=None): + l = [] + + if (cell==None): + if self._cell == None: + raise Exception("PatWrite.get_interface() " + "cell reference no given during PatWrite instanciation," + " thus the cell parameter is mandatory.") + else: + cell = self._cell + + # 1. Clocks + for port in cell._st_cks: + if isinstance(port, CkIn): + port._format = self.connectors_format[port._name] + l.append(port) + + # 2. Inputs + for port in cell._st_ports: + if isinstance(port, SignalIn): + port._format = self.connectors_format[port._name] + l.append(port) + + # 3. Outputs + for port in cell._st_ports: + if isinstance(port, SignalOut): + port._format = self.connectors_format[port._name] + l.append(port) + + # 4. VDDs + for port in cell._st_vdds: + if isinstance(port, VddIn): + port._format = self.connectors_format[port._name] + l.append(port) + + # 5. VSSs + for port in cell._st_vsss: + if isinstance(port, VssIn): + port._format = self.connectors_format[port._name] + l.append(port) + + return l + + + # ------------------------------------------------------ + ## Affect a string value to a connector + # + # Update the connectors_current_values dictionary with value. + # + # @param connector Stratus connector + # @param value String to affect to connector + def affect(self, connector, value): + self.connectors_current_values[connector._name] = value + + # ------------------------------------------------------ + ## Affect an integer (CA2) value to a connector + # + # Convert the 2's complement value to the corresponding binary + # value. The binary size is taken from the connector arity. Then, + # update the connectors_current_values dictionary with the + # computed binary value. + # + # If the connector is an output, the binary value is preceded by + # "?". + # + # @param connector Stratus connector. + # @param value 2's complement value to affect to the connector. + # @todo add code for octal format and execption ... + def affect_int(self, connector, value): + # Test if the connector is a connector + if str(connector.__class__ ) not in ( "st_net.SignalIn", "st_net.SignalOut", "st_net.SignalInOut", "st_net.SignalUnknown", "st_net.TriState", "st_net.VddIn", "st_net.VssIn", "st_net.CkIn" ) : + raise Exception("PatWrite.affect_int() the first argument must be an external net.") + + # 1.Test if output connector + if self._is_output(connector): + tmp = "?" + else: + tmp ="" + + # 2. Get connector format + format = self.connectors_format[connector._name] + + # 3. Create output string + if format == 'B': + tmp += int2str(value, connector._arity) + elif format == 'O': + pass + elif format == 'X': + tmp += int2strhex(value, connector._arity) + + # 4. Update connector value + self.connectors_current_values[connector._name] = tmp + + + + # ------------------------------------------------------ + ## Affect a fixed point value to a connector. + # + # Convert the floating point input value to the corresponding + # fixed point value with word_length=connector.arity() and + # integer_word_length=iwl. + # + # If the connector is an output, the binary value is preceded by + # "?". + # + # @param connector Stratus connector. + # @param value floating point value to convert and asign to connector. + # @param iwl integer word length + def affect_fix(self, connector, value, iwl): + # 1.Test if output connector + if self._is_output(connector): + tmp = "?" + else: + tmp ="" + + # 2.Finish to compute binary string and update connectors + # values dictionary. + self.connectors_current_values[connector._name] = \ + tmp+float2strfix(value, connector._arity, iwl) + + # ------------------------------------------------------ + ## Disable comparison between this connector value and the one + # calculated during simulation. + # + # @param connector Stratus connector. + # + # @remark We systematicaly write the optional "?" mark before the + # "*" symbols. This is to allow the Synopsys module generated + # testbench to correctly detect output values. With this all the + # output values are begin with "?". + # + # @todo add exception if unknown type + def affect_any(self, connector): + # search connector format + format = self.connectors_format[connector._name] + + # create output value + any_str = '?' + if format == 'B': + any_str += connector._arity*'*' + elif format == 'O': + any_str += int(ceil(connector._arity/3.))*'*' + elif format == 'X': + any_str += int(ceil(connector._arity/4.))*'*' + + + # Update connectors values dictionary + self.connectors_current_values[connector._name] = any_str + + + + # ------------------------------------------------------ + ## Adds a pattern + # + # Add the pattern with @e current_time time and + # @e connectors_current_values values. Then increment + # @e current_time by @e time_interval. + def addpat(self): + # write time and comment + self._f.write("< " + str(self.current_time).rjust(10) + + " " + self.time_unit + ">" + " : ") + # write connectors values + for connector in self.connectors_list: + if connector not in self.connectors_current_values : + raise Exception("PatWrite.addpat() : connector %s is missing." % connector) + self._f.write(self.connectors_current_values[connector] + " ") + # end pattern + self._f.write(";\n") + + # increment time for next pattern + self.current_time += self.time_interval + + # ------------------------------------------------------ + ## Mark the end of the interface declaration and the beginning of + # the test vectors. + def pattern_begin(self): + self._f.write("\nbegin\n\n") + + # ------------------------------------------------------ + ## Mark the end of the test vectors and of the patterns file. + def pattern_end(self): + self._f.write("\nend;\n") + self._f.close() + self._finished = True + + + # ------------------------------------------------------ + ## Automatically create the pattern values for arithmetic function + # of 2 inputs + # + # @param cell is the tested Stratus model + # @param val_mask is the value of the MaskNumber + # @param function is the arithmetic function to test defined as a python lambda + # function of (a,b) operands (ex: function = lambda a,b : a+b) + # @param mode is the mode for the patterns : + # - 'zd' : zero delay simulation + # - 'delay' : the current pattern affects the inputs and the next the output + # - 'dense delay' : the current pattern affects the inputs and the output of the last pattern + # + # @remark this function can be used only if the cell's ports are : + # - i0 corresponding to the 1st operand signal + # - i1 corresponding to the 2nd operand signal + # - o corresponding to the output signal + # - cin corresponding to the input carry signal (optionnal) + # - cout corresponding to the output carry signal (optionnal) + def pat_function(self, cell, val_mask, function, mode = 'zd'): + res = res_cout = None + if 'cin' not in cell._param : cin = False + else : cin = param['cin'] + if 'cout' not in cell._param : cout = False + else : cout = param['cout'] + + # extends the sign of a given value from width1 to width2 + def extend(val,width): + if val >= 2**(width-1): + mask = ~(2**width-1) + return (val | mask) + else: + return val + # cout calculation + def cout_cal(valA,valB,valCin): + mask = 2**cell._nbit - 1 + val = (valA & mask) + (valB & mask) + valCin + if val >= 2**cell._nbit: + return 1 + else: + return 0 + + # Affectation + self.affect_int(cell._st_vdds[0], 1) + self.affect_int(cell._st_vsss[0], 0) + # use of a MaskNumber value of val_mask for the 2 input + valuesA = MaskNumber(cell.i0._arity,val_mask) + for valA in valuesA: + valuesB = MaskNumber(cell.i1._arity,val_mask) + for valB in valuesB: + self.affect_int(cell.i0,valA) + self.affect_int(cell.i1,valB) + # take account of sign extension + if cell._signed : + valAe = extend(valA,cell.i0._arity) + valBe = extend(valB,cell.i1._arity) + else: + valAe = valA + valBe = valB + if cin: + for valCin in (0,1): + self.affect_int(cell.cin,valCin) + # the output is affected with the parameter function + res_old = res + res = function(valAe,valBe)+valCin + res_cout_old = res_cout + res_cout = cout_cal(valAe,valBe,valCin) + if mode == 'zd' : + self.affect_int(cell.o,res) + if cout: + self.affect_int(cell.cout,res_cout) + elif mode == 'delay' : + self.affect_any(cell.o) + if cout: + self.affect_any(cell.cout) + self.addpat() + self.affect_int(cell.o,res) + if cout: + self.affect_int(cell.cout,res_cout) + elif mode == 'dense delay' : + if res_old == None : + self.affect_any(cell.o) + else: + self.affect_int(cell.o,res_old) + if cout: + if res_cout_old == None : + self.affect_any(cell.cout) + else: + self.affect_int(cell.cout,res_cout_old) + self.addpat() + else: + # the output is affected with the parameter function + res = function(valAe,valBe) + self.affect_int(cell.o,res) + if cout: + self.affect_int(cell.cout,cout_cal(valA,valB,0)) + self.addpat() diff --git a/stratus1/src/modules/patterns/synopsys.py b/stratus1/src/modules/patterns/synopsys.py new file mode 100644 index 00000000..c7499c34 --- /dev/null +++ b/stratus1/src/modules/patterns/synopsys.py @@ -0,0 +1,867 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Ludovic NOURY | +# | Roselyne CHOTIN-AVOT | +# | E-mail : Ludovic.Noury@lip6.fr | +# | =============================================================== | +# | Py Module : "./__init__.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + +# ---------------------------------------------------------------------------- +# $Id: synopsys.py,v 1.6 2008/11/26 15:19:11 roselyne Exp $ +# Author: LIP6/ASIM ludovic.noury@lip6.fr +# Contributor: Roselyne.Chotin-Avot@lip6.fr +# ---------------------------------------------------------------------------- +import os +import re +from tempfile import TemporaryFile + +from stratus import * + + +# ---------------------------------------------------------------------------- +## Everything to simulate with Synopsys +# +# - export design to VHDL. +# - create testbench and run blocks +# - Synopsys compilaltion +# - Synopsys simulation +# +# See complete example into the example section +# +# @remark ".pat" connectors order is important, the call to patWrite +# instance to get it. +# +# @remark Currently all values must be in binary in the ".pat". +# +# @remark This is a first draft. This class should be edited a lot and +# maybe merged (or dervived from) with patwrite +# +# @todo signal errors to output pat like asimut does +# @todo separate debug to (verbose and debug) +# @bug description bloc copy to res has some missing caracters. Hack +# adds missing ';' ... +class Synopsys: + + # @var self._cell cell + + # ------------------------------------------------------------- + ## Constructor + # @var cell reference to Stratus design cell + def __init__(self, cell): + self._cell = cell + self._name = cell._name + + # ------------------------------------------------------------- + ## Convert the VST netlist to VHDL + # + # Uses VASY to convert from VST to VHDL, then remove VDD/VSS from + # resulting VHD files. Optionaly rename fd1qll cells input clock + # from 'ck' to 'cp' (st option). + # + # raise Exception if error + # @param debug debug mode (default=False) + # @param st must be set to True if we use ST CORE9GP standard cells + # @bug as the function is generic and don't depend on synopsys it + # should be defined somewhere else. (But it depends on VASY) + def convert_to_vhdl(self, debug=False, st=False): + # Convert to VHDL + if debug: + print('VST to VHDL conversion ---------------' + '--------------------------------------\n' + ' - VASY (%s) ...'% self._name) + if os.system('vasy -o -V -S -I vst -H %s %s 1> %s_vasy.log' % + (self._name, self._name, self._name)): + raise Exception('VASY error (see "%s_vasy.log")'% self._name) + vhdl = re.compile(r'\.vhd$') + + # Remove VDD/VSS and change CK to ST name + if debug and st: + print(' - remove vdd/vss connectors declarations and change registers\n' + ' input connector name (ST mode) ...') + elif debug: + print(' - remove vdd/vss connectors declarations ...') + + for filename in os.listdir('./'): + if vhdl.search(filename): + self._remove_power(filename, False) # false for no debug + if st: + self._change_ck2st(filename, False) # false for no debug + + if debug: + print ' - VHDL conversion done.' + + # ------------------------------------------------------------- + ## Remove power supply connectors from a VHDL file. + # + # Overwrite input file. + # + # @param filename VHDL input file name. + # @param debug debug mode (default False). + # @bug if instances names have vdd/vss in !!! + def _remove_power(self, filename, debug=False): + # STEP1: remove vdd/vss ------------------------------------- + input = open(filename, 'r') + temp = TemporaryFile('w+') + alim = re.compile('.*(vdd|vss)+.*', re.IGNORECASE) + removed = 0 + + for line in input: + if not alim.search(line): + temp.write(line) + else: + removed += 1 + + if debug: + print ' - removed %d power supply declarations'%removed + + input.close() + + # STEP2: remove ";\n)" and ",\n)" syntax errors ------------- + temp.seek(0) + + out = open(filename, 'w') + + comma = re.compile('.*\w+.*(;|,)') + close = re.compile('^\s*\);') + corrige = re.compile('(;|,)') + corrected = 0 + + previous = temp.next() + for current in temp: + if close.search(current) and comma.search(previous): + out.write(corrige.sub('', previous)) + corrected += 1 + else: + out.write(previous) + previous = current + out.write(previous) + + if debug: + print ' - corrected %s syntax errors'%corrected + + # END ------------------------------------------------------- + temp.close() + input.close() + out.close() + + # ------------------------------------------------------------- + ## Correct clocks names for ST CORE9GP fd1qll cells + # + # Change 'ck' connector name to 'cp'. Overwrite input file + # + # @param filename VHDL input filename. + # @param debug Debug mode (default=False) + def _change_ck2st(self, filename, debug=False): + # STEP1: change CKs ----------------------------------------- + input = open(filename, 'r') + temp = TemporaryFile('w+') + + alim = re.compile('.*(vdd|vss)+.*', re.IGNORECASE) + changed = 0 + + reg_declare = re.compile('COMPONENT fd1qll') + reg_inst = re.compile(': fd1qll') + reg_aff = re.compile('ck =>') + + for line in input: + if reg_declare.search(line): + temp.write(line) + temp.write(input.next()) + temp.write(' cp : IN STD_LOGIC;\n') + input.next() + changed += 1 + elif reg_inst.search(line): + temp.write(line) + temp.write(input.next()) + line = input.next() + temp.write(reg_aff.sub('cp =>', line)) + changed += 1 + else: + temp.write(line) + + if debug: + print ' - changed %d ck'%changed + + # STEP2: write changes to input file ------------------------ + temp.seek(0) + input.close() + input = open(filename, 'w') + for line in temp: + input.write(line) + + # END ------------------------------------------------------- + input.close() + temp.close() + + # ------------------------------------------------------------- + def create_testbench(self, interface, delay, unit, debug=False, downto=False, logic=False): + name = self._cell._name + '_tb' + outfilename = self._cell._name + '_res.pat' + infilename = self._cell._name + '.pat' + tb = open('%s_tb.vhd'%self._cell._name, 'w') + + if debug: + print('Testbench module ---------------------' + '--------------------------------------\n' + ' - module name : %s.vhd\n' + ' - patterns input : %s\n' + ' - patterns output: %s' + % (name, infilename, outfilename)) + + # Libraries --------------------------------------------------- + tb.write('library ieee;\n' + 'use ieee.std_logic_1164.all;\n' + 'use ieee.std_logic_textio.all;\n' + 'use std.textio.all;\n\n') + + # Entity ------------------------------------------------------ + # Declar input, outputs and clocks. No support inout yet. + tb.write('entity %s IS\n\n' + ' port (\n' % name) + for signal in self._cell._st_ports: + # SignalIn + if isinstance(signal, SignalIn): + tb.write(' %s : out std_logic' % signal._name) + # SignalOut + elif isinstance(signal, SignalOut): + tb.write(' %s : in std_logic' % signal._name) + # SignalInOut (unsupported) + elif isinstance(signal, SignalInOut): + raise Exception('unsupported connector (SignalInOut: %s)' % signal._name) + # Skip to next if not a IO + else: + continue + # Bit vectors + if signal._arity != 1: + if downto : + tb.write('_vector(%d downto 0)'% (signal._arity-1)) + else: + tb.write('_vector(0 to %d)'% (signal._arity-1)) + tb.write(';\n') + + # CkIn + for signal in self._cell._st_cks: + tb.write(' %s : out std_logic;\n' % signal._name) + + # Remove last ';' + tb.seek(-2,1) + tb.write(');\n\n' + 'end %s;\n\n' % name) + + # Architecture ------------------------------------------------ + tb.write('architecture rtl of %s is\n\n' % name) + + # Procedures + tb.write(' -- Skip whitespaces\n' + ' procedure skip_spaces(l :inout line) is\n' + ' variable c : character;\n' + ' begin\n' + ' loop\n' + " if l(1) = ' ' then\n" + ' read(l, c);\n' + ' else\n' + ' exit;\n' + ' end if;\n' + ' end loop;\n' + ' end skip_spaces;\n\n') + + tb.write(' -- Skip asterisks\n' + ' procedure skip_asterisks(l :inout line) is\n' + ' variable c : character;\n' + ' begin\n' + ' loop\n' + " if l(1) = '*' then\n" + ' read(l, c);\n' + ' else\n' + ' exit;\n' + ' end if;\n' + ' end loop;\n' + ' end skip_asterisks;\n\n') + + tb.write(' -- Check for end of declaration block\n' + ' procedure is_begin(l : inout LINE; declaration_block : inout boolean) is\n' + ' begin\n' + " if l(1)='b' and l(2)='e' and l(3)='g' and l(4)='i' and l(5)='n' then\n" + ' declaration_block := false;\n' + ' end if;\n' + ' end is_begin;\n\n') + + + tb.write(' -- change end_pat to true if end detected\n' + ' procedure is_end (l : inout line; end_pat : inout boolean) is\n' + ' begin\n' + " if l(1)='e' and l(2)='n' and l(3)='d' and l(4)=';' then\n" + ' end_pat := true;\n' + ' end if;\n' + ' end is_end;\n\n') + + + + tb.write('begin -- rtl\n\n') + + # Variables + tb.write(' process\n' + ' -- VARIABLES\n' + ' variable l : line; -- input line\n' + ' variable lout : line; -- output line\n' + ' variable ldebug : line; -- termial output line\n' + ' variable empty_line : line;\n' + ' variable declaration_block : boolean := true;\n' + ' variable end_of_patterns : boolean := false;\n' + ' variable char : character;\n' + ' file TTY_OUTPUT: TEXT open WRITE_MODE is "STD_OUTPUT";\n' + ) + + tb.write(' -- INPUT PATTERNS VARIABLES\n') + in_list = [] + for c in interface: + if isinstance(c, SignalIn) or isinstance(c, CkIn): + in_list.append(c) + if (c._format == 'X') and (c._arity % 4 != 0) and (c._arity != 1): + tb.write(' variable v_%s_ext: std_logic' % c._name) + if downto : + tb.write('_vector(%d downto 0)'% (c._arity-1 + (4 - c._arity % 4))) + else: + tb.write('_vector(0 to %d)'% (c._arity-1) + (4 - c._arity % 4)) + tb.write(';\n') + tb.write(' variable v_%s: std_logic' % c._name) + if c._arity != 1: + if downto : + tb.write('_vector(%d downto 0)'% (c._arity-1)) + else: + tb.write('_vector(0 to %d)'% (c._arity-1)) + tb.write(';\n') + + tb.write(' -- OUTPUT PATTERNS VARIABLES\n') + out_list = [] + for c in interface: + if isinstance(c, SignalOut): + out_list.append(c) + if (c._format == 'X') and (c._arity % 4 != 0) and (c._arity != 1): + tb.write(' variable vpat_%s_ext: std_logic' % c._name) + if downto : + tb.write('_vector(%d downto 0)'% (c._arity-1 + (4 - c._arity % 4))) + else: + tb.write('_vector(0 to %d)'% (c._arity-1) + (4 - c._arity % 4)) + tb.write(';\n') + tb.write(' variable vpat_%s: std_logic' % c._name) + if c._arity != 1: + if downto: + tb.write('_vector(%d downto 0)'% (c._arity-1)) + else: + tb.write('_vector(0 to %d)'% (c._arity-1)) + tb.write(';\n') + if (c._format == 'X') and (c._arity % 4 != 0): + tb.write(' variable v_%s_ext: std_logic' % c._name) + if c._arity != 1: + if downto : + tb.write('_vector(%d downto 0)'% (c._arity-1 + (4 - c._arity % 4))) + else: + tb.write('_vector(0 to %d)'% (c._arity-1) + (4 - c._arity % 4)) + tb.write(';\n') + tb.write(' variable v_%s : std_logic' % c._name) + if c._arity != 1: + if downto: + tb.write('_vector(%d downto 0)'% (c._arity-1)) + else: + tb.write('_vector(0 to %d)'% (c._arity-1)) + tb.write(';\n') + + + tb.write(' -- FILES\n' + ' file outfile : TEXT is OUT "%s"; -- input patterns\n' + ' file infile : TEXT is IN "%s"; -- output patterns\n' % + (outfilename, infilename)) + tb.write(' begin -- process\n') + tb.write(' write(empty_line, string\'(""));') + # Write header to pat + tb.write(' -- Write Header\n' + ' write(l, string\'("-- Synopsys VHDL simulation results"));\n' + ' writeline(outfile, empty_line);\n\n') + # MAIN LOOP + tb.write(' -- main loop\n' + ' while not endfile(infile) loop\n' + ' readline(infile, l);\n') + # Comments and empty lines + tb.write(' ---------------------------------------------------------\n' + ' -- Comments and empty lines\n' + ' ---------------------------------------------------------\n' + ' -- skip empty lines\n' + ' if L\'length = 0 then\n' + ' writeline(outfile, empty_line);\n' + ' next;\n' + ' end if;\n\n' + + " -- Skip '--' comments\n" + " if (l(1) = '-') and (l(2) = '-') then\n" + ' next;\n' + ' end if;\n\n' + + " -- Copy '#' comments to output file\n" + " if l(1) = '#' then\n" + ' writeline(outfile, l);\n' + ' next;\n' + ' end if;\n') + # Declaration block + tb.write(' ---------------------------------------------------------\n' + ' -- Declaration block\n' + ' ---------------------------------------------------------\n' + ' skip_spaces(l);\n' + ' if declaration_block then\n' + ' -- Check for end of declaration block and copy to output\n' + ' is_begin(l, declaration_block);\n' + ' -- Ugly hack : add mysteriously missing ending ";;"\n' + ' if declaration_block then\n' + ' write(l, string\'(";;"));\n' + ' end if;\n' + ' writeline(outfile, l);\n' + ) + + # Description block + # - time + tb.write(' ---------------------------------------------------------\n' + ' -- Description block\n' + ' ---------------------------------------------------------\n' + " elsif l(1) = '<' then -- lines begin with <\n" + " -- we don't copy time, instead we use simulation time\n" + ' read(l, char);\n' + " while char /= '>' loop\n" + ' read(l,char);\n' + ' end loop;\n' + ' write(lout, string\'("< "));\n' + ' write(lout, now);\n' + ' write(lout, string\'(" >"));\n\n' + + ' -- Copy label to outfile\n' + ' read(l, char);\n' + " while char /= ':' loop\n" + ' write(lout, char);\n' + ' read(l,char);\n' + ' end loop;\n' + ' write(lout, char);\n' + " write(lout, character'(' '));\n\n") + # - read pattern values and affect them netlist + tb.write(' -- read inputs values from connectors and write them to output\n') + for c in in_list: + n = c._name + hex='' + ext='' + if ((c._format == 'X') and (c._arity > 1)): + hex = 'h' + if (c._arity % 4) != 0: + ext = '_ext' + #else: + # hex = '' + tb.write(' -- %s\n' + ' skip_spaces(l);\n' + ' %sread(l, v_%s%s);\n' + ' %swrite(lout, v_%s%s);\n' + " write(lout, ' ');\n" % (n, hex, n, ext, hex, n, ext)) + tb.write(' %s <= ' % n) + + if c._arity == 1: + tb.write('v_%s;' % n) + else: + for b in range(c._arity-1, -1, -1): + tb.write('v_%s%s(%d)&' % (n, ext, b)) + tb.seek(-1,1) + tb.write('; -- to respect order in .pat\n') + + + # - get output connectors values and write them to outfile + # - delay beetween input and output + if logic : + tb.write('\n -- delay\n' + ' wait for %d %s;\n\n' % (delay, unit)) + tb.write('\n -- get output connectors values and write them to outfile\n') + for c in out_list: + n = c._name + hex='' + ext='' + if ((c._format == 'X') and (c._arity > 1)): + hex = 'h' + if (c._arity % 4) != 0: + ext = '_ext' + #else: + # hex = '' + tb.write(' -- %s\n' + ' v_%s := ' % (n, n)) + if c._arity == 1: + tb.write('%s;' % n) + else: + for b in range(c._arity-1, -1, -1): + tb.write('%s(%d)&' % (n, b)) + tb.seek(-1,1) + tb.write('; -- to respect order in .pat\n') + + tb.write(' write(lout, string\'("?"));\n' + ' %swrite(lout, v_%s%s);\n' + " write(lout, character'(' '));\n" + ' skip_spaces(l);\n' + " read(l, char); -- skip '?'\n" + " if l(1) /= '*' then\n" + ' %sread(l, vpat_%s%s);\n' % (hex, n, ext, hex, n, ext)) + if (c._format == 'X') and ((c._arity % 4) != 0) and (c._arity > 1) : + tb.write(' vpat_%s := vpat_%s_ext(vpat_%s\'range);\n' %(n, n, n)) + tb.write(' if vpat_%s /= v_%s then\n' + ' write(ldebug, string\'("- at time="));\n' + ' write(ldebug, now);\n' + ' write(ldebug, string\'(" error: %s="));\n' + ' %swrite(ldebug, v_%s%s);\n' + ' write(ldebug, string\'(" (expected "));\n' + ' %swrite(ldebug, vpat_%s%s);\n' + ' write(ldebug, string\'(")"));\n' + ' writeline(TTY_OUTPUT, ldebug);\n' + ' end if;\n' + ' end if;\n' + ' skip_asterisks(l);\n' + % (n, n , n, hex, n, ext, hex, n, ext)) + + # - write vdd vss + tb.write('\n -- write vdd/vss\n' + ' write(lout, string\'("1 0;"));\n') + # - save line + tb.write('\n -- save line\n' + ' writeline(outfile, lout);\n\n') + + # - delay beetween 2 patterns + if not logic: + tb.write('\n -- delay\n' + ' wait for %d %s;\n\n' % (delay, unit)) + + # End of pattern + tb.write(' ---------------------------------------------------------\n' + ' -- End\n' + ' ---------------------------------------------------------\n' + ' else\n' + ' is_end(l, end_of_patterns);\n' + ' if end_of_patterns then\n' + ' writeline(outfile, l);\n' + ' assert false report "End of simulation."\n' + ' severity note;\n' + ' wait;\n' + ' end if;\n' + ' end if;\n' + ' end loop;\n' + ' ASSERT FALSE REPORT "End of simulation without end signal !"\n' + ' severity ERROR;\n' + ' wait;\n' + ' end process;\n' + '\nend rtl;\n') + tb.close() + + + if debug: + print(' - testbench successfully created') + + + + # ---------------------------------------------------------------- + ## Remove STCells empty vhd files + # + # To allow the use of ST macroblocks we declare them a ".vst". + # As a consequence, VASY outputs .vhd files corresponding to these + # blocks, which belonging to the library musn't be here a ".vhd". + def remove_stcells_vhds(self, debug=False): + stmacro = 'b2cr_65.vhd dphs9gp_72x12m4d4_h.vhd schmitc_65.vhd' + + if debug: + print('Remove macroblocks ".vhd"-------------' + '--------------------------------------\n' + ' - block list: %s' % stmacro) + + os.system('rm -f %s'%stmacro) + + if debug: + print(' - macroblocks vhds removed') + + + # ---------------------------------------------------------------- + ## Create run block + # + # run block instanciate both design and testbench + def create_run(self, interface, debug=False, downto=False): + name = self._cell._name + '_run' + run = open('%s.vhd' % name, 'w') + + if debug: + print('Run module ---------------------------' + '--------------------------------------\n' + ' - module name : %s.vhd' % name) + + # Libraries --------------------------------------------------- + run.write('library ieee;\n' + 'use ieee.std_logic_1164.all;\n' + 'use ieee.std_logic_textio.all;\n' + 'use std.textio.all;\n\n') + # Entity ------------------------------------------------------ + run.write('entity %s is\n' + 'end %s;\n\n' % (name, name)) + + # Architecture ------------------------------------------------ + run.write('architecture rtl of %s is\n\n' % name) + # - signals + run.write(' -- SIGNALS\n') + + for c in interface: + if (isinstance(c, SignalIn) or isinstance(c, SignalOut) or + isinstance(c, CkIn)): + run.write(' signal %s: std_logic' % c._name) + if c._arity != 1: + if downto: + run.write('_vector(%d downto 0)'% (c._arity-1)) + else: + run.write('_vector(0 to %d)'% (c._arity-1)) + run.write(';\n') + + # - components + run.write('\n -- COMPONENTS\n') + + run.write(' component %s\n' + ' Port(\n' % self._cell._name) + for c in interface: + if isinstance(c, SignalIn) or isinstance(c, CkIn): + run.write(' %s: in std_logic' % c._name) + elif isinstance(c, SignalOut): + run.write(' %s: out std_logic' % c._name) + else: + continue # skip vdd/vss + if c._arity != 1: + if downto: + run.write('_vector(%d downto 0)'% (c._arity-1)) + else: + run.write('_vector(0 to %d)'% (c._arity-1)) + run.write(';\n') + # Remove last ';' + run.seek(-2,1) + run.write(');\n' + ' end component;\n\n') + + run.write(' component %s_tb\n' + ' Port(\n' % self._cell._name) + for c in interface: + if isinstance(c, SignalIn) or isinstance(c, CkIn): + run.write(' %s: out std_logic' % c._name) + elif isinstance(c, SignalOut): + run.write(' %s: in std_logic' % c._name) + else: + continue # skip vdd/vss + if c._arity != 1: + if downto : + run.write('_vector(%d downto 0)'% (c._arity-1)) + else: + run.write('_vector(0 to %d)'% (c._arity-1)) + run.write(';\n') + # Remove last ';' + run.seek(-2,1) + run.write(');\n' + ' end component;\n\n') + + # - main + run.write('begin\n\n' + ' CHIP: %s\n' + ' port map (' % self._cell._name) + for c in interface: + if (isinstance(c, SignalIn) or isinstance(c, SignalOut) or + isinstance(c, CkIn)): + run.write(c._name+', ') + # remove last ', ' + run.seek(-2,1) + run.write(');\n\n') + + run.write(' STIM: %s_tb\n' + ' port map (' % self._cell._name) + for c in interface: + if (isinstance(c, SignalIn) or isinstance(c, SignalOut) or + isinstance(c, CkIn)): + run.write(c._name+', ') + # remove last ', ' + run.seek(-2,1) + run.write(');\n\n') + + + run.write('end rtl;') + run.close() + + if debug: + print(' - run module successfully created') + + + + # --------------------------------------------------------------- + ## Compile for Synopsys VHDL simulation + def compile(self, debug=False): + if debug: + print('Compile design Synopsys simulator ----' + '--------------------------------------\n' + ' - vhdlan ...') + os.system('mkdir WORK') + vhdl = re.compile(r'\.vhd$') + for filename in os.listdir('./'): + if vhdl.search(filename): + #if debug: + # print('vhdlan: %s' % filename) + if (os.system('vhdlan -nc -debug %s' % filename) != 0): + raise Exception('vhdlan error: vhdlan failure on "%s" analysis or ' + 'Synopsys environment not set.' % filename) + if debug: + print(' - scs %s (ignore "sys_errlist" and "sys_nerr" warnings) ...' + % self._name) + os.system('scs -nc -debug %s_run' % self._name) + + if debug: + print(' - simulator successfully created') + + # --------------------------------------------------------------- + ## Run Synopsys simulation + def run(self, debug=False): + if debug: + print('Executing simulation -----------------' + '--------------------------------------') + os.system("echo 'run; quit' | ./scsim -nc") + if debug: + print(' - end of simulation') + + + # ------------------------------------------------------------------------- + ## If called after Inst.Save() and Inst.Pattern() will build a Synopsys + # simulator + # + # 1 (optional) convert the netlist from vst to vhd through VASY + # (with "self.convert_to_vhdl") + # 2 create vhdl module sending the patterns + # (with "self.create_testbench") + # 3 create main vhdl which connect : the chip and the patterns block + # (with "self.create_run method") + # 4 run the simulator compilation (withe "self.compile") + # @remark Don't forget that you may need a "synopsys_sim.setup" file + # to configure Synopsys for the target library. + def build_simulator(self, debug=False, convert_vst=True, st=True): + if convert_vst: + self.convert_to_vhdl(st=st, debug=debug) + + if debug: + print ' - generate test bench and build simulator (Synopsys) ...' + try: + self._cell.pat + except AttributeError: + # On plante car ne fait pas sens sans pattern + raise Exception("build_simulator: paterns are mandatory") + self.create_testbench(self._cell.pat.get_interface(), + self._cell.pat.time_interval, + self._cell.pat.time_unit) + self.create_run(self._cell.pat.get_interface()) + self.compile(debug=debug) + + # ------------------------------------------------------------------------- + ## Convert the netlist vst to hierachical verilog + # + # + # We consider that this method is called after module.Save(), + # i.e. that the vst as been exported. + # + # 1. (optional) use VASY to convert from VST to VHDL + # 2. use Synopsys to convert from VHDL to VERILOG + # + # @remark this is very usefull to export stratus designs to Cadence + # SOC Encounter. + # + # @remark Creates a file named 'convert_to_verilog.cmd' (name can be + # changed with command_file parameter) + # + # @remark Create a directory named 'BG' (name can be changed with + # the library_dir parameter) + # + # @remark Don't forget that you may need a ".synopsys_dc.setup" file + # to configure Synopsys for the target library. + # + # @warning delete modulename_tb.vhd and modulename_run.vhd + def convert_vhdl2verilog(self, debug=False, + command_file='convert_to_verilog.cmd', + library_dir='BG', + convert_vst=True, + uniquify=True, + st=False): + # Debug messages + if debug: + print(' - converting vhdl to verilog (uses Synopsys, uniquify=%s) ...' + %uniquify) + + # Optionnal vst2vhd conversion + if convert_vst: + self.convert_to_vhdl(st=st, debug=debug) + + # We don't want the test bench components into the output verilog + os.system("rm %s_run.vhd %s_tb.vhd 2> /dev/null"% + (self._name,self._name)) + + # Write Synopsys command file ----------------------------------- + # First part + command_file = 'convert_to_verilog.cmd' + output = open(command_file, 'w') + output.write('sh mkdir %s\n' + 'define_design_lib %s -path ./%s\n' + 'analyze -library %s -format vhdl {\n'% + (library_dir,library_dir,library_dir,library_dir)) + output.close() + + # Add the vhd files names to the conversion script + # (as we use a shell command we need to close the command_file and + # reopen it after) + if (os.system("ls *.vhd >> %s" % command_file) != 0): + raise Exception("error : no vhd files found (missing conversion ?)") + + # End + output = open(command_file, 'a+') + output.write('}\n' + 'elaborate %s -architecture RTL -library %s\n' + %(self._name, library_dir)) + if uniquify: + output.write('uniquify\n') + output.write('write -hierarchy -format verilog -output %s.v\n' + 'exit\n'%self._name) + output.close() + + # Call synopsys to make the conversion -------------------------- + os.system('dc_shell -tcl_mode < %s' % command_file) diff --git a/stratus1/src/modules/patterns/utils.py b/stratus1/src/modules/patterns/utils.py new file mode 100644 index 00000000..8224d09b --- /dev/null +++ b/stratus1/src/modules/patterns/utils.py @@ -0,0 +1,616 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Ludovic NOURY | +# | Roselyne CHOTIN-AVOT | +# | E-mail : Ludovic.Noury@lip6.fr | +# | =============================================================== | +# | Py Module : "./__init__.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + +# ------------------------------------------------------ +# $Id: utils.py,v 1.3 2009/11/18 15:35:02 cobell Exp $ +# Author: LIP6/ASIM ludovic.noury@lip6.fr +# Contributor: Roselyne.Chotin-Avot@lip6.fr +# ------------------------------------------------------ +__all__ = ['strfix2float', 'str2int', 'str2uint', 'int2str', 'int2strhex', + 'float2strfix', 'runpat', 'LoadSig', 'MaskNumber', 'runsynop', + 'cout_cal'] + +import math +import re +from math import ceil +from os import system +from stratus import * + +# ------------------------------------------------------ +## @defgroup patterns_utils patterns.utils +# Module: conversion functions +# +# @todo add parameters checks everywhere ... +# +# @version $Id: utils.py,v 1.3 2009/11/18 15:35:02 cobell Exp $ + +# ------------------------------------------------------ +## Convert string to int list (with LSB at res[0]) +# +# @param val input string +# @return corresponding list +# +# @ingroup patterns_utils +def _str2list(val): + binlist = list(val) + binlist.reverse() + binlist = map(int, binlist) + return binlist + +# ------------------------------------------------------ +## Convert the binary representation of a CA2 signed fixed point +# number to the corresponding floating point number. +# +# @param val input string +# @param iwl integer word length +# @return corresponding floating point value +# @todo make a function of "1" as we also use it for PatRead ? +# @remark iwl includes sign bit. +# +# @ingroup patterns_utils +def strfix2float(val, iwl): + # 1. Convert string to int list (with LSB at binlist[0]) + binlist = _str2list(val) + + # 2. Get word length & fractional word length + wl = len(binlist) + fwl = wl-iwl + + # 3. Compute + res = -(2**(iwl-1)) * binlist[wl-1] + for i in range(wl-2, -1, -1): + res += binlist[i]*(2**(i-fwl)) + + # 4. Return + return res + +# ------------------------------------------------------ +## Convert the binary representation of a CA2 signed fixed point +# number to the corresponding int number. +# +# @remark Warning ! works only on signed numbers !! +# +# @param val input string +# @return corresponding int value +# +# @ingroup patterns_utils +def str2int(val): + # 1. Convert string to int list (with LSB at binlist[0]) + binlist = _str2list(val) + + # 2. Get word length + wl = len(binlist) + + # 3. Compute + res = -pow(2,wl-1) * binlist[wl-1] + for i in range(wl-1): + res += binlist[i]*(2**i) + + # 4. Return + return res + +# ------------------------------------------------------ +## Convert the binary representation of a CA2 unsigned fixed point +# number to the corresponding int number. +# +# @param val input string +# @return corresponding int value +# +# @ingroup patterns_utils +def str2uint(val): + # 1. Convert string to int list (with LSB at binlist[0]) + binlist = _str2list(val) + + # 2. Get word length + wl = len(binlist) + + # 3. Compute + res = 0 + for i in range(wl): + res += binlist[i]*(2**i) + + # 4. Return + return res + + +# ------------------------------------------------------ +## Convert an int value to the corresponding 2's complement binary +# string value on wl bits. +# +# We suppose that the machine representation of "value" is in 2's +# complement. Hence we just decode it with binary operations and +# put the result into a string. +# +# @param value int value to convert +# @param wl size of the binary output string : word length +# +# @ingroup patterns_utils +def int2str(value, wl): + res = "" + for pos in range(wl): + res = str( (value & 1L<>pos) + res + return res + +# ------------------------------------------------------ +## Convert an int on wl bit to the corresponding hexadecimal +# representation string. +# +# @param value int value to convert +# @param wl input value word size +# +# @ingroup patterns_utils +def int2strhex(value, wl): + mask = 2**wl-1 + format = '%%0%dx' %int(ceil(wl/4.)) + return format %(value & mask) + + +# ------------------------------------------------------ +## Convert a float value to the corresponding signed fixed point +# string on wl bit and with an integer word size of iwl bits. +# +# @param value int value to convert +# @param wl word length +# @param iwl interger word length (including sign bit) +# +# @ingroup patterns_utils +def float2strfix(value, wl, iwl): + # Put into an int corresponding fixed point number + fixed_value = int(value*2**(wl-iwl)) + + # Convert the number to string + return int2str(fixed_value, wl) + +# ------------------------------------------------------ +## Pattern simulation with asimut +# +# Run netlist simulation with Asimut using the following parameters: +# - options (see option parameter), +# - netlist filename: \e name.vst, +# - pattern filename: \e name.pat, +# - results filename: \e name_res.pat . +# +# @param name netlist name, +# @param options asimut command line options (optional, default empty), +# @param stdout asimut stout (optional, default False), +# @param stderr asimut stderr (optional, default True). +# @return returns asimut exit value. +# @todo Add exception for simulation error. +# +# @ingroup patterns_utils +def runpat(name_vst, name_pat, options='', stdout=False, stderr=True): + cmd_str = ('asimut %s %s %s %s') % (options, name_vst, name_pat, name_pat+'_res') + + if not stdout: + cmd_str += ' > /dev/null' + if not stderr: + cmd_str += ' 2> /dev/null' + + result = system(cmd_str) + if not result : print "Simulation OK" + + return result + +## Return interface connectors dictionnary where key is the conector's name +# and value the connector's format ('B' or 'X' or 'O') +# +# @param name is the tested Stratus model reference name +# @return connectors dictionnary +def get_interface_format(name): + file = open(name+'.pat', 'r') + dict = {} + for line in file : + # stop at end of the declaration + if re.compile(r"^begin$", re.I).search(line): + break; + # skip blank line + if re.compile(r"^ *$", re.I).search(line): + continue + # get name and format + res = re.search("[in|out]+ *(\w*).*([X|B|O]) *;*",line).group(1,2) + dict[res[0]] = res[1] + file.close() + return dict + +## Return interface connectors list +# +# @param cell tested Stratus model reference +# @return connectors list +# +# @ingroup patterns_utils +def get_interface(cell): + l = [] + + dict = get_interface_format(cell._name) + + if (cell==None): + raise Exception("get_interface() " + "cell reference no given thus the cell parameter is mandatory.") + + # 1. Clocks + for port in cell._st_cks: + if isinstance(port, CkIn): + port._format = dict[port._name] + l.append(port) + + # 2. Inputs + for port in cell._st_ports: + if isinstance(port, SignalIn): + port._format = dict[port._name] + l.append(port) + + # 3. Outputs + for port in cell._st_ports: + if isinstance(port, SignalOut): + port._format = dict[port._name] + l.append(port) + + # 4. VDDs + for port in cell._st_vdds: + if isinstance(port, VddIn): + port._format = dict[port._name] + l.append(port) + + # 5. VSSs + for port in cell._st_vsss: + if isinstance(port, VssIn): + port._format = dict[port._name] + l.append(port) + + return l + +# ------------------------------------------------------ +## Pattern simulation with synopsys +# +# @param cell tested Stratus model reference +# @param vasy if vhdl is obtained from Alliance vst netlist (optional, default False) +# @param time_interval between pattern (optional, default 20) +# @param time_unit for simulation, valid values are ps, ns, us and ms (optional, default 'ns') +# @param debug informations during compilation and simulation (optional, default False) +# @param downto to have vector in MSB to LSB format (optional, default True) +# @param logic to have a time_interval delay between inputs and outputs affectations for logical simulation (optional, default False) +# +# @ingroup patterns_utils +def runsynop(cell, vasy = False, time_interval = 20, time_unit = 'ns', debug = False, downto = True, logic = False): + from synopsys import Synopsys + # Convert to VHDL + syn = Synopsys(cell) + if vasy : + syn.convert_to_vhdl() + + # Create testbench + syn.create_testbench(get_interface(cell), time_interval, time_unit, debug, downto, logic) + + # Create testbench and block instance + syn.create_run(get_interface(cell), debug, downto) + + # Compile + syn.compile(debug=True) + + # Run simulation + syn.run() + + del syn + +# ------------------------------------------------------ +## Create a samples iterator from an input file +# +# Return a iterator from the specified input signal. The iterator +# output format can be : +# - LoadSig.FIX the corresponding fixed point number converted back +# to float, +# - LoadSig.STRING the binary representation of the fixed point number +# into a string, +# - LoadSig.FLOAT the original floating point number without any +# conversion. +# - LoadSig.INT the rounded int number +# +# @remark the input file has one floating point number per line, +# comments begin with # +# +# @remark Python don't support multiple constructors without hack, so +# we prefer not to use them. +# (see: http://mail.python.org/pipermail/python-list/2005-May/280116.html) +# +# @ingroup patterns_utils +class LoadSig: + # Class attributes ------------------------------------- + ## Used a constructor parameter, select fixed point output + FIX = 0 + ## Used a constructor parameter, select binary string output + STRING = 1 + ## Used a constructor parameter, select unconverted float output + FLOAT = 2 + ## Used a constructor parameter, select rounded int output + INT = 3 + + # Private attributes ----------------------------------- + # @var _f file object + # @var _it input file object iterator + # @var _wl word length + # @var _iwl input word length + # @var _mode output format (FIX|STRING|FLOAT|INT) + + # ------------------------------------------------------ + ## Constructor + # + # @param filename input filename, + # @param connector stratus connector, + # @param iwl integer word length, + # @param mode set iterator output format (LoadSig.FIX | + # LoadSig.STRING | LoadSig.FLOAT | LoadSig.INT). + def __init__(self, filename, connector, iwl, mode): + self._f = open(filename, 'r') + self._it = iter(self._f) + self._wl = connector._arity + self._iwl = iwl + self._mode = mode + + # ------------------------------------------------------ + # Activate Iterator + def __iter__(self): + return self + + # ------------------------------------------------------ + # Subfonction used by next(), convert a line to the selected output + # format. + def _make_output(self,line): + r = float2strfix(float(line), self._wl, self._iwl) + + if self._mode == self.STRING: + return r + elif self._mode == self.FIX: + return strfix2float(r , self._iwl) + elif self._mode == self.FLOAT: + return float(line) + elif self._mode == self.INT: + return int(round(float(line))) + + # ------------------------------------------------------ + ## Return next sample + def next(self): + line = self._it.next() + while re.compile("^#").search(line): + line = self._it.next() + return self._make_output(line) + +# ------------------------------------------------------------------------- +## Create an iterator for a pattern input signal values. +# +# The iterator will return at each call the next input signal value in +# the form of the corresponding unsigned int. The output value +# sequence depends on the input signal word length (wl): +# - wl=MAX_IT: use Pattern Mask Generator (PMG) to reduce the number +# of values. +# +# The PMG splits the number into 3 parts: +# - a middle fixed part where all bits have the same value (0 or 1), +# - 2 varying parts (called masks, one for msb and one for lsb) with +# the same fixed width. +# +# At each call, the iterator : +# -# increments the masks to obtain all the possible values, +# -# add these 2 masks around the middle part to obtain the final +# value, +# -# returns the final value. +# +# @todo Add constructor parameters check (raise exception if +# width<=mask_width). +# @todo Check if there is no errors during << witch could be corrected +# by using long int. +# +# @ingroup patterns_utils +class MaskNumber: + # Class attributes ----------------------------------------------- + ## Maximal signal width for exhaustive generation + MAX_IT = 9 + + # Private instance attributes ------------------------------------ + ## @var _mask_value + # Varying part value. + + ## @var _middle + # Central part value. + + ## @var _currrent + # Current value of the number. + + ## @var _mask_width + # Mask width. + + ## @var _width + # Width of the signal to affect. + + ## @var _exhaustiv + # If False force using PMG even if wl= width: + raise Exception('MaskNumber.__init__: ' + 'mask_width(%d)*2 >= width(%d)' % (mask_width, width)) + self._mask_max_value = 2**(2*mask_width) - 1 + + self._mask_lsb = 2**mask_width-1 + self._mask_msb = (2**mask_width-1) << mask_width + self._dec_val = self._width - 2 * self._mask_width + + # ---------------------------------------------------------------- + # Activate Iterator + def __iter__(self): + return self + + # ---------------------------------------------------------------- + def _next_exhaustive(self): + if self._mask_value == self._mask_max_value: + # stop generation at last value + raise StopIteration + else: + # increment each value by 1 + self._mask_value += 1 + self._current = self._mask_value + return self._mask_value + + # ---------------------------------------------------------------- + def _next_pmg(self): + if self._mask_value == self._mask_max_value: + if self._middle != 0: + # Stop generation when all the mask value are obtained + # for both value (0 and 1) of the central part. + raise StopIteration + else: + # When all the mask value are obtained for the 0 central value + # we pass to the 1 central value. + self._mask_value = -1 + self._middle = 2**self._width - 1 + self._middle = (self._middle ^ + ((self._mask_msb * 2**self._dec_val) + self._mask_lsb)) + value = 0 + # 2.a Adds 1 to the mask value + self._mask_value = self._mask_value + 1 + # 2.b Constructs msb and lsb parts of the mask value + lsb = self._mask_value & self._mask_lsb + msb = (self._mask_value & self._mask_msb) * 2**self._dec_val + # 2.c Place msb and lsb around central part + value = msb + self._middle + lsb + # 2.d Return the obtained value + self._current = value + return value + + # ---------------------------------------------------------------- + ## Return next sample + # + # @param self The object pointer. + # @return next sample. + def next(self): + # Signal width inferior to MAX_IT => exhaustive pattern generation. + # else we use PMG. + if (self._width < self.MAX_IT) and (self._exhaustiv): + return self._next_exhaustive() + else: + return self._next_pmg() + + # ---------------------------------------------------------------- + ## Reset the generator to the first value + # + # @param self The object pointer. + def reset(self): + self._mask_value = -1 + self._middle = 0 + self._current = -1 + + # ---------------------------------------------------------------- + ## Return current sample + # + # @param self The object pointer. + # @return current sample. + def current(self): + return self._current + +# ------------------------------------------------------ +## Extend a given signed number +# @param val is the number to extend +# @param width is the width in bits of the number +# @return the extended value +def extend(val,width): + # if the number is negative extend the sign ('1') + if val >= 2**(width-1): + mask = ~(2**width-1) + return (val | mask) + # else return the number + else: + return val + +# ------------------------------------------------------ +## Calculation of the cout's value in case of addition +# @param width is the width in bits of the number +# @param vali0 is the value of the first operand +# @param vali1 is the value of the second operand +# @param valCin is the value of the input carry +# @return the corresponding value of cout +def cout_cal(width,valA,valB,valCin): + mask = 2**width - 1 + val = (valA & mask) + (valB & mask) + valCin + if val >= 2**width: + return 1 + else: + return 0 diff --git a/stratus1/src/stratus/CMakeLists.txt b/stratus1/src/stratus/CMakeLists.txt new file mode 100644 index 00000000..ebc64ce0 --- /dev/null +++ b/stratus1/src/stratus/CMakeLists.txt @@ -0,0 +1,36 @@ + + set ( pysources ${CMAKE_CURRENT_SOURCE_DIR}/st_bool.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_cat.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_comp.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_const.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_extend.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_func_gen_wallace.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_generate.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_getrealmodel.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_instance.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_model.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_mult_blocs.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_mult_matrix.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_mult.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_mux.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_net.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_param.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_parser.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_placeAndRoute.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_placement.py + ${CMAKE_CURRENT_SOURCE_DIR}/stratus.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_ref.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_shifter.py + ${CMAKE_CURRENT_SOURCE_DIR}/st_slansky.py + ${CMAKE_CURRENT_SOURCE_DIR}/util_Const.py + ${CMAKE_CURRENT_SOURCE_DIR}/util_Defs.py + ${CMAKE_CURRENT_SOURCE_DIR}/util_Gen.py + ${CMAKE_CURRENT_SOURCE_DIR}/util_Misc.py + ${CMAKE_CURRENT_SOURCE_DIR}/util_Place.py + ${CMAKE_CURRENT_SOURCE_DIR}/util.py + ${CMAKE_CURRENT_SOURCE_DIR}/util_Route.py + ${CMAKE_CURRENT_SOURCE_DIR}/util_Shift.py + ${CMAKE_CURRENT_SOURCE_DIR}/util_uRom.py + ) + + install ( FILES ${pysources} DESTINATION ${PYTHON_SITE_PACKAGES}/stratus ) diff --git a/stratus1/src/stratus/st_bool.py b/stratus1/src/stratus/st_bool.py new file mode 100644 index 00000000..277a704f --- /dev/null +++ b/stratus1/src/stratus/st_bool.py @@ -0,0 +1,159 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_bool.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +from st_parser import I, I0, I2, I3, A, CK, CMD, CMD0, CIN, Q, NQ, S + +class Bool ( Model ) : + + def __init__ ( self, name, param, inout ) : + Model.__init__ ( self, name, param ) + + self.m = self._param['model'] + self.realM = self._param['realModel'] + + self.dictInOut = inout + + if 'nbit' not in param : self.nbit = 1 + else : self.nbit = self._param['nbit'] + + if self.nbit < 1 : + err = "\n[Stratus ERROR] " + self.m + " : the number of bits must be greater than 0.\n" + raise err + + def Interface ( self ) : + if self.m in I : + self._i = SignalIn ( "i", self.nbit ) + elif self.m in I0 : + self._i0 = SignalIn ("i0", self.nbit ) + self._i1 = SignalIn ("i1", self.nbit ) + elif self.m in A : + self._a = SignalIn ( "a", self.nbit ) + self._b = SignalIn ( "b", self.nbit ) + + if self.m in I2 : + self._i2 = SignalIn ("i2", self.nbit ) + if self.m in I3 : + self._i3 = SignalIn ("i3", self.nbit ) + + if self.m in CMD : + self._cmd = SignalIn ( "cmd", 1 ) + elif self.m in CMD0 : + self._cmd0 = SignalIn ( "cmd0", 1 ) + self._cmd1 = SignalIn ( "cmd1", 1 ) + + if self.m in CK : + self._ck = CkIn ( "ck" ) + + if self.m in CIN : + self._cin = SignalIn ( "cin", self.nbit ) + + if self.m in Q : + self._q = SignalOut ( "q", self.nbit ) + elif self.m in NQ : + self._nq = SignalOut ( "nq", self.nbit ) + elif self.m in S : + self._sout = SignalOut ( "sout", self.nbit ) + self._cout = SignalOut ( "cout", self.nbit ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + for i in range ( self.nbit ) : + boolMap = { self.dictInOut['vdd'] : self._vdd + , self.dictInOut['vss'] : self._vss + } + + if self.m in I : + boolMap[self.dictInOut['i']] = self._i[i] + elif self.m in I0 : + boolMap[self.dictInOut['i0']] = self._i0[i] + boolMap[self.dictInOut['i1']] = self._i1[i] + elif self.m in A : + boolMap[self.dictInOut['a']] = self._a[i] + boolMap[self.dictInOut['b']] = self._b[i] + + if self.m in I2 : + boolMap[self.dictInOut['i2']] = self._i2[i] + if self.m in I3 : + boolMap[self.dictInOut['i3']] = self._i3[i] + + if self.m in CIN : + boolMap[self.dictInOut['cin']] = self._cin[i] + if self.m in CMD : + boolMap[self.dictInOut['cmd']] = self._cmd + elif self.m in CMD0 : + boolMap[self.dictInOut['cmd0']] = self._cmd0 + boolMap[self.dictInOut['cmd1']] = self._cmd1 + if self.m in CK : + boolMap[self.dictInOut['ck']] = self._ck + + if self.m in Q : + boolMap[self.dictInOut['q']] = self._q[i] + elif self.m in NQ : + boolMap[self.dictInOut['nq']] = self._nq[i] + elif self.m in S : + boolMap[self.dictInOut['sout']] = self._sout[i] + boolMap[self.dictInOut['cout']] = self._cout[i] + + Inst ( "%s" % self.realM + , map = boolMap + ) + + def GetParam ( cls ): + global BV + from st_parser import BV + if BV == [] : InitBV() + + return {'nbit' : 'integer', 'model' : BV} + + GetParam = classmethod ( GetParam ) diff --git a/stratus1/src/stratus/st_cat.py b/stratus1/src/stratus/st_cat.py new file mode 100644 index 00000000..5ba7962c --- /dev/null +++ b/stratus1/src/stratus/st_cat.py @@ -0,0 +1,104 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_cat.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from Hurricane import * + +from st_net import * + +import types + +def Cat ( *nets ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + nb = len ( cell._TAB_NETS_CAT ) + + cell._TAB_NETS_CAT += [Signal ( "net_cat_%d" % nb )] + + netToCat = cell._TAB_NETS_CAT[nb] + + if type ( nets[0] ) == types.ListType : nets = nets[0] + + # Creation of the inversed tab + netstries = [] + for net in nets : netstries.insert ( 0, net ) + + if ( "_arity" not in net.__dict__ ) or ( "_real_net" not in net.__dict__ ) or ( "_ind" not in net.__dict__ ) : + err = "\n[Stratus ERROR] Cat : Problem of parameter.\n" + raise err + + # Construction of the tab _to_cat if needed + if not ( len ( netToCat._to_cat ) ) : + for net in netstries : + for l in range ( net._arity ) : netToCat._to_cat.append ( 0 ) + + # Initialisation of _to_cat + for net in netstries : + if net._real_net : realNet = net._real_net + else : realNet = net + + nbit1 = net._ind + if ( '_reverse' in net.__dict__ ) and ( net._reverse ) : + nbit2 = net._ind - net._arity + pas = -1 + else : + nbit2 = net._ind + net._arity + pas = 1 + + for l in range ( nbit1, nbit2, pas ) : + netToCat._to_cat[netToCat._arity] = [realNet, l] + netToCat._arity += 1 + + # Initialisation of _hur_net if in hurricane mode + if netToCat._st_cell._hur_cell : netToCat._hur_net += [realNet._hur_net[l]] + + return netToCat diff --git a/stratus1/src/stratus/st_comp.py b/stratus1/src/stratus/st_comp.py new file mode 100644 index 00000000..1466fc25 --- /dev/null +++ b/stratus1/src/stratus/st_comp.py @@ -0,0 +1,198 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_comp.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +import re, types + +class Comp ( Model ) : + + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + + self.nbit = param['nbit'] + self.nb = param['nb'] + self.egal = param['egal'] + + if self.egal : self.func = "Eq" + else : self.func = "Ne" + + # Error : if net is not a string + if type ( self.nb ) != types.StringType : + err = "\n[Stratus ERROR] " + self.func + " : the argument must be a string.\n" + raise err + + def Interface ( self ) : + self.netIn = SignalIn ( "netin", self.nbit ) + self.netOut = SignalOut ( "netout", 1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + netConst = Signal ( "netconst" ) + + extendConst = Signal ( "extendconst", self.nbit ) + tempXor = Signal ( "tempxor", self.nbit ) + + netConst <= self.nb + + # Error : if the number is too big for the arity of the net + if netConst._arity > self.nbit : + err = "\n[Stratus ERROR] " + self.func + " : the number does not match with the net's lenght.\n" + raise err + # Otherwise, completion of the net + elif netConst._arity < self.nbit : extendConst <= netConst.Extend ( self.nbit, 'zero' ) + else : netConst.Alias ( extendConst ) + + # Xor bit per bit + tempXor <= self.netIn ^ extendConst + + if self.nbit > 1 : + if self.egal : + Generate ( "st_comp.BoolToOne", "bool_to_one_%s_%dbits" % ( "nor", tempXor._arity ), param = { 'nbit' : tempXor._arity, 'func' : "Nor" } ) + Inst ( "bool_to_one_%s_%dbits" % ( "nor", tempXor._arity ) + , map = { 'i' : tempXor + , 'q' : self.netOut + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + else : + Generate ( "st_comp.BoolToOne", "bool_to_one_%s_%dbits" % ( "or", tempXor._arity ), param = { 'nbit' : tempXor._arity, 'func' : "Or" } ) + Inst ( "bool_to_one_%s_%dbits" % ( "or", tempXor._arity ) + , map = { 'i' : tempXor + , 'q' : self.netOut + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + else : + if self.egal : self.netOut <= ~tempXor + else : self.netOut <= tempXor + + def GetModelName ( cls, param ) : + modelName = "comparator" + + modelName += "_" + + if param['egal'] : modelName += "eq" + else : modelName += "ne" + + modelName += "_" + modelName += param['nb'] + + return modelName + + GetModelName = classmethod ( GetModelName ) + + def GetParam ( cls ): + + return {'nbit' : 'integer', 'nb' : 'StringInteger' , 'egal' : 'boolean'} + + GetParam = classmethod ( GetParam ) + +class BoolToOne ( Model ) : + + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + + self.nbit = param['nbit'] + + if self.nbit < 2 : raise "\n[Stratus ERROR] booltoone : the number of bits of the inputs must be greater than 1.\n" + + self.func = param['func'] + + if self.func not in ( "And", "Nand", "Or", "Nor", "Xor", "Nxor" ) : + err = "\n[Stratus ERROR] " + self.func + " : the argument must be a string.\n" + raise err + + def Interface ( self ) : + self._in = SignalIn ( "i", self.nbit ) + self._q = SignalOut ( "q", 1 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + nbStages = log2(self.nbit) + + def bool_function ( net1, net2 ) : + if self.func == 'And' : return ( net1 & net2 ) + elif self.func == 'Nand' : return ~( net1 & net2 ) + elif self.func == 'Or' : return ( net1 | net2 ) + elif self.func == 'Nor' : return ~( net1 | net2 ) + elif self.func == 'Xor' : return ( net1 ^ net2 ) + elif self.func == 'Nxor' : return ~( net1 ^ net2 ) + + out = {} + out[0] = self._in[0] + for i in range ( 1, self.nbit ) : + out[i] = Signal("out%d" % i , 1 ) + out[i] <= bool_function ( out[i-1], self._in[i] ) + self._q <= out[self.nbit-1] + + def GetModelName ( cls, param ) : + modelName = str(param['func']) + + modelName += "_" + modelName += str(param['nbit']) + modelName += "bits_to one" + + return modelName + + GetModelName = classmethod ( GetModelName ) + + def GetParam ( cls ): + + return {'nbit' : 'integer', 'func' : ["And", "Nand", "Or", "Nor", "Xor", "Nxor"]} + + GetParam = classmethod ( GetParam ) + diff --git a/stratus1/src/stratus/st_const.py b/stratus1/src/stratus/st_const.py new file mode 100644 index 00000000..dd8da513 --- /dev/null +++ b/stratus1/src/stratus/st_const.py @@ -0,0 +1,199 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_const.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +from Hurricane import * + +from st_net import * +from st_instance import Inst +from st_generate import Generate + +import types + +################## +def One ( nbit ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n" + + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "one_%d" % num_net, nbit )] + + # "1 bit constant" => directly instanciate the virtual cell "One" cell + # "> 1 bit constant" => generate a model +# if nbit == 1: +# inst_name = "one" +# else: + inst_name = "one_%dbits" % nbit + Generate ( "One", inst_name, param = { 'nbit' : nbit } ) + Inst ( inst_name + , map = { 'q' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + return cell._TAB_NETS_OUT[num_net] + +################### +def Zero ( nbit ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n" + + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "zero_%d" % num_net, nbit )] + + # "1 bit constant" => directly instanciate the virtual cell "Zero" cell + # "> 1 bit constant" => generate a model +# if nbit == 1: +# inst_name = "zero" +# else: + inst_name = "zero_%dbits" % nbit + Generate ( "Zero", inst_name, param = { 'nbit' : nbit } ) + Inst ( inst_name + , map = { 'nq' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + return cell._TAB_NETS_OUT[num_net] + +###################### +class Constant ( Model ) : + + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + + self.string = Constant.getString ( param ) + self.nbit = len ( self.string ) + + def Interface ( self ) : + self.outPut = SignalOut ( "output0", self.nbit ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + i = 0 + for letter in self.string : + if letter == "1" : self.outPut[i] <= One ( 1 ) + else : self.outPut[i] <= Zero ( 1 ) + i += 1 + + def GetModelName ( cls, param ) : + modelName = "constant" + + modelName += "_" + modelName += param['nb'] + + return modelName + + GetModelName = classmethod ( GetModelName ) + + def GetString ( param ) : + nb = param['nb'] + + # Error : if nb is not a string + if type ( nb ) != types.StringType : raise "\n[Stratus ERROR] Constant : the argument must be a string.\n" + + ### String representing a binary number ( from the LSB to the MSB ) ### + bin = re.search ( "0[bB]([0-1]+)", nb ) + hexa = re.search ( "0[xX]([0-9,A-F]+)", nb ) + oct = re.search ( "0[oO]([0-7]+)", nb ) + dec = re.search ( "([0-9]+)", nb ) + + # The parameter is a binary number + if bin : + result = bin.group(1) + string = "" + for i in range ( len (result)-1, -1, -1 ) : string += result[i] + # The parameter is an hexadecimal number + elif hexa : + result = hexa.group(1) + string = "" + raise "Hexa not ready yet." + # The parameter is an octal number + elif oct : + result = oct.group(1) + string = "" + raise "Octal not ready yet." + # The parameter is a decimal number + elif dec : + num = int ( nb ) + string = "" + + if not num : + string = "0" + else : + while num : + num2 = num + num /= 2 + if ( num * 2 ) != num2 : string += "1" + else : string += "0" + + # Error if the string does not belong to the previous categories + else : + raise "\n[Stratus ERROR] Const : the argument must be a string representing a number in decimal, binary (0b) or hexa (0x).\n" + + return string + + GetString = staticmethod ( GetString ) + + def GetParam ( cls ): + + return {'nb' : 'StringInteger'} + + GetParam = classmethod ( GetParam ) diff --git a/stratus1/src/stratus/st_extend.py b/stratus1/src/stratus/st_extend.py new file mode 100644 index 00000000..1fbd5a13 --- /dev/null +++ b/stratus1/src/stratus/st_extend.py @@ -0,0 +1,88 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_extend.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +from stratus import * + +class Extend ( Model ) : + + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + self.nbit0 = param['nbit0'] + self.nbit1 = param['nbit1'] + + self.type = param['type'] + + def Interface ( self ) : + self.i = SignalIn ( "i", self.nbit0 ) + self.o = SignalOut ( "o", self.nbit1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + if self.nbit0 > 1 : self.o[self.nbit0-1:0] <= self.i.Buffer() + else : self.o[0] <= self.i.Buffer() + + if self.type == 'zero' : + if (self.nbit1-1) == self.nbit0 : self.o[self.nbit0] <= Zero ( 1 ) + else : self.o[self.nbit1-1:self.nbit0] <= Zero ( self.nbit1 - self.nbit0 ) + elif self.type == 'one' : + if (self.nbit1-1) == self.nbit0 : self.o[self.nbit0] <= One ( 1 ) + else : self.o[self.nbit1-1:self.nbit0] <= One ( self.nbit1 - self.nbit0 ) + elif self.type == 'signed' : + for i in range ( self.nbit0, self.nbit1 ) : self.o[i] <= self.i[self.nbit0-1].Buffer() + else : + raise "\n[Stratus ERROR] Extend : type must be \'zero\', \'one\' or \'signed\'.\n" + + def GetParam ( cls ): + + return {'nbit0' : 'integer', 'nbit1' : 'integer', 'type' : ["zero", "one", "signed"]} + + GetParam = classmethod ( GetParam ) + diff --git a/stratus1/src/stratus/st_func_gen_wallace.py b/stratus1/src/stratus/st_func_gen_wallace.py new file mode 100644 index 00000000..bc3a670d --- /dev/null +++ b/stratus1/src/stratus/st_func_gen_wallace.py @@ -0,0 +1,340 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_func_gen_wallace.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +from math import * + +import string + +################################################################ +def genWallace ( cell, _tabIn, matrixIn ) : + FA = 0 + HA = 1 + tabIn = transpose ( _tabIn ) + mylistTransposed = transpose ( matrixIn[:] ) + nbNumbers = len ( _tabIn ) + + tabtmp = wallace ( mylistTransposed ) + tabFAHA = tabtmp[0] + + count = 0 + choix = 0 + + tabInput = [] + for i in range ( len ( tabIn ) ) : + tabInput.append ( [] ) + + for j in range ( len ( tabIn[i] ) ) : + if tabIn[i][j] : + choix = 1 + count = count + 1 + tabInput[i].append ( Signal ( "tabinput_%d_%d" % ( i, j ) , 1 ) ) + + tabInput[i][len(tabInput[i])-1] = tabIn[i][j] + + if choix == 0 : tabInput = tabIn + + if nbNumbers > 2 and len ( tabFAHA ) > 0 : + for i in range ( len ( tabInput ) ) : + for k in range ( tabInput[i].count ( 0 ) ) : tabInput[i].pop ( tabInput[i].index ( 0 ) ) + + for i in range ( len ( tabFAHA[0] ) - len( tabInput ) ) : tabInput = [[]] + tabInput + + colOut = [] + reportedCarries = [] + + for i in range ( len ( tabFAHA ) ) : + for jinv in range ( len ( tabFAHA[i] ) ) : + j = len(tabFAHA[i]) - 1 - jinv + jj = j + + t = tabFAHA[i][j] + reportCarries = [] + col = [] + col = tabInput[jj] + reportedCarries + colOut = [] + + for ii in range ( t[FA] ) : + listFA = getInputs ( col, 3 ) + + colOut.append ( Signal ( "colout_%d_%d_%d" % ( i, jinv, ii ), 1 ) ) + reportCarries.append ( Signal ( "report_%d_%d_%d" % ( i, jinv, ii ), 1 ) ) + + Generate ( 'Fulladder', "full_adder", param = {'nbit' : 1} ) + Inst ( 'full_adder' + , map = { 'a' : col[listFA[0]] + , 'b' : col[listFA[1]] + , 'cin' : col[listFA[2]] + , 'sout' : colOut[ii] #[0] + , 'cout' : reportCarries[ii][0] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + col.pop ( listFA[2] ) + col.pop ( listFA[1] ) + col.pop ( listFA[0] ) + + sizeReportCarries = len ( reportCarries ) + sizeColOut = len ( colOut ) + + for ii in range ( t[HA] ) : + listHA = getInputs ( col, 2 ) + + colOut.append ( Signal ( "colout_%d_%d_%d" % ( i, jinv, ii+t[FA]), 1 ) ) + reportCarries.append ( Signal ( "report_%d_%d_%d" % ( i, jinv, ii+t[FA]), 1 ) ) + + Generate ( 'Halfadder', 'half_adder', param = {'nbit ': 1} ) + Inst ( 'half_adder' + , map = { 'a' : col[listHA[0]] + , 'b' : col[listHA[1]] + , 'sout' : colOut[sizeColOut + ii] #[0] + , 'cout' : reportCarries[sizeReportCarries + ii][0] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + col.pop(listHA[1]) + col.pop(listHA[0]) + + for ii in range ( len ( colOut ) ) : col = col + [colOut[ii][0]] + + for ii in range ( len ( reportCarries ) ) : + tmp = reportCarries[ii][0] + reportCarries[ii] = tmp + + tabInput[jj] = col[:] + + reportedCarries = reportCarries[:] + + for i in range ( len ( tabInput ) ) : + for k in range ( tabInput[i].count ( 0 ) ): tabInput[i].pop ( tabInput[i].index ( 0 ) ) + + sizeTabInput = len ( tabInput ) + + output0 = Signal ( "output0", sizeTabInput ) + output1 = Signal ( "output1", sizeTabInput ) + + for j in range ( sizeTabInput ) : + jj = sizeTabInput -1 -j + + if len ( tabInput[j] ) == 0 : + output0[jj] <= Zero(1) + output1[jj] <= Zero(1) + + elif len ( tabInput[j] ) == 1 : + output0[jj] <= tabInput[j][0].Buffer() + output1[jj] <= Zero(1) + + elif len ( tabInput[j] ) > 1 : + output0[jj] <= tabInput[j][0].Buffer() + output1[jj] <= tabInput[j][1].Buffer() + + return [sizeTabInput,output0,output1] + +################################################################ +def getInputs ( lst, nb ) : + lResult = [] + sizeList = len(lst) + i = 0 + + while nb > 0 and i < sizeList: + if lst[i] : + lResult = lResult + [i] + nb = nb -1 + i = i+1 + + return lResult + +################################################################ +def suite_dadda ( iValue ) : + Un = 2 + Un_1 = 2 + + while Un < iValue : + aux = (3 * Un_1) / 2 + Un_1 = Un + Un = aux + + return Un_1 + +################################################################ +def transpose ( lValue ) : + ltmp = [] + + nbCol = len(lValue[0]) + nbLine = len(lValue) + + for j in range(nbCol): + ltmp2 = [] + for i in range ( nbLine ) : ltmp2.append ( lValue[i][j] ) + + ltmp.append ( 0 ) + ltmp[j] = ltmp2 + + return ltmp + +################################################################ +def find_first_zero ( lValue ) : + i_ = 0 + + for i_ in range (len ( lValue ) ) : + if lValue[i_] == 0 : return i_ + + return -1 + +################################################################ +def wallace_1level ( lMat, lAdders ) : + + lMatrice = lMat[:] + + for j in range(len(lMatrice)): + lAdders.append([0]) + + hmax = max_list(lMatrice) + umax = suite_dadda(hmax) + + carries = [] + + for j in range(len(lMatrice)): + i=len(lMatrice)-1-j + + nb_FA = 0 + nb_HA = 0 + report_carries = [] + + delta = size_list(lMatrice[i]) - umax + nbToDel = delta + len(carries) + + if(nbToDel > 0): + nb_FA = nbToDel/2 + nb_HA = nbToDel%2 + else: + nb_FA = 0 + nb_HA = 0 + + for k in range(nb_FA + nb_HA) : report_carries = report_carries + [1] + + lAdders[i] = [nb_FA, nb_HA] + + nb = size_list(lMatrice[i]) + + for k in range(len(carries)): + ii = find_first_zero(lMatrice[i]) + + if(ii == -1): + (lMatrice[i]).append(1) + else: + lMatrice[i].remove(0) + lMatrice[i].insert(ii,1) + + for k in range(nbToDel ): + (lMatrice[i]).remove(1) + (lMatrice[i]).append(0) + + carries = report_carries + + if(len(carries) > 0 ): + for i in range( len(lMatrice[0]) - len(carries) ) : carries = carries + [0] + + lMatrice = [carries] + lMatrice + + return lMatrice + +#------------------------------------------------------------------------ +def wallace ( lValue ) : + ltmp=lValue[:] + + nbNumbers = len(lValue[0]) + + listAdders = [] + + counter = 0 + + while max_list(ltmp)>2: + listAdders.append([0]) + listAdders[counter] = [] + + ltmp = wallace_1level(ltmp,listAdders[counter]) + counter = counter +1 + + if(nbNumbers>2): + mmax = 0; + for i in range(len(listAdders)): + if len(listAdders[i]) > mmax : mmax = len(listAdders[i]) + + for i in range(len(listAdders)) : + while (mmax - len(listAdders[i])) > 0 : listAdders[i] = [[0,0]] + listAdders[i] + + if(nbNumbers>2 and len(listAdders) > 0) : return [listAdders,ltmp] + else : return [[],lValue] + +#------------------------------------------------------------------------ +def size_list ( lValue ) : + count = 0 + + for i in range ( len ( lValue ) ) : + if ( lValue[i] == 1 ) : count = count + 1 + + return count + +#------------------------------------------------------------------------ +def max_list ( lValue ) : + nbmax = 0 + + for j in range ( len ( lValue ) ) : + nb = size_list ( lValue[j] ) + + if nb > nbmax : nbmax = nb + + return nbmax diff --git a/stratus1/src/stratus/st_generate.py b/stratus1/src/stratus/st_generate.py new file mode 100644 index 00000000..87ec99fc --- /dev/null +++ b/stratus1/src/stratus/st_generate.py @@ -0,0 +1,115 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_generate.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from Hurricane import * +from CRL import * + +from st_model import Model, MODELMAP +from st_getrealmodel import GetRealModel, InitBV + +import sys, re, types, os + +def Generate ( model_name, inst_name, param = {} ) : + global CELLS, FRAMEWORK, MODEL_MAP + from st_model import CELLS, FRAMEWORK + cell = CELLS[-1] + + if '_vbe' in cell.__dict__ : param['behavioral'] = cell._vbe + + # Error : if the model is not a string + if type ( model_name ) != types.StringType : + err = "\n[Stratus ERROR] Generate : the model must be described in a string.\n" + raise err + if type ( inst_name ) != types.StringType : + err = "\n[Stratus ERROR] Generate : the model must be described in a string.\n" + raise err + + # Error : spaces are forbidden + if re.search ( " ", inst_name ) : + err = "\n[Stratus ERROR] Generate : " + inst_name + " the name of the model \"" + model_name + "\" can not contain a space.\n" + raise err + # Warning : the name can not contain capitalized letters + if re.search ( "[A-Z]", inst_name ) : + print "[Stratus Warning] Generate : Upper case letters are not supported, the name", inst_name, "is lowered." + inst_name = inst_name.lower() + + # Check if the model does already exist + hur_masterCell = FRAMEWORK.getCell ( inst_name, Catalog.State.Views ) + + st_masterCell = None + for c in cell._underCells : + if inst_name == c._name : st_masterCell = c + + # Creation of model not found neither in the database nor in the files + if not ( hur_masterCell or st_masterCell ) : + cell._model_map[inst_name] = [model_name, param] + + realModele = None + inout = None + + global BVg + from st_parser import BVg + if BVg == [] : InitBV() + + if model_name in BVg : realModele, inout = GetRealModel ( model_name.lower() ) + + st_masterCell = cell.ModelCreation ( model_name, inst_name, param, cell._hierarchy+1, realModele, inout ) + + if "Properties" in dir ( st_masterCell ) : return st_masterCell.Properties() + else : return st_masterCell + + else : + if st_masterCell : + # MAJ of the hierarchy in _underCells + CELLS[0]._underCells[st_masterCell] = cell._hierarchy+1 + return st_masterCell + + else: + return hur_masterCell diff --git a/stratus1/src/stratus/st_getrealmodel.py b/stratus1/src/stratus/st_getrealmodel.py new file mode 100644 index 00000000..0f995fc3 --- /dev/null +++ b/stratus1/src/stratus/st_getrealmodel.py @@ -0,0 +1,93 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_getrealmodel.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + +from st_parser import Parser, InitParser, WeightParser + +import os + +def InitBV () : + myP = InitParser() + + if 'STRATUS_MAPPING_NAME' in os.environ : + myP.Parse ( os.environ['STRATUS_MAPPING_NAME'] ) + else : + err = "\n[Stratus ERROR] Virtual library : No file found in order to parse.\nCheck STRATUS_MAPPING_NAME.\n" + raise err + +def GetRealModel ( model ) : + myP = Parser() + + if 'STRATUS_MAPPING_NAME' in os.environ : + myP.Parse ( os.environ['STRATUS_MAPPING_NAME'] ) + else : + err = "\n[Stratus ERROR] Virtual library : No file found in order to parse.\nCheck STRATUS_MAPPING_NAME.\n" + raise err + + return myP._realCell[model], myP._inOut[model] + +def GetWeightTime ( model ) : + myP = WeightParser() + + if 'STRATUS_MAPPING_NAME' in os.environ : + myP.Parse ( os.environ['STRATUS_MAPPING_NAME'] ) + else : + err = "\n[Stratus ERROR] Virtual library : No file found in order to parse.\nCheck STRATUS_MAPPING_NAME.\n" + raise err + + return myP._weightTime[model] + +def GetWeightArea ( model ) : + myP = WeightParser() + + if 'STRATUS_MAPPING_NAME' in os.environ : + myP.Parse ( os.environ['STRATUS_MAPPING_NAME'] ) + else : + err = "\n[Stratus ERROR] Virtual library : No file found in order to parse.\nCheck STRATUS_MAPPING_NAME.\n" + raise err + + return myP._weightArea[model] diff --git a/stratus1/src/stratus/st_instance.py b/stratus1/src/stratus/st_instance.py new file mode 100644 index 00000000..a9601dcf --- /dev/null +++ b/stratus1/src/stratus/st_instance.py @@ -0,0 +1,375 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_instance.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from Hurricane import * +import CRL + +from st_model import Model, MODELMAP +from st_getrealmodel import GetRealModel, InitBV + +import sys, re, types, os + +## Alliance's libraries ## +SXLIB = "_x[0-8]" +PXLIB = "_px" +RAMLIB = "ram_" +RFLIB = "rf_" +RF2LIB = "rf2_" +ROMLIB = "rom_" +DPSXLIB = "dp_.*_x[1-8]" + +## Puts MBK_CATA_LIB at the begining of PYTHONPATH ## +cata_lib = os.environ['MBK_CATA_LIB'] +chaine = re.search ( "([^:]*):(.*)", cata_lib ) +while chaine : + rep = chaine.group ( 1 ) + cata_lib = chaine.group ( 2 ) + + sys.path.insert ( 0, rep ) + + chaine = re.search ( "([^:]*):(.*)", cata_lib ) + +## Class of nets ## +NET = ( "st_net.SignalIn", "st_net.SignalOut", "st_net.SignalInOut" \ + , "st_net.SignalUnknown", "st_net.TriState" \ + , "st_net.CkIn" \ + , "st_net.Signal", "st_net.Sig" \ + , "st_net.VddIn", "st_net.VssIn" \ + , "st_net.VddInFromHur", "st_net.VssInFromHur" + ) +ALIM_NET = ( "st_net.VddIn", "st_net.VssIn" \ + , "st_net.VddInFromHur", "st_net.VssInFromHur" + ) + +################ +##### Inst ##### +################ +class Inst : + + ################ + ##### Init ##### + ################ + def __init__ ( self, model, name = None, map = {}, cell = None ) : + global MODELMAP, CELLS, FRAMEWORK + + from st_model import MODELMAP, CELLS, FRAMEWORK + from util_Place import UNPLACED, NOSYM + + if not cell : cell = CELLS[-1] + + ##### Virtual library ##### + global BV + from st_parser import BV + if BV == [] : InitBV() + + if model in BV : model, self._inout = GetRealModel ( model ) + + ##### Attributes of the instance ##### + self._model = model.lower() + self._st_cell = cell + self._hur_instance = None + self._plac = UNPLACED + self._map = map + + ##### Name of the instance ###### + if not name : + name = "instance%d_%s" % ( cell._NB_INST, self._model ) + cell._NB_INST += 1 + self._name = name + + ##### The instance is put in the instances' list of the cell ##### + cell._st_insts.append ( self ) + + ##### Errors ##### + # Error : if the model is not a string + if type ( model ) != types.StringType : raise "\n[Stratus ERROR] Inst : the model must be described in a string.\n" + # Warning : the model can not contain capitalized letters + if re.search ( "[A-Z]", model ) : + print "[Stratus Warning] Inst : Upper case letters are not supported, the name", model, "is lowered." +# model = model.lower() + # Error : spaces are forbidden + if re.search ( " ", model ) : + err = "\n[Stratus ERROR] Inst : " + name + " the name of the model \"" + model + "\" can not contain a space.\n" + raise err + if name : + if re.search ( " ", name ) : + err = "\n[Stratus ERROR] Inst : \"" + name + "\" the name of the instance can not contain a space.\n" + raise err + # Warning : the name can not contain capitalized letters + if re.search ( "[A-Z]", name ) : + print "[Stratus Warning] : Upper case letters are not supported, the name", name, "is lowered." + name = name.lower () + + # Error : if map[pin] is not a net + if map : + for pin in map : + if str ( map[pin].__class__ ) not in NET : + err = "\n[Stratus ERROR] Inst : \"" + name + "\" one argument is not a net : " + err += "pin is : " + pin + " and is associated to : " + if map[pin] : err += str(map[pin]) + else : err += "None" + err += "\n" + raise err + + ##### MasterCell ##### + self._hur_masterCell = FRAMEWORK.getCell ( self._model, CRL.Catalog.State.Views ) + + self._st_masterCell = None + for c in CELLS[0]._underCells : + if self._model == c._name : + self._st_masterCell = c + break + if not( self._hur_masterCell or self._st_masterCell ) : print "\n[Stratus Warning] Inst : no master cell found for instance" + self._name + + # Creation of the hurricane instance + if CELLS[0]._hur_plug : self.create_hur_inst ( model ) + + ############## + ### Delete ### + ############## + def Delete ( self ) : + # Erasement of the references to the instance + for i in range ( len ( self._st_cell._st_insts ) ) : + if self._st_cell._st_insts[i] == self : + del self._st_cell._st_insts[i] + break + # Erasement of the hurricane instance associated + if self._hur_instance : self._hur_instance.Delete() + + ############################################## + ##### Creation of the hurricane instance ##### + ############################################## + def create_hur_inst ( self, model ) : + if not self._hur_masterCell : + #self._hur_masterCell = FRAMEWORK.getCell ( self._model, CRL.Catalog.State.Views ) + self._hur_masterCell = FRAMEWORK.getCell ( model, CRL.Catalog.State.Views ) + + if not self._hur_masterCell : + err = "\n[Stratus ERROR] HurricanePlug : Problem of master cell " + model + ".\nCheck model name and/or CRL_IN_LO/CRL_IN_PH variables .\n" + raise err + + if not self._st_masterCell : + if MODELMAP.has_key ( str ( self._hur_masterCell ) ) : + self._st_masterCell = MODELMAP[str ( self._hur_masterCell )] + else : + self._st_masterCell = Model ( str ( self._hur_masterCell.getName() ), hurCell = self._hur_masterCell ) + + if not self._st_cell._hur_cell : + err = "\n[Stratus ERROR] HurricanePlug : Problem of hurricane cell.\nTry to contact Coriolis team.\n" + raise err + + inst = Instance ( self._st_cell._hur_cell + , self._name + , self._hur_masterCell + ) + # The hurricane instance is connected to the stratus instance + self._hur_instance = inst + + ##### Connection ##### + for pin in self._map : + mapNet = self._map[pin] + + ### Virtual library ### + if "_inout" in self.__dict__ : pin = self._inout[pin] + + # Error : if there is a space in the name of the pin (usually done at the end of the pin ...) + if re.search ( " ", pin ) : + err = "\n[Stratus ERROR] Inst : " + self._name + " the keys of the connection map can not contain a space : \"" + pin + "\".\n" + raise err + + # Error : if the net to connect does not have it's arity defined + if not ( mapNet._arity ) : + err = "\n[Stratus ERROR] Inst : " + self._name + " : the size of " + mapNet._name + " has not been defined properly.\n" + raise err + + wrong_pin = 1 + for net in self._hur_masterCell.getExternalNets(): + if ( pin == str(net.getName()) ) or re.search ( "%s\(" % pin, str(net.getName()) ) : + wrong_pin = 0 + break + + # Error : if the pin doesn't exist in the model's ports + if wrong_pin : + err = "\n[Stratus ERROR] Inst : " + str(self._name) + " : port " + pin \ + + " does not exist in model " + str(self._hur_masterCell.getName()) + ". Pins are :" + for pin in self._hur_masterCell.getExternalNets(): + err += str ( pin.getName() ) + err += "," + sea = re.search ( "(.*),$", err ) + if not sea : err += "No pins found ..." + else : err = sea.group(1) + raise err + + # Error : if the arities of the nets don't correspond + tabPins = self._st_masterCell._st_ports + self._st_masterCell._st_cks + self._st_cell._st_vdds + self._st_cell._st_vsss + for net in tabPins : + if net._name == pin : + if net._arity != mapNet._arity : + err = "\n[Stratus ERROR] Inst : " + str(self._name) + " : The arity of the net " + mapNet._name + " " + str(mapNet._arity) \ + + " does not correspond to the arity of the port of the cell : "+ net._name + " " + str(net._arity) + ".\n" + raise err + + # If the port of the masterCell doesn't have a LSB which is 0 + lsb = 0 + if mapNet._arity > 1 : + netBus = None + while not ( netBus ) : + netBus = self._hur_masterCell.getNet ( pin.lower() + "(" + str ( lsb ) + ")" ) + lsb += 1 + if lsb > 20 : # value chosen in order to avoid infinite loop in case of a problem (may be higher) + err = "\n[Stratus ERROR] Inst : " + str(self._name) + " : Probem of map, check the arities of your nets.\n" + raise err + if lsb : lsb -= 1 + + ### Connection ### + if mapNet._real_net : realNet = mapNet._real_net + else : realNet = mapNet + + # range 1: given the indice's net + nbit1 = mapNet._ind - realNet._ind + # range 2: deal with reverse nets + if ( '_reverse' in mapNet.__dict__ ) and ( mapNet._reverse ) : + nbit2 = nbit1 - mapNet._arity + pas = -1 + else : + nbit2 = nbit1 + mapNet._arity + pas = 1 + + j = 0 + for i in range ( nbit1, nbit2, pas ) : + # If the net has to be concatened + if ( realNet._to_cat ) and ( realNet._to_cat[i] ) : + net = realNet._to_cat[i][0] + bit = realNet._to_cat[i][1] + if net._real_net : net = net._real_net + + # If the net which is concatened is an alias + if ( net._alias ) and ( net._alias[bit] ) : + netA = net._alias[bit].keys()[0] + bitA = net._alias[bit][netA] + if net._real_net : netA = netA._real_net + + hurNet = netA._hur_net[bitA-net._ind] + else : + hurNet = net._hur_net[bit-net._ind] + + # If the net is an alias + elif ( realNet._alias ) and ( realNet._alias[i] ) : + net = realNet._alias[i].keys()[0] + bit = realNet._alias[i][net] + if net._real_net : net = net._real_net + + hurNet = net._hur_net[bit+net._ind] + + else : + hurNet = realNet._hur_net[i] + + #if mapNet._arity == 1 : tempNet = self._hur_masterCell.getNet ( pin.lower() ) + if mapNet._arity == 1 : tempNet = self._hur_masterCell.getNet ( pin ) + else : tempNet = self._hur_masterCell.getNet ( pin.lower() + "(" + str(j+lsb) + ")" ) + j += 1 + + if not ( tempNet ) : + err = "\n[Stratus ERROR] Inst : Problem in map. Check that the arities of your nets are correct.\n" + raise err + + plug = self._hur_instance.getPlug ( tempNet ) + plug.setNet ( hurNet ) + + # In order to see the ring + if str ( realNet.__class__ ) not in ALIM_NET : CRL.createPartRing ( self._st_cell._hur_cell, hurNet.getName() ) + + # Error message if the connection is not correct (detection before vst driver) + # Not for vdd/vss in case of utilisation of SetGlobal + # The detection is done with vst driver in this case ... + for plug in self._hur_instance.getUnconnectedPlugs(): + if plug.getMasterNet().getType() not in ( TypePOWER, TypeGROUND ) : + name = str(plus.getMasterNet().getName()) + chaine = re.search ( "(.*)\(", name ) + if chaine : name = chaine.group(1) + + err = "\n[Stratus ERROR] Inst : plug " + name + " of instance " + self._name + " must be connected.\n" + raise err + + ############## + ### Prints ### + ############## + def printInstance ( self ) : + print " => model", self._model + print " => map" + for pin in self._map : + n = self._map[pin] + if n._to_merge : n = n._to_merge[0][0] + print " ", pin, "->", n._name + + def printMap ( self ) : + print "Map:", self._name + for pin in self._map : + print " ", pin, self._map[pin]._name + +######################### +#### SetCurrentModel #### +######################### +def SetCurrentModel ( instance ) : + global CELLS + from st_model import CELLS + + if not instance : + err = "\n[Stratus ERROR] SetCurrentModel : argument given does not exist.\n" + raise err + cell = instance._st_masterCell + + if not cell : + err = "\n[Stratus ERROR] SetCurrentModel : cannot find model for instance " + str ( getName ( instance ) ) + ".\n" + raise err + + CELLS.append ( cell ) + + return cell diff --git a/stratus1/src/stratus/st_model.py b/stratus1/src/stratus/st_model.py new file mode 100644 index 00000000..5d74fdd5 --- /dev/null +++ b/stratus1/src/stratus/st_model.py @@ -0,0 +1,1123 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_model.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from Hurricane import * +import CRL + +import re, types, string + +FRAMEWORK = None +EDITOR = None + +MODELMAP = {} +CELLS = [] + +STRATUS = 100 +LOGICAL = CRL.Catalog.State.Logical +PHYSICAL = CRL.Catalog.State.Physical +VIEWS = CRL.Catalog.State.Views + +def setEditor ( editor ): + global EDITOR + + EDITOR = editor + return + +####################### +##### Class Model ##### +####################### +class Model : + + ########################## + ##### Initialisation ##### + ########################## + def __init__ ( self, nom, param = {}, hurCell = None, hurricane_plug = True ) : + global FRAMEWORK, CELLS + + self._name = nom + self._param = param + + self._hur_cell = hurCell + + self._st_insts = [] # Tab : list of the instances + self._st_ports = [] # Tab : list of the nets + self._st_sigs = [] # Tab : list of the nets + + self._st_partsigs = [] # Tab : list of the partial nets + self._st_merge = [] # Tab : list of the nets to merge, in order to have them in the right order + + self._hierarchy = 0 # Modified in ModelCreation + + self._TAB_NETS_OUT = [] + self._TAB_NETS_CAT = [] + self._NB_INST = 0 + + # List of the generators used for overload + self._and = 'A2' + self._or = 'O2' + self._xor = 'Xr2' + self._not = 'Inv' + self._buff = 'Buf' + self._reg = 'Sff1' + # Stratus generators + self._mux = 'Smux' + self._shift = 'Shifter' + self._comp = 'Comp' + # Arithmetic generators + self._add = 'Slansky' + self._sub = 'Sub' + self._mult = 'Multiplier' + self._div = None + + self._signed = True + self._extended = False + + self._model_map = {} + + # List of the under-cells of a cell + self._underCells = {} +# self._tabPlacement = [] + # Instance reference for placement + self._insref = None + + # Place and Route + self._nb_alims_verticales = 0 + self._nb_pins = 0 # to number the pins of the core + self._nb_vdd_pins = 0 # to number the pins vdd of the core + self._nb_vss_pins = 0 # to number the pins vss of the core + self.standard_instances_list = [] + self.pad_north = [] # list to save the pads names + self.pad_south = [] + self.pad_east = [] + self.pad_west = [] + + # Creation of the database + if not FRAMEWORK : + #Initialize() + FRAMEWORK = CRL.getAllianceFramework() + + self._st_vdds = [] + self._st_vsss = [] + + if hurCell : + from st_net import VddInFromHur + from st_net import VssInFromHur + + netVdd = iter(hurCell.getPowerNets()).next() + netVss = iter(hurCell.getGroundNets()).next() + if netVdd != None : self._st_vdds.append ( VddInFromHur ( netVdd ) ) + else : print "[Stratus Warning] : Cell", self._name, "does not have a vdd port." + if netVss != None : self._st_vsss.append ( VssInFromHur ( netVss ) ) + else : print "[Stratus Warning] : Cell", self._name, "does not have a vss port." + + self._st_cks = [] + + if not hurCell : + # List of the cells + CELLS.append ( self ) + # List of the undercells + if CELLS[0] != self : + CELLS[0]._underCells[self] = 0 +# CELLS[0]._tabPlacement.append ( self ) + + self._hur_plug = hurricane_plug + + # HurricanePLug if : no hurCell, in mode hurricane plug (i.e. hurricane_plug and hurricane_plug of the masterCell) + if ( not hurCell ) and ( hurricane_plug ) : + if CELLS[0] == self : + self.HurricanePlug() + else : + if CELLS[0]._hur_plug : + self.HurricanePlug() + + ##### Delete ##### + def Delete ( self ) : + UpdateSession.open() + + under_cells = self._underCells + self._hur_cell.Delete() + for cell in under_cells : cell._hur_cell.Delete() + + UpdateSession.close() + + ##################################################### + ##### Initialisation of attributes for the cell ##### + ##################################################### + def InitGraph ( self ) : + self._graph = True + + # External nets + for net in self._st_ports : + net._st_inst_in = None + net._st_insts_out = [] + net._covered = False + + # Internal nets + for net in self._st_sigs : + net._st_inst_in = None + net._st_insts_out = [] + net._covered = False + + # Part nets + for pnet in self._st_partsigs : + pnet._st_inst_in = None + pnet._st_insts_out = [] + pnet._covered = False + + # Instances + for inst in self._st_insts : + inst._st_nets_in = [] + inst._st_nets_out = [] + + # Initialisation of instances and nets + self.initNet ( inst ) + self.initInst ( inst ) + + ######################################################## + ##### Initialisation of the attributes of the nets ##### + ######################################################## + def initNet ( self, instance ) : + # For each pin + for pin in instance._map : + # Check if the pin is an output or an input + direct = "" + direct = self.getDirect ( instance._model, pin ) + + # Get the net connected to this pin + if instance._map[pin]._to_merge : mapNet = instance._map[pin]._to_merge[0][0] + else : mapNet = instance._map[pin] + + if len ( instance._map[pin]._to_merge ) > mapNet._arity : + mapNet._real_arity = len ( instance._map[pin]._to_merge ) + mapNet._inverse_merge = instance._map[pin] + + # Initialisation + if direct == 'input' : + if mapNet._real_net : + mapNet = mapNet._real_net + + if '_st_insts_out' not in mapNet.__dict__ : mapNet._st_insts_out = [] + + if instance not in mapNet._st_insts_out : mapNet._st_insts_out += [instance] + + elif direct == 'output' : # FIXME _real_net not taken care of + mapNet._st_inst_in = instance + + ############################################################# + ##### Initialisation of the attributes of the instances ##### + ############################################################# + def initInst ( self, instance ) : + # For each pin + for pin in instance._map : + # Check if the pin is an output or an input + direct = "" + direct = self.getDirect ( instance._model, pin ) + + # Get the net connected to this pin + if instance._map[pin]._to_merge : mapNet = instance._map[pin]._to_merge[0][0] + else : mapNet = instance._map[pin] + + # Initialisation + if direct == 'input' : instance._st_nets_in += [mapNet] + elif direct == 'output' : instance._st_nets_out += [mapNet] + + ########################################### + ##### Returns the direction of a port ##### + ########################################### + def getDirect ( self, model, pin ) : + global FRAMEWORK + + hurCell = FRAMEWORK.getCell ( model, CRL.Catalog.State.Views ) + + stCell = None + if not hurCell : + for c in self._underCells : + if c._name == model : + stCell = c + break + + if not hurCell and not stCell : + raise "\nError : no cell found with model %s.\n" % model + + # Hurricane cell found: + if hurCell : + found = False + for netLoc in hurCell.getExternalNets(): + net = netLoc.getElement() + direction = net.getDirection() + name = str(net.getName()) + + if net.getType() in ( TypePOWER, TypeGROUND, TypeCLOCK ) : + found = True + continue + + chaine = re.search ( "(.*)\([0-9]+\)", name ) + if chaine : name = chaine.group(1) + + if name == pin : + found = True + if direction == DirectionOUT : return "output" + elif direction == DirectionIN : return "input" + else : raise "\nError : unable to find direction of port %s in model %s. Direction is %d\n" % ( pin, model, direction ) + + if not found : raise "\nError : unable to find port %s in model %s.\n" % ( pin, model ) + + # Stratus cell found: + elif stCell : + found = False + + for net in stCell._st_vdds : + if net._name == pin : + found = True + break + + for net in stCell._st_vsss : + if net._name == pin : + found = True + break + + for net in stCell._st_cks : + if net._name == pin : + found = True + break + + # _st_ports i.e. not alimentations and not clock + for net in stCell._st_ports : + if net._name == pin : + found = True + if net._direct == "OUT" : return "output" + elif net._direct == "IN" : return "input" + else : raise "\nError : unable to find direction of port %s in model %s.\n" % ( pin, model ) + + if not found : + ports = "" + for net in stCell._st_ports : ports += net._name + "," + raise "\nError : unable to find port %s in model %s.\nPorts are : %s\n" % ( pin, model, ports ) + + else : + err = "\n[ERROR] InitGraph : no model named " + model + " in the database.\n" + raise err + + ############################# + ##### Print of the cell ##### + ############################# + def Print ( self ) : + print "################## The Cell ##################" + for inst in self._st_insts : + print " * inst name :", inst._name + print " inst model :", inst._model + for pin in inst._map : + if pin != 'vdd' and pin != 'vss' : + net = inst._map[pin] + print " pin :", pin, "net :", net._name, "with arity :", net._arity + if net._to_merge : + net = inst._map[pin]._to_merge[0][0] + print " net merged with :", net._name, "with arity :", net._arity + + ######################### + def PrintGraph ( self ) : + if "_graph" not in self.__dict__ : + err = "\n[Stratus ERROR] PrintGraph : The graph does not exist. Use initGraph before.\n" + raise err + else : + if self._graph == False : + err = "\n[Stratus ERROR] PrintGraph : The graph does not exist. Use initGraph before.\n" + raise err + + print "################## Cell's Graph features ##################" + for inst in self._st_insts : + print " => inst name :", inst._name, "( model :", inst._model, ")" + print " inst st_nets_in :" + for net in inst._st_nets_in : print " ", net._name + print " inst st_nets_out :" + for net in inst._st_nets_out : print " ", net._name + for port in self._st_ports : + print " => port name :", port._name + if port._st_inst_in : print " port _st_inst_in :", port._st_inst_in._name + print " port _st_insts_out :" + for p in port._st_insts_out : print " ", p._name + for sig in self._st_sigs : + print " => sig name :", sig._name + if sig._st_inst_in : print " sig _st_inst_in :", sig._st_inst_in._name + print " sig _st_insts_out :" + for s in sig._st_insts_out : print " ", s._name + for psig in self._st_partsigs : + print " => part sig name :", psig._name + if '_st_inst_in' in psig.__dict__ and psig._st_inst_in: print " part sig _st_inst_in :", psig._st_inst_in._name + if '_st_insts_out' in psig.__dict__ : + print " part sig _st_insts_out :" + for s in psig._st_insts_out : print " ", s._name + + ##################### + ##### overloard ##### + ##################### + ##### __getattr ##### +# def __getattr__ ( self, attr ) : + + ##### __str ##### + def __str__ ( self ) : + s = "Model" + str ( self._hur_cell ) + return s + + ######################## + ##### VLSI Methods ##### + ######################## + ##### Interface ##### + def Interface ( self ) : + print "[Stratus Warning] : Execution of empty Interface method for", self._name, "." + + ##### Netlist ##### + def Netlist ( self ) : + print "[Stratus Warning] : Execution of empty Netlist method for", self._name, "." + pass + + ##### Layout ##### + def Layout ( self ) : + print "[Stratus Warning] : Execution of empty Layout method for", self._name, "." + pass + + ##### Vbe ##### + def Vbe ( self ) : + self._vbe = True + + ##### View : in order to see the in the editor ##### + def View ( self, stopLevel=1, message="Status stop point" ) : + global EDITOR + + if not self._hur_cell : + err = "\n[Stratus ERROR] View : Hurricane Cell does not exist.\nCheck CRL_IN_LO/CRL_IN_PH variables.\n" + raise err + + if EDITOR: + EDITOR.setCell ( self._hur_cell ) + EDITOR.fit () + Breakpoint.stop ( stopLevel, message ) + + ##### Save : in order to create the output files ##### + def Save ( self, views = 0, fileName = None ) : + global FRAMEWORK + global CELLS + + if views == STRATUS : + self.exportStratus ( fileName ) + + else : + UpdateSession.open() + + hurCell = self._hur_cell + + if str ( hurCell.getName() ) != "__Scratch__" : + FRAMEWORK.saveCell ( hurCell, views|CRL.Catalog.State.Logical ) + + if len ( CELLS ) == 0 : + err = "\n[Stratus ERROR] Save : CELLS stack is empty.\n" + raise err + + CELLS.pop() + + UpdateSession.close() + + ##### Simul : in order to use simulation tool ##### + def Simul ( self, name = None, tool = 'asimut' ) : + from utils import runpat + + if not name : name = self._name + + if tool == 'asimut' : runpat ( self._name, name, '-l 1 -p 100 -zerodelay -nocheckdriver -nostrict -bdd -nowarning' ) + else : raise 'not implemented yet' + + ##### Create a stratus file given the database ##### + def exportStratus ( self, fileName ) : + + ## Cat formating ## + def catName ( net, tableau ) : + + name = "Cat ( " + paire = tableau[-1] + if paire : + net1 = paire[0] + bit1 = str(paire[1]) + else : + net1 = net + bit1 = str(len(tableau)-1) + + for i in range ( len(tableau)-2, -1, -1 ) : + change = False + if tableau[i] and not tableau[i+1] : + change = True + elif not tableau[i] and tableau[i+1] : + change = True + elif tableau[i] and tableau[i+1] : + if tableau[i][0] != tableau[i+1][0] : + change = True + + if change : + if tableau[i+1] : bit2 = str(tableau[i+1][1]) + else : bit2 = str(i+1) + + name += "self." + if int(bit2) == int(net1._ind) and int(bit1) == (net1._arity-1) : + name += net1._name + else : + name += net1._name + name += "[" + name += bit1 + name += ":" + name += bit2 + name += "]" + + name += ", " + + if tableau[i] : net1 = tableau[i][0] + else : net1 = net + + if tableau[i] : bit1 = str(tableau[i][1]) + else : bit1 = str(i) + + if tableau[0] : + bit2 = str(tableau[0][1]) + else : + bit2 = "0" + + name += "self." + if int(bit2) == int(net1._ind) and int(bit1) == (net1._arity-1) : + name += net1._name + else : + name += net1._name + name += "[" + name += bit1 + name += ":" + name += bit2 + name += "]" + + name += " )" + + return name + + ######################### + nom = str(self.__class__) + chaine = re.search ( "[^\.]*\.(.*)", nom ) + nom = chaine.group(1) + + if not fileName : fileName = nom + "_created" + fileName += ".py" + + file = open ( fileName, "w+" ) + + file.write ( "#!/usr/bin/python\n\n" ) + file.write ( "from stratus import *\n\n" ) + + file.write ( "class %s ( Model ) :\n\n" % nom ) + + ##### Interface ##### + file.write ( " def Interface ( self ) :\n\n" ) + + for net in self._st_ports : + if net._direct == "IN" : classe = "SignalIn" + elif net._direct == "OUT" : classe = "SignalOut" + elif net._direct == "INOUT" : classe = "SignalInOut" + + file.write ( " self.%s = %s ( \"%s\", %d )\n" % ( net._name, classe, net._name, net._arity ) ) + file.write ( "\n" ) + + for ck in self._st_cks : + if ck._ext: + file.write ( " self.%s = CkIn ( \"%s\" )\n" % (ck._name, ck._name) ) + + file.write ( " self.vdd = VddIn ( \"vdd\" )\n" ) + file.write ( " self.vss = VssIn ( \"vss\" )\n" ) + file.write ( "\n" ) + + ##### Netlist ##### + file.write ( " def Netlist ( self ) :\n\n" ) + + # Signals + for net in self._st_sigs : + if net._to_merge : + towrite = False + for paire in net._to_merge : + if paire == 0 : towrite = True + if not towrite : continue + file.write ( " self.%s = Signal ( \"%s\", %d )\n" % ( net._name, net._name, net._arity ) ) + file.write ( "\n" ) + + # Generate + for cell in CELLS[0]._underCells : + if CELLS[0]._underCells[cell] == 1 : + classe = str(cell.__class__) + nom = cell._name + param = cell._param + + # Gestion of libraries with specific treatment + chaine = re.search ( "(.*)\.([^\.]*)", classe ) + if chaine : + fichier = chaine.group(1) + if re.search ( "dpgen_", fichier ) or re.search ( "st_", fichier ) : + classe = chaine.group(2) + # Special treatment for virtual library + if classe == "Bool" : + nom = cell._name + classe = cell._param['model'] + param = cell._param + del param['model'] + del param['realModel'] + + classe = string.upper(classe[0]) + classe[1:] #FIXME !!! + if re.search ( "(.*)\.([^\.]*)", classe ) : # ArithLib generator + classe = string.lower(classe[0]) + classe[1:] + + file.write ( " Generate ( \"%s\", \"%s\", param = %s )\n" % ( classe, nom, param ) ) + file.write ( "\n" ) + + # Instances + for inst in self._st_insts : + #chaine = re.search ( "([^_]*)_(.*)", inst._name ) #XTOF FIXME !!! + #instName = chaine.group(1) #XTOF FIXME !! + file.write ( " self.%s = Inst ( \"%s\"\n" % ( inst._name, inst._model ) ) + file.write ( " , \"%s\"\n" % inst._name ) + file.write ( " , map = { " ) + + # Map + for pin in inst._map : + toto = False + tata = False + + netInMap = inst._map[pin] + nom = "self." + netInMap._name + + # <= + if netInMap._to_merge : + oneperone = True + for i in range ( len ( netInMap._to_merge ) ) : + paire = netInMap._to_merge[i] + + if paire : + net = paire[0] + if i > 0 : + if netInMap._to_merge[i-1] != 0 : + netbefore = netInMap._to_merge[i-1][0] + else : + oneperone = False + break + if net != netbefore : + oneperone = False + break + if paire[1] != i : + oneperone = False + break + + else : + toto = True + oneperone = False + break + + # "easy" case : 1 per 1 corresponding + if oneperone : + netInMap = netInMap._to_merge[0][0] + nom = "self." + netInMap._name + + # else : Cat of the different signals + else : + nom = catName ( netInMap, netInMap._to_merge ) + + # Cat + if netInMap._to_cat : + tata = True + nom = catName ( netInMap, netInMap._to_cat ) + + if toto and tata : print "Attention est ce un cas bien gere ???" + + if pin == inst._map.keys()[0] : file.write ( "\"%s\" : %s\n" % ( pin, nom ) ) + else : file.write ( " , \"%s\" : %s\n" % ( pin, nom ) ) + + file.write ( " }\n" ) + file.write ( " )\n\n" ) + + ##### End ##### + file.close () + + #### Quit : to quit the current cell without saving ##### + def Quit ( self ) : + global CELLS + + CELLS.pop () + + ######################################### + ##### GetModelName : Class's method ##### + ######################################### + def GetModelName ( param ) : + return None + GetModelName = staticmethod ( GetModelName ) + + ######################################### + ##### GetParam : Class's method ##### + ######################################### + def GetParam () : + return None + GetParam = staticmethod ( GetParam ) + + ############### + ##### Set ##### + ############### + def SetAnd ( self, model ) : self._and = model + def SetOr ( self, model ) : self._or = model + def SetXor ( self, model ) : self._xor = model + def SetNot ( self, model ) : self._not = model + + def SetBuff ( self, model ) : self._buff = model + def SetReg ( self, model ) : self._reg = model + def SetMux ( self, model ) : self._mux = model + def SetShift ( self, model ) : self._shift = model + def SetComp ( self, model ) : self._comp = model + + def SetAdd ( self, model ) : self._add = model + def SetMult ( self, model ) : self._mult = model + def SetDiv ( self, model ) : self._div = model + + def SetSigned ( self, model ) : self._signed = model + def SetExtended ( self, model ) : self._extended = model + + ############################# + ##### Creation of model ##### + ############################# + def ModelCreation ( self, modele, modele2, dict, hierarchy, realModele = None, inOut = None ) : + global CELLS + + from st_parser import BVg + + ## Virtual library ## + from st_bool import Bool + + ## Stratus generators ## + from st_mux import Smux + from st_shifter import Shifter + from st_comp import Comp + from st_const import Constant + from st_extend import Extend + + from st_slansky import Slansky + from st_slansky import Sub + from st_mult import Multiplier + + ## Genlib ## + from dpgen_Shifter import DpgenShifter + from dpgen_Shrot import DpgenShrot + from dpgen_Nul import DpgenNul + from dpgen_RAM import DpgenRam + from dpgen_ROM2 import DpgenRom2 + from dpgen_ROM4 import DpgenRom4 + from dpgen_ADSB2F import DpgenAdsb2f + from dpgen_RF1 import DpgenRf1, DpgenRf1d, DpgenRf1r0, DpgenRf1dr0, DpgenFifo + from dpgen_RF2 import DpgenRf2, DpgenRf2d, DpgenRf2r0, DpgenRf2dr0 + from dpgen_Regular import DpgenAnd2, DpgenAnd3, DpgenAnd4, DpgenBuff, DpgenBuse, DpgenConst, DpgenDff, DpgenDfft, DpgenInv, DpgenMux2, DpgenNand2, DpgenNand2mask, DpgenNand3, DpgenNand4, DpgenNbuse, DpgenNmux2, DpgenNor2, DpgenNor2mask, DpgenNor3, DpgenNor4, DpgenOr2, DpgenOr3, DpgenOr4, DpgenSff, DpgenSfft, DpgenXnor2, DpgenXnor2mask, DpgenXor2 + + from util_Gen import F_MSB_FIRST + + if type ( dict ) != types.DictType : + raise "\n[Stratus ERROR] Inst : instanciation of a user's defined generator. The methods' arguments must be dictionnaries.\n" + + ##### Creation of the instance ##### +# dict['flags'] = F_MSB_FIRST # When vst driver permits to do F_LSB_FIRST or F_LSB_FIRST TODO + + ## Virtual library ## + if modele in BVg : + dict['model'] = modele.lower() + dict['realModel'] = realModele + + instCell = Bool ( modele2, dict, inOut ) + + ## Generator ## + elif re.search ( "\.", modele ) : + chaine = re.search ( "(.*)\.([^\.]*)$", modele ) + + ficName = chaine.group(1) + className = chaine.group(2) + + # Roselyne : pour prendre en compte les modeles recursifs + import sys + #moduleClass = __import__ ( ficName, globals(), locals(), [className] ) + #modeleClass = getattr ( moduleClass, className ) + try : + modeleClass = getattr ( sys.modules['__main__'], className ) + except AttributeError : + moduleClass = __import__ ( ficName, globals(), locals(), [className] ) + modeleClass = getattr ( moduleClass, className ) + # fin Roselyne + + instCell = modeleClass ( modele2, dict ) + + else : + instCell = eval ( "%s ( \"%s\", %s )" % ( modele, modele2, str(dict) ) ) + + ## MAJ of the hierarchy ## + instCell._hierarchy = hierarchy + + ##### Methods ##### + if ( self._hur_cell ) and ( not instCell._hur_cell ) : instCell.HurricanePlug() + + instCell.Interface() + instCell.Netlist() + + if ( 'clean' in dict ) and ( dict['clean'] != False ) : + if 'interactive' not in dict : dict['interactive'] = False + instCell.Clean ( dict['interactive'], dict['clean'] ) + + if ( 'behavioral' in dict ) and ( dict['behavioral'] == True ) : + instCell.Vbe() + + if instCell._hur_cell : + v = 0 + if ( 'physical' in dict ) and ( dict['physical'] == True ) : + instCell.Layout() + v = CRL.Catalog.State.Physical + instCell.Save( v|CRL.Catalog.State.Logical ) + + else : + instCell.Quit() + + if CELLS[0] != instCell : CELLS[0]._underCells[instCell] = hierarchy + + return instCell + + ################################################################# + ##### HurricanePlug : in order to create the hurricane cell ##### + ################################################################# + def HurricanePlug ( self ) : + global FRAMEWORK, CELLS + + if self._hur_cell : + print "[Stratus Warning] : The stratus cell already exists." + return + + self._hur_plug = True + + ##### Creation of all the under cells ##### + # Initialisation of the max depth + max_depth = 0 + for keyCell in self._underCells : + if self._underCells[keyCell] > max_depth : max_depth = self._underCells[keyCell] + # Creation from the leaf to the top cell + while max_depth : + for keyCell in self._underCells : + if self._underCells[keyCell] == max_depth : + if not FRAMEWORK.getCell ( keyCell._name, CRL.Catalog.State.Views ) : + CELLS.append ( keyCell ) + keyCell.CellHurCreation() + max_depth -= 1 + + # Creation of the top cell + CELLS.append ( self ) + self.CellHurCreation() + + ##### CellHurCreation ##### + def CellHurCreation ( self ) : + global FRAMEWORK, CELLS + + # The cell + hurCell = FRAMEWORK.createCell ( self._name ) + hurCell.setTerminal ( 0 ) + + self._hur_cell = hurCell + + MODELMAP [ str ( self._hur_cell ) ] = self + + # The nets + for net in self._st_ports : net.create_hur_net() + for net in self._st_sigs : net.create_hur_net() + + + for net in self._st_cks : net.create_hur_net() + + for net in self._st_vdds : net.create_hur_net() + for net in self._st_vsss : net.create_hur_net() + + # The instances and the connection + for inst in self._st_insts : inst.create_hur_inst ( inst._model ) + + # Merge + for net in self._st_merge : net.hur_merge() + + if ( self != CELLS[0] ) and ( self._st_insts ) : # Layout done if HurricanePlug after Netlist method + #self.Layout() # FIXME trouver une raison de le faire ou pas : instances placees ou pas ... HurricanePlug ne doit plus marcher avec placement A VERIFIER 14/01/08 + if self._st_insts[0]._hur_instance.getPlacementStatus() : self.Save ( CRL.Catalog.State.Physical ) + else : self.Save ( CRL.Catalog.State.Logical ) + else : + self.Quit() + + #################### + ##### Clean Up ##### + #################### + def Clean ( self, interactive = False, tab_name_net = [] ) : + + # Hurricane cell + hurricane_cell = self._hur_cell + + # Useful for print + TAB_NETS = [] + TAB_INSTS = [] + cpt_inst_del = 0 + cpt_net_del = 0 + + ##### Tabs initialisation ##### + net_entree = [] + net_sortie = [] + net_interne = [] + + for net in hurricane_cell.getNets(): + if net.getDirection() == DirectionUNDEFINED : net_interne.append ( net ) + elif net.getDirection() == DirectionIN : net_entree.append ( net ) + elif net.getDirection() == DirectionOUT : net_sortie.append ( net ) + + ##### File initialisation ##### + file = [] + + # Output nets put in the file if there are given as arguments + if tab_name_net != True : + for net_name in tab_name_net : + for net in net_sortie : + if net_name == str ( net.getName() ) : + file.insert ( 0, net ) + if interactive : print "Output Net", net, "has to be erased, it is put in the fifo." + + ## Internal nets ## + # Number of plugs of each net : + # if equal to 0 : del net + # if equal to 1 : put net in the file + for net in net_interne : + nb_plugs = self.count_plugs ( net ) + + if nb_plugs == 0 : + if interactive : print "* One net suppressed (a) :", net + TAB_NETS.append ( net.getName () ) + cpt_net_del += 1 + + net.Delete() + + elif nb_plugs == 1 : + if net.getPlugs().next().getMasterNet().getDirection() == DirectionOUT: # output of an instance + if interactive : print "* One net put in the fifo :", net + file.insert ( 0, net ) + + ## Ouput nets ## + # Number of plugs of each net : + # if equal to 0 : del net + for net in net_sortie + net_entree : + cpt_plugs_sor = self.count_plugs ( net ) + if cpt_plugs_sor == 0 : + print "[Stratus Warning] Clean : Interface of", self._name, "changed, net :", net, "is suppressed" + TAB_NETS.append ( net.getName() ) + cpt_net_del += 1 + + net.Delete() + + ##### Algorithm ##### + while len ( file ) > 0 : + net_file = file.pop() + plug = net_file.getPlugs().next() + inst = plug.getInstance() + + # input nets of the instance + plugs_inst = inst.getPlugs() + net_entree_inst = [] + net_sortie_inst = [] + cpt_sortie = 0 + + for plug_de_inst in plugs_inst: + # compute the number of outputs of the instance + if plug_de_inst.getMasterNet().getDirection() == DirectionOUT : + cpt_sortie += 1 + # output nets of the instance put in tab, except for the net being worked on + if net_file != plug_de_inst.getNet() : net_sortie_inst.append ( plug_de_inst.getNet() ) + + if plug_de_inst.getMasterNet().getDirection() == DirectionIN : + # ignore vdd and vss + type = plug_de_inst.getNet().getType() + if type not in ( TypePOWER, TypeGROUND ) : net_entree_inst.append ( plug_de_inst.getNet() ) + + ### Deletion of te instance ### + # If the instance has only one output + if cpt_sortie == 1 : + if interactive : print "* One net suppressed (b) :", net_file + TAB_NETS.append ( net_file.getName() ) + cpt_net_del += 1 + + net_file.Delete() + + if interactive : print "* One instance suppressed (a) :", inst, inst + TAB_INSTS.append(inst.getName()) + cpt_inst_del += 1 + + UpdateSession.open() + inst.Delete() + UpdateSession.close() + + for net_ent in net_entree_inst : + cpt_plugs_in = self.count_plugs ( net_ent ) + if cpt_plugs_in == 0 : + if net_ent in net_entree : + print "[Stratus Warning] Clean : Interface of", self._name, "changed, net :", net_ent, "is suppressed" + + TAB_NETS.append ( net_ent.getName() ) + cpt_net_del += 1 + + net_ent.Delete() + else : + if interactive : print "* One net suppressed (c) : ", net_ent + + TAB_NETS.append ( net_ent.getName() ) + cpt_net_del += 1 + + net_ent.Delete() + + elif cpt_plugs_in == 1 : + if net_ent.getPlugs().next().getMasterNet().getDirection() == DirectionOUT : # is an output net of another instance + if interactive : print "* One net put in the fifo :", net_ent + file.insert ( 0, net_ent ) + + # If the instance has more than one output + elif cpt_sortie >= 2 : + connect = False + for net_sor in net_sortie_inst: + cpt_sor = self.count_plugs ( net_sor ) + if cpt_sor >= 2 : + connect = True # at least one output connected + break + elif cpt_sor == 1 : + if net_sor in net_sortie : + connect = True # at least one output connected + break + + if not ( connect ) : + if interactive : print "* One net suppressed (d) :", net_file + + TAB_NETS.append ( net_file.getName() ) + cpt_net_del += 1 + + net_file.Delete() + + for net_sor in net_sortie_inst : + if net_sor in file : file.remove ( net_sor ) + + if interactive : print "* One net suppressed (e) :", net_sor + TAB_NETS.append ( net_sor.getName() ) + cpt_net_del += 1 + + net_sor.Delete() + + if interactive : print "* One instance suppressed (b) :", inst + TAB_INSTS.append ( inst.getName() ) + cpt_inst_del += 1 + + UpdateSession.open() + inst.Delete() + UpdateSession.close() + + for net_ent in net_entree_inst : + cpt_plugs_in = self.count_plugs ( net_ent ) + + if cpt_plugs_in == 0 : + if net_ent in net_entree : + print "[Stratus Warning] Clean : Interface of", self._name, "changed, net :", net_ent, "is suppressed" + + TAB_NETS.append ( net_ent.getName() ) + cpt_net_del += 1 + + net_ent.Delete() + + else : + if interactive : print "* One net suppressed (f) :", net_ent + + TAB_NETS.append ( net_ent.getName() ) + cpt_net_del += 1 + + net_ent.Delete() + + elif cpt_plugs_in == 1 : + if net_ent.getPlugs().next().getMasterNet().getDirection() == DirectionOUT: # in an output net of another instance + if interactive : print "* One net net put in the fifo :", net_ent + file.insert ( 0, net_ent ) + + else : + if interactive : print "The net", net_file, "can not be delayed, it may be delayed later" + + else : + print "[Warning] Pb in Clean." + + if interactive : + print "" + print "* Number of net suppressed :", cpt_net_del + print "* List of these nets :", TAB_NETS + print "" + print "* Number of instances suppressed :", cpt_inst_del + print "* List of these instance :", TAB_INSTS + print "" + + ############################### + def count_plugs ( self, net ) : + return len(net.getPlugs()) + + + ############################################################################# + ############################## Place and route ############################## + ############################################################################# + def getCore ( self ) : + '''This function returns the instance "core" : the only one which is not a pad''' + + from placeandroute import isPad + + cores = [] + for instance in self._hur_cell.getInstances(): + if not isPad ( instance ): + cores.append ( instance ) + + if len(cores) == 0 : raise "\n[Stratus ERROR] getCore : No core found.\n" + elif len(cores) > 1 : raise "\n[Stratus ERROR] getCore : More than one core found.\n" + + return cores[0] diff --git a/stratus1/src/stratus/st_mult.py b/stratus1/src/stratus/st_mult.py new file mode 100644 index 00000000..98225c88 --- /dev/null +++ b/stratus1/src/stratus/st_mult.py @@ -0,0 +1,212 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_mult.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +from st_mult_matrix import Matrix, Matrix_Inv +from st_func_gen_wallace import genWallace + +class Multiplier ( Model ) : + + def __init__ ( self, name, param ) : + Model.__init__ ( self, name, param ) + + if 'nbit' in param : + self.nbit0 = param['nbit'] + self.nbit1 = param['nbit'] + else : + self.nbit0 = param['nbit0'] + self.nbit1 = param['nbit1'] + + if 'signed' in param : + self._signed = param['signed'] + else : + self._signed = True + + if self.nbit0 < 3 or self.nbit1 < 3 : raise SizeError, 'input arities must be greater than 2' + + self.type = "nr" + self.nType = 1 + + def Interface ( self ) : + self._i0 = SignalIn ( "i0", self.nbit0 ) + self._i1 = SignalIn ( "i1", self.nbit1 ) + + if self._signed : + self._o = SignalOut ( "o", self.nbit0+self.nbit1 ) + else : + self._o = SignalOut ( "o", self.nbit0+self.nbit1-2 ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + size_A = self.nbit0 + 2 + + if self.nbit1 % 2 == 0 : size_B = self.nbit1 / 2 + else : size_B = ( self.nbit1+1 ) / 2 + + if self.nbit1 % 2 == 0 : parite = 1 + else : parite = 0 + + # Signaux internes + sig_nul = Signal ( "sig_nul", 1 ) + opB = Signal ( "opb", 2*size_B-1 ) + NUL = Signal ( "nul", size_B ) + DECA = Signal ( "deca", size_B ) + COMP = Signal ( "comp", size_B ) + + # Matrice de Produits Partiels + matrice_v = [] + for i in range ( size_B ) : + matrice_v_bis = [] + for j in range ( size_A ) : matrice_v_bis += [Signal ( "matrice_%d_%d" % ( i, j ), 1 )] + matrice_v += [matrice_v_bis] + + matrice = [] + position = [] + NEW_matrice = [] + NEW_position = [] + PPmatrix = [] + + sig_nul <= Zero ( 1 ) + + for i in range ( size_B ) : + matrice.append ( [] ) + position.append ( [] ) + + # Premiere ligne + myMap = { 'nul' : NUL[i] + , 'deca' : DECA[i] + , 'comp' : COMP[i] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if i == 0 : + myMap['bminus'] = sig_nul + myMap['b'] = self._i1[i] + myMap['bplus'] = self._i1[i+1] + elif i == ( size_B - 1 ) : + myMap['bminus'] = self._i1[(2*i)-1] + myMap['b'] = self._i1[2*i] + if parite : myMap['bplus'] = self._i1[(2*i)+1] + else : myMap['bplus'] = self._i1[2*i] + else : + myMap['bminus'] = self._i1[(2*i)-1] + myMap['b'] = self._i1[2*i] + myMap['bplus'] = self._i1[(2*i)+1] + + Generate ( 'st_mult_blocs.booth_decoder', 'booth_decoder' ) + Inst ( 'booth_decoder' , map = myMap ) + + for j in range ( size_A ) : + myMap = { 'nul' : NUL[i] + , 'deca' : DECA[i] + , 'comp' : COMP[i] + , 'pp' : matrice_v[i][j] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + + if j == 0 : + myMap['a'] = sig_nul + myMap['b'] = self._i0[j] + elif j > ( self._i0._arity - 1 ) : + myMap['a'] = self._i0[self.nbit0-1] + myMap['b'] = self._i0[self.nbit0-1] + else : + myMap['a'] = self._i0[j-1] + myMap['b'] = self._i0[j] + + Generate ( 'st_mult_blocs.booth_mux', 'booth_mux' ) + Inst ( 'booth_mux', map = myMap ) + + matrice[i] = matrice[i] + [matrice_v[i][j]] + position[i] = position[i] + [1] + + # Adaptation de la matrice de produits partiels pour + MX = Matrix ( matrice, position, COMP, size_A, size_B ) + NEW_matrice = Matrix_Inv ( MX[0],( size_B + 1 ) ) + NEW_position = Matrix_Inv ( MX[1],( size_B + 1 ) ) + + # WALLACE + PPmatrix = genWallace ( self, NEW_matrice, NEW_position ) + + # Conversion pour que la sortie soit en non redondant + #temp_out = Signal ( "tempout", PPmatrix[0] ) + #temp_out <= PPmatrix[1] + PPmatrix[2] + #self._o <= temp_out[self._o._arity-1:0] + self._o <= PPmatrix[1][self._o._arity-1:0] + PPmatrix[2][self._o._arity-1:0] + + def GetModelName ( cls, param ) : + modelName = "multca2_" + + if 'nbit' in param : + modelName += str(param['nbit']) + elif 'nbit1' in param : + if param['nbit0'] != param['nbit1'] : + modelName += str(param['nbit0']) + modelName += "x" + modelName += str(param['nbit1']) + else : + modelName += str(param['nbit0']) + modelName += "bits" + + return modelName + + GetModelName = classmethod ( GetModelName ) + + def GetParam ( cls ): + + return {'nbit' : 'integer', 'nbit0' : 'integer', 'nbit1' : 'integer'} + + GetParam = classmethod ( GetParam ) + diff --git a/stratus1/src/stratus/st_mult_blocs.py b/stratus1/src/stratus/st_mult_blocs.py new file mode 100644 index 00000000..c548b2fd --- /dev/null +++ b/stratus1/src/stratus/st_mult_blocs.py @@ -0,0 +1,99 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_mult_blocs.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class booth_decoder ( Model ) : + def Interface ( self ) : + self.Bminus = SignalIn ( "bminus", 1 ) + self.B = SignalIn ( "b", 1 ) + self.Bplus = SignalIn ( "bplus", 1 ) + self.NUL = SignalOut ( "nul", 1 ) + self.DECA = SignalOut ( "deca", 1 ) + self.COMP = SignalOut ( "comp", 1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + inv_B = Signal ( "inv_b" ) + inv_Bplus = Signal ( "inv_bplus" ) + inv_Bminus = Signal ( "inv_bminus" ) + + inv_B <= ~self.B + inv_Bplus <= ~self.Bplus + inv_Bminus <= ~self.Bminus + + self.NUL <= ( self.Bplus & self.B & self.Bminus ) | ( inv_B & inv_Bplus & inv_Bminus ) + self.COMP <= self.Bplus & ( inv_B | inv_Bminus ) + self.DECA <= ( inv_B & inv_Bminus & self.Bplus ) | ( inv_Bplus & self.B & self.Bminus ) + + def GetModelName ( cls, param ) : + return "booth_decoder" + GetModelName = classmethod ( GetModelName ) + +class booth_mux ( Model ) : + def Interface ( self ) : + self.A = SignalIn ( "a", 1 ) + self.B = SignalIn ( "b", 1 ) + self.NUL = SignalIn ( "nul", 1 ) + self.COMP = SignalIn ( "comp", 1 ) + self.DECA = SignalIn ( "deca", 1 ) + self.PP = SignalOut ( "pp", 1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + self.PP <= ( ( ( self.A & self.DECA ) | ( ~self.DECA & self.B ) ) ^ ( self.COMP ) ) & ( ~self.NUL ) + + def GetModelName ( cls, param ) : + return "booth_mux" + GetModelName = classmethod ( GetModelName ) diff --git a/stratus1/src/stratus/st_mult_matrix.py b/stratus1/src/stratus/st_mult_matrix.py new file mode 100644 index 00000000..8482c06e --- /dev/null +++ b/stratus1/src/stratus/st_mult_matrix.py @@ -0,0 +1,106 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./mult_matrix.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +########################################################################################################################### +def Matrix ( matrice, position, sig_comp, size_A, size_B ) : + size_row = size_B + 1 + + for k in range ( size_B ) : + size_line = (2*(size_B - 1)) - 2*k + + if k == 0 : + for kk in range ( size_line ) : + matrice[k] = matrice[k] + [matrice[k][size_A-1]] + position[k] = position[k] + [1] + + elif k == size_B-1 : + position[k] = [0] + position[k] + position[k] = [1] + position[k] + matrice[k] = [0] + matrice[k][:] + matrice[k] = [sig_comp[k-1]] + matrice[k][:] + + else : + position[k] = [0] + position[k] + matrice[k] = [0] + matrice[k] + matrice[k] = [sig_comp[k-1]]+ matrice[k][:] + position[k] = [1] + position[k] + + for kk in range ( size_line ) : + matrice[k]= matrice[k] + [matrice[k][len(matrice[k])-1]] + position[k] = position[k] + [1] + + position.append([]) + matrice.append([]) + + for ii in range ( 2, size_row ) : + for jj in range ( ii - 1 ) : + position[ii] = [0] + [0]+ position[ii] + matrice[ii] = [0] + [0]+ matrice[ii][:] + + position[size_B] = position[size_B] + [1] + matrice[size_B] = matrice[size_B][:] + [sig_comp[k]] + + for jj in range ( size_A-1 ) : + position[ii] = position[ii] + [0] + matrice[ii] = matrice[ii][:] + [0] + + return [matrice,position] + +def Matrix_Inv ( matrice, size_row ) : + matrice_inv = [] + + for i in range ( size_row ) : + matrice_inv.append ([]) + for j in range ( len ( matrice[0] ) ) : + matrice_inv[i] = matrice_inv[i] + [matrice[i][len(matrice[i])-j-1]] + + return(matrice_inv) diff --git a/stratus1/src/stratus/st_mux.py b/stratus1/src/stratus/st_mux.py new file mode 100644 index 00000000..9b746aad --- /dev/null +++ b/stratus1/src/stratus/st_mux.py @@ -0,0 +1,145 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_mux.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class Smux ( Model ) : + + def Interface ( self ) : + + nbit_cmd = self._param['nbit_cmd'] + nbit = self._param['nbit'] + + if nbit_cmd < 1 : raise "\n[Stratus ERROR] mux : the number of bits of the command must be greater than 0.\n" + if nbit < 1 : raise "\n[Stratus ERROR] mux : the number of bits of the inputs must be greater than 0.\n" + + self._cmd = SignalIn ( "cmd", nbit_cmd ) + + self._in_tab = [] + for i in range ( int(pow ( 2, nbit_cmd )) ) : self._in_tab += [SignalIn ( "i%d" % i, nbit )] + + self._q = SignalOut ( "q", nbit ) + + self._vdd = VddIn ( "vdd" ) + self._vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + nbit_cmd = self._param['nbit_cmd'] + nbit = self._param['nbit'] + + # If the command is a bus + ######################### + if nbit_cmd > 1 : + temp = {} + # Input nets are renamed + for i in range ( int(pow ( 2, nbit_cmd )) ) : temp[i] = self._in_tab[i] + # Temporary nets + for i in range ( int(pow ( 2, nbit_cmd )), int(pow ( 2, nbit_cmd + 1 ) - 1) ) : temp[i] = Signal ( "temp_%d" % i, nbit ) + + bit_cmd = 0 + bit_entree = 0 + bit_sortie = pow ( 2, nbit_cmd ) + + for i in range ( nbit_cmd - 1, -1, -1 ) : + for j in range ( int(pow ( 2, i )) ) : + Generate ( "Mx2", "mux_%dbits" % nbit, param = { 'nbit' : nbit } ) + Inst ( "mux_%dbits" % nbit + , map = { 'i0' : temp[2*j+bit_entree] + , 'i1' : temp[2*j+1+bit_entree] + , 'cmd' : self._cmd[bit_cmd] + , 'q' : temp[j+bit_sortie] + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + bit_cmd += 1 + bit_entree += pow ( 2, i ) * 2 + bit_sortie += pow ( 2, i ) + + self._q <= temp[pow ( 2, nbit_cmd + 1 ) - 2] + + # If the command is a 1 bit net + ############################### + else : + Generate ( "Mx2", "mux_%dbits" % nbit, param = { 'nbit' : nbit } ) + Inst ( "mux_%dbits" % nbit + , map = { 'i0' : self._in_tab[0] + , 'i1' : self._in_tab[1] + , 'cmd' : self._cmd + , 'q' : self._q + , 'vdd' : self._vdd + , 'vss' : self._vss + } + ) + + def GetModelName ( cls, param ) : + + modelName = "smux" + + modelName += "_" + modelName += str(param['nbit']) + modelName += "bits" + + modelName += "_" + modelName += str(param['nbit_cmd']) + modelName += "cmdbits" + + return modelName + + GetModelName = classmethod ( GetModelName ) + + def GetParam ( cls ): + + return {'nbit' : 'integer', 'nbit_cmd' : 'integer'} + + GetParam = classmethod ( GetParam ) + diff --git a/stratus1/src/stratus/st_net.py b/stratus1/src/stratus/st_net.py new file mode 100644 index 00000000..73efbc72 --- /dev/null +++ b/stratus1/src/stratus/st_net.py @@ -0,0 +1,1166 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_net.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +from Hurricane import * +import CRL + +from st_model import Model +from st_instance import Inst +from st_generate import Generate + +import re, types, inspect + +## Class of nets ## +PORT = ( "st_net.SignalIn", "st_net.SignalOut", "st_net.SignalInOut" \ + , "st_net.SignalUnknown", "st_net.TriState" \ + ) + +##################### +##### Class net ##### +##################### +class net : + + # Creation of the instance : coded for each herited class + def __init__ ( self, nbit ) : pass + + # Deletion of the instance : the same for each net + def Delete ( self ) : + # Erasement of the references to the net + if str ( self.__class__ ) in PORT : + for i in range ( len ( self._st_cell._st_ports ) ) : + if self._st_cell._st_ports[i] == self : + del self._st_cell._st_ports[i] + break + else : + for i in range ( len ( self._st_cell._st_sigs ) ) : + if self._st_cell._st_sigs[i] == self : + del self._st_cell._st_sigs[i] + break + + for net in self._st_cell._st_sigs : + if "_to_merge" in net.__dict__ : + if len ( net._to_merge ) : + for i in range ( len ( net._to_merge ) ): + if net._to_merge[i] != 0 : + if net._to_merge[i][0] == self : net._to_merge[i] = 0 # Erasement of a reference of the net + non = False + # Erasement of the net which wes going to be merged to the net being deleted + for i in range ( len ( net._to_merge ) ) : + if net._to_merge[i] != 0 : + non = True + break + if not non : net.Delete() + + # Erasement in the connections + for inst in self._st_cell._st_insts : + for pin in inst._map : + if self == inst._map[pin] : + del inst._map[pin] + break + + # Erasement of the huricane nets associated + for hurNet in self._hur_net : + if hurNet : hurNet.Delete() + + + ##### For buses ##### + def __getitem__ ( self, indice ) : + if ( indice < self._ind ) or ( indice >= ( self._ind + self._arity ) ) : + err = "\n[Stratus ERROR] [] : bad index " + str(indice) + " for net : " \ + + self._name + " of arity " + str(self._arity) + if self._ind != 0 : err += " and LSB " + str(self._ind) + err += ".\n" + raise err + + return Sig ( self, indice ) + + def __getslice__ ( self, ind1, ind2 ) : + if ind1 < ind2 : + indmin = ind1 + indmax = ind2 + else : + indmin = ind2 + indmax = ind1 + + # Errors + if ( (indmax-indmin) < 1 ) or ( (indmax-indmin) > self._arity ) : + err = "\n[Stratus ERROR] [:] : bad indexes " + str(indmax) + ", and " + str(indmin) \ + + " for net : " + self._name + " of arity " + str(self._arity) + if self._ind != 0 : err += " and LSB " + str(self._ind) + err += ".\n" + raise err + if ( indmax >= ( self._ind + self._arity ) ) or ( indmin < self._ind ) : + err = "\n[Stratus ERROR] [:] : bad indexes " + str(indmax) + ", and " + str(indmin) \ + + " for net : " + self._name + " of arity " + str(self._arity) + if self._ind != 0 : err += " and LSB " + str(self._ind) + err += ".\n" + raise err + + return Sig ( self, ind1, ind2 ) + + ##### To affect a signal : <= ##### + def __le__ ( self, net ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + ### Initialisation of net representing a constant ### + if type ( net ) == types.StringType : + from st_const import Constant + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : + raise "\n[Stratus ERROR] : there is no alim.\n" + + constParam = { 'nb' : net } + string = Constant.getString ( constParam ) + + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "constant_%d" % num_net, len ( string ) )] + + # 3 possible constant operator output name (nq,q,output) => 3 differents map + if string == "0" : + inst_name = "zero" + map_cst = { 'nq' : cell._TAB_NETS_OUT[num_net] + , 'vdd': cell._st_vdds[0] + , 'vss': cell._st_vsss[0] + } + elif string == "1" : + inst_name = "one" + map_cst = { 'q' : cell._TAB_NETS_OUT[num_net] + , 'vdd': cell._st_vdds[0] + , 'vss': cell._st_vsss[0] + } + else : + inst_name = Constant.getModelName ( constParam ) + map_cst = { 'output0': cell._TAB_NETS_OUT[num_net] + , 'vdd': cell._st_vdds[0] + , 'vss': cell._st_vsss[0] + } + Generate ( "Constant", inst_name, param = constParam ) + + Inst ( inst_name + , map = map_cst + ) + + net = cell._TAB_NETS_OUT[num_net] + + ### Merging of two nets ### + # Resizement of the output net if needed thanks to the input net's lenght + if not ( self._arity ) : self.create_net ( self._name, net._arity ) + + # Error if the nets don t have the same size + if self._arity - net._arity : + err = "\n[Stratus ERROR] <= : the nets " + self._name + " " + str(self._arity) + " and " + net._name + " " + str(net._arity) \ + + " must have the same lenght\n" + raise err + + # If the nets are virtual, Let s work with the corresponding real nets + if self._real_net : netInCell = self._real_net + else : netInCell = self + + if net._real_net : netToMerge = net._real_net + else : netToMerge = net + + # Error if self is an input net + if ( netInCell._ext ) and ( netInCell._direct == "IN" ) : + err = "\n[Stratus ERROR] <= : " + self._name + " One can not give a value to an input net.\n" + raise err + + if netToMerge._ext : + err = "\n[Stratus ERROR] <= : " + self._name + # Error if net is an output net + if netToMerge._direct == "OUT" : err += " One can not initialise a net with an output net.\n" + # Error if net is an input net + elif netToMerge._direct == "IN" : err += " One can not initialise a net with an input net. The method Buffer() should be used.\n" + raise err + + # Construction of the tab if needed + if not ( len ( netToMerge._to_merge ) ) : + for i in range ( netToMerge._arity ) : netToMerge._to_merge.append ( 0 ) + + # Initialisation of _to_merge + for i in range ( net._arity ) : netToMerge._to_merge[i+net._ind] = [netInCell, i+self._ind] + + # Puts the net in the list of nets to merge in order to have them in the right order + self._st_cell._st_merge.append ( net ) + + if self._st_cell._hur_cell : + net.hur_merge() + for i in range ( net._arity ) : + CRL.createPartRing ( self._st_cell._hur_cell, netInCell._hur_net[i+self._ind].getName() ) # FIXME plante avec le adder mixed dans un cas particulier indetermine .... + + ##### Instanciation of a buffer ##### + def Buffer ( self ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n" + + # Creation of the output net with the right size + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "net_outbuf_%d" % num_net, self._arity )] + + buffMap = { 'q' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + + if self._st_cell._buff == 'DpgenBuff' : buffMap['i0'] = self + else : buffMap['i'] = self + +# if ( self._st_cell._buff == "Buf" ) and ( self._arity == 1 ) : +# inst_name = self._st_cell._buff.lower() +# else : + inst_name = self._st_cell._buff.lower() + inst_name = re.sub ( "\.", "_", inst_name ) + inst_name += "_" + inst_name += str(self._arity) + inst_name += "bits" + + Generate ( self._st_cell._buff, inst_name, param = { 'nbit' : self._arity } ) + + Inst ( inst_name, map = buffMap ) + + return cell._TAB_NETS_OUT[num_net] + + ##### Boolean operators ##### + def __and__ ( self, other_net ) : return self.bool ( other_net, self._st_cell._and ) + def __or__ ( self, other_net ) : return self.bool ( other_net, self._st_cell._or ) + def __xor__ ( self, other_net ) : return self.bool ( other_net, self._st_cell._xor ) + + def bool ( self, other_net, model ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if model == self._st_cell._and : f = "&" + elif model == self._st_cell._or : f = "|" + elif model == self._st_cell._xor : f = "^" + if self._arity - other_net._arity : + err = "\n[Stratus ERROR] " + f + " : the nets " + self._name + " and " + other_net._name + " must have the same lenght.\n" + raise err + + # Creation of the output net with the right size + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, self._arity )] + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n" + +# if ( model in ( "A2", "O2", "Xr2" ) ) and ( self._arity == 1 ) and ( other_net._arity == 1 ) : +# inst_name = model.lower() +# +# else : + inst_name = model.lower() + inst_name = re.sub ( "\.", "_", inst_name ) + inst_name += "_" + inst_name += str(self._arity) + inst_name += "bits" + + Generate ( model, inst_name, param = { 'nbit' : self._arity } ) + + Inst ( inst_name + , map = { 'i0' : self + , 'i1' : other_net + , 'q' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + return cell._TAB_NETS_OUT[num_net] + + def __invert__ ( self ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n" + + # Creation of the output net with the right size + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, self._arity )] + + invMap = { 'nq' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + if self._st_cell._not == 'DpgenInv' : invMap['i0'] = self + else : invMap['i'] = self + +# if ( self._st_cell._not == "Inv" ) and ( self._arity == 1 ) : +# inst_name = self._st_cell._not.lower() +# else : + inst_name = self._st_cell._not.lower() + inst_name = re.sub ( "\.", "_", inst_name ) + inst_name += "_" + inst_name += str(self._arity) + inst_name += "bits" + + Generate ( self._st_cell._not, inst_name, param = { 'nbit' : self._arity } ) + + Inst ( inst_name, map = invMap ) + + return cell._TAB_NETS_OUT[num_net] + + ##### Arithmetic operators ##### + def __add__ ( self, other_net ) : return self.arithgen ( other_net, self._st_cell._add, {'signed' : self._st_cell._signed, 'extended' : self._st_cell._extended} ) + def __sub__ ( self, other_net ) : return self.arithgen ( other_net, self._st_cell._sub, {'signed' : self._st_cell._signed, 'extended' : self._st_cell._extended} ) + def __mul__ ( self, other_net ) : return self.arithgen ( other_net, self._st_cell._mult, {'signed' : self._st_cell._signed} ) + def __div__ ( self, other_net ) : return self.arithgen ( other_net, self._st_cell._div ) + + def arithgen ( self, other_net, function, parameter = {} ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not function : raise "\n[Stratus ERROR] / : to be done.\n" + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] there is no alim in cell %s.\n" % str(cell._name) + + # Creation of the output net with the right size + num_net = len ( cell._TAB_NETS_OUT ) + + if function == self._st_cell._add : + if self._st_cell._extended : + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, max ( self._arity, other_net._arity )+1 )] + else: + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, max ( self._arity, other_net._arity ) )] + elif function == self._st_cell._sub : + if self._st_cell._extended : + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, max ( self._arity, other_net._arity )+1 )] + else: + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, max ( self._arity, other_net._arity ) )] + elif function == self._st_cell._mult : cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, self._arity+other_net._arity )] + + arithParam = parameter + if not self._st_cell._signed and function == self._st_cell._mult : + name1 = re.sub(r"\[([0-9]+):([0-9]+)\]",r"\1\2", self._name) + "ext" + name2 = re.sub(r"\[([0-9]+):([0-9]+)\]",r"\1\2", other_net._name) + "ext" + i0ext = Signal(name1, self._arity+1) + i1ext = Signal(name2, other_net._arity+1) + i0ext <= self.Extend(self._arity+1, 'zero') + i1ext <= other_net.Extend(other_net._arity+1, 'zero') + + arithParam['nbit0'] = self._arity+1 + arithParam['nbit1'] = other_net._arity+1 + + arithMap = { 'i0' : i0ext + , 'i1' : i1ext + , 'o' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + + else: + + arithParam['nbit0'] = self._arity + arithParam['nbit1'] = other_net._arity + + arithMap = { 'i0' : self + , 'i1' : other_net + , 'o' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + + inst_name = function.lower() + inst_name = re.sub ( "\.", "_", inst_name ) + for p in arithParam : inst_name += "_%s_%s" % ( str(p).lower(), str(arithParam[p]).lower() ) + + Generate ( function, inst_name, param = arithParam ) + Inst ( inst_name, map = arithMap ) + + return cell._TAB_NETS_OUT[num_net] + + ##### Shifter ##### + def Shift ( self, inputNet, direction, type ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not inputNet._arity : raise "\n[Stratus ERROR] Shift : The input net does not have a positive arity.\n" + if not self._arity : raise "\n[Stratus ERROR] Shift : The command net does not have a positive arity.\n" + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] there is no alim.\n" + # Wrong parameters : + if direction not in ( "left", "right" ) : raise "\n[Stratus ERROR] Shift : The direction parameter must be \"left\" or \"right\".\n" + if type not in ( "logical", "arith", "circular" ) : raise "\n[Stratus ERROR] Shift : The type parameter must be \"logical\" or \"arith\" or \"circular\".\n" + + # Creation of the output net with the right size + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, inputNet._arity )] + + # Initialisation of shiftType + if direction is "left" : + if type is "logical" : shiftType = 0x12 + elif type is "arith" : shiftType = 0xa + else : shiftType = 0x6 + else : + if type is "logical" : shiftType = 0x11 + elif type is "arith" : shiftType = 0x9 + else : shiftType = 0x5 + + inst_name = self._st_cell._shift.lower() + inst_name = re.sub ( "\.", "_", inst_name ) + inst_name += "_" + inst_name += type + inst_name += "_" + inst_name += str(inputNet._arity) + inst_name += "bits" + + Generate ( self._st_cell._shift, inst_name, param = { 'nbit' : inputNet._arity, 'type' : shiftType } ) + Inst ( inst_name + , map = { 'cmd' : self + , 'i' : inputNet + , 's' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + return cell._TAB_NETS_OUT[num_net] + + ##### Register ##### + def Reg ( self, inputNet ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not inputNet._arity : raise "\n[Stratus ERROR] Reg : The input net does not have a positive arity.\n" + if not self._arity : raise "\n[Stratus ERROR] Reg : The clock does not have a positive arity.\n" + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] there is no alim.\n" + + # Creation of the output net with the right size + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, inputNet._arity )] + +# if ( self._st_cell._reg == "Sff1" ) and ( inputNet._arity == 1 ) : +# inst_name = "sff1" +# else : +# inst_name = self._st_cell._reg.lower() +# inst_name = re.sub ( "\.", "_", inst_name ) +# inst_name += "_" +# inst_name += str(inputNet._arity) +# inst_name += "bits" +# +# Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } ) + + inst_name = self._st_cell._reg.lower() + inst_name = re.sub ( "\.", "_", inst_name ) + inst_name += "_" + inst_name += str(inputNet._arity) + inst_name += "bits" + + Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } ) + + Inst ( inst_name + , map = { 'i' : inputNet + , 'ck' : self + , 'q' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + return cell._TAB_NETS_OUT[num_net] + + ##### Multiplexor ##### + def Mux ( self, nets ) : + + maxPossibility = pow ( 2, self._arity ) - 1 + + ### List ### + if type ( nets ) == types.ListType : + if len ( nets ) != ( maxPossibility + 1 ) : + raise "\n[Stratus ERROR] Mux : when using a list, all the nets must be precised. Maybe one should use a dictionnary.\n" + + return self.muxList ( nets ) + + ### Dictionnary : Creation of the corresponding list ### + elif type ( nets ) == types.DictType : + + # Initialisation of the by default to 0 net if no default net given + if "default" not in nets : nets["default"] = 0 + + # Traitement of lists, intervals and numbers + for net in nets.keys () : + if re.search ( "-", net ) or re.search ( ",", net ) or re.search ( "#", net ) : + chaine = net + while chaine : + interval = re.search ( "^([0-9]+)-([0-9]+)", chaine ) + chiffre = re.search ( "^([0-9]+)", chaine ) + diese = re.search ( "^#([0-9\?]+)", chaine ) + + ############# + if interval : + nb1 = int ( interval.group(1) ) + nb2 = int ( interval.group(2) ) + + # Error : wrong interval + if nb1 >= nb2 : + raise "\n[Stratus ERROR] Mux : when an interval is specified, the second number of the interval must be the greater one.\n" + # Error : if the interval does not correspond to the lenght of the command + if ( nb1 > maxPossibility ) or ( nb2 > maxPossibility ) : + raise "\n[Stratus ERROR] Mux : One key does not match with the arity of the input nets.\n" + + for i in range ( nb1, nb2+1 ) : nets[i] = nets[net] + + # Next element + temp = re.search ( "^[0-9]+-[0-9]+,(.+)$", chaine ) + if temp : chaine = str ( temp.group(1) ) + else : chaine = None + + ############## + elif chiffre : + if int ( chiffre.group(0) ) > maxPossibility : + raise "\n[Stratus ERROR] Mux : One key does not match with the arity of the input nets.\n" + + nets[int(chiffre.group(0))] = nets[net] + + # Next element + temp = re.search ( "^[0-9]+,(.+)$", chaine ) + if temp : chaine = str ( temp.group(1) ) + else : chaine = None + + ############ + elif diese : + binaire = diese.group ( 1 ) + + # Error : if the binary number does not correspond to the lenght of the command + if len ( binaire ) != self._arity : + err = "\n[Stratus ERROR] Mux : the binary number " + str(binaire) \ + + " does not match with the lenght of the command. It has to be a " + str(self._arity) + "bits number.\n" + raise err + + # Error : if the number is not binary + for n in binaire : + if n not in ( "0", "1", "?", "#" ) : + err = "\n[Stratus ERROR] Mux : after #, the number has to be binary.\n" + raise err + + nombrebit = self._arity + + nb = 0 + for i in range ( -1, -nombrebit - 1, -1 ) : + if binaire[i] == "1" : nb += pow ( 2, -i - 1 ) + + nombres = [] + premierpassage = 1 + for i in range ( -1, -nombrebit - 1, -1 ) : + if binaire[i] == "?" : + if premierpassage : + nombres += [nb] + nombres += [nb + pow ( 2, -i - 1 )] + premierpassage = 0 + else : + enplus = [] + for chaquenombre in nombres : enplus += [chaquenombre + pow ( 2, -i - 1 )] + nombres += enplus + + for chaquenombre in nombres : nets[chaquenombre] = nets[net] + + # Next element + temp = re.search ( "^#.*,(.+)$", chaine ) + if temp : chaine = str ( temp.group (1) ) + else : chaine = None + + else : + err = "\n[Stratus ERROR] Mux : wrong key.\n" + raise err + + del nets[net] + + # Otherwise it must be a number : + elif re.search ( "^[0-9]+$", net ) : + chaine = re.search ( "^([0-9]+)$", net ) + chiffre = str ( chaine.group ( 1 ) ) + + if int ( chiffre ) > maxPossibility : + err = "\n[Stratus ERROR] Mux : One key does not match with the arity of the input nets.\n" + raise err + + nets[int(chiffre)] = nets[chiffre] + del nets[chiffre] + + else : + if net != "default" : + err = "\n[Stratus ERROR] Mux : wrong key.\n" + raise err + + clefs = nets.keys () + clefs.sort () + + # Covering of the keys wich are not default + lenClefs = 0 + for c in clefs : + if c != "default" : lenClefs += 1 + + liste = [] + decalage = 0 + for i in range ( lenClefs ) : + nb = clefs[i] + nb2 = i + decalage + if nb2 < nb : + while nb2 < nb : + liste.append ( nets["default"] ) + nb2 += 1 + decalage += 1 + liste.append ( nets[clefs[i]] ) # it is the right one + else : + liste.append ( nets[clefs[i]] ) + + # Number of wanted nets : + lenList = pow ( 2, self._arity ) + + # If nets are missing theu are default nets + while len ( liste ) < lenList : liste.append ( nets["default"] ) + + # Creation of the list corresponding to the dictionnary + return self.muxList ( liste ) + + # Error : wrong argument + else : + err = "\n[Stratus ERROR] Mux : wrong argument type.\n" + raise err + + + ### List ### + def muxList ( self, nets ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n" + + long = 0 + for i in range ( len ( nets ) ) : + if nets[i] : long = nets[i]._arity + + # Error : if no input net + if not ( long ) : raise "\n[Stratus ERROR] Mux : there are no input nets.\n" + + # Instanciation of a zero cell if needed + for net in nets : + if net == 0 : + from st_const import Zero + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "sig0_%d" % num_net, long )] + cell._TAB_NETS_OUT[num_net] <= Zero ( long ) + break + + # Creation of the map + map_mux = { 'cmd' : self + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + + i = 0 + for net in nets : + if net : map_mux['i%d' % i] = net + else : map_mux['i%d' % i] = cell._TAB_NETS_OUT[num_net] + + i += 1 + + # Initialisation of the output net + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, long )] + + map_mux ['q'] = cell._TAB_NETS_OUT[num_net] + + inst_name = self._st_cell._mux.lower() + inst_name = re.sub ( "\.", "_", inst_name ) + inst_name += "_" + inst_name += str(long) + inst_name += "bits" + inst_name += "_" + inst_name += str(self._arity) + inst_name += "cmd" + + Generate ( self._st_cell._mux, inst_name, param = { 'nbit' : long, 'nbit_cmd' : self._arity } ) + Inst ( inst_name, map = map_mux ) + + return cell._TAB_NETS_OUT[num_net] + + + ##### Comparison functions ##### + def Eq ( self, nb ) : return self.comparaison ( nb, True ) + def Ne ( self, nb ) : return self.comparaison ( nb, False ) + + # TODO : it could work with un string representing binary, decimal, or hexadecimal + def comparaison ( self, nb, egal ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : threre is no alim.\n" + + # Initialisation of the output net + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, 1 )] + + inst_name = self._st_cell._comp.lower() + inst_name = re.sub ( "\.", "_", inst_name ) + inst_name += "_" + inst_name += str(self._arity) + inst_name += "bits" + inst_name += "_" + inst_name += str(nb) + if egal : inst_name += "egal" + + Generate ( self._st_cell._comp, inst_name, param = { 'nbit' : self._arity, 'nb' : nb, 'egal' : egal } ) + Inst ( inst_name + , map = { "netin" : self + , "netout" : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + return cell._TAB_NETS_OUT[num_net] + + + ##### Method Alias ##### + def Alias ( self, net ) : + + # Error : if the net already has an alias + if net._alias : + err = "\n[Stratus ERROR] Alias : the net " + net._name + " is already an alias.\n" + raise err + + # Resizement of the net if needed + if not ( net._arity ) : net.create_net ( net._name, self._arity ) + + # Error : if the nets don't have the same lenght + if self._arity != net._arity : + err = "\n[Stratus ERROR] Alias : the nets " + self._name + " and " + net._name + " must have the same lenght\n" + raise err + + # If nets are virtual, let's work with the corresponding real nets + if net._real_net : realNet = net._real_net + else : realNet = net + + if self._real_net : realSelf = self._real_net + else : realSelf = self + + # Construction of the tab if needed + if not ( len ( realNet._alias ) ) : + for i in range ( realNet._arity ) : realNet._alias.append ( 0 ) + + # Initialisation of _alias + for i in range ( net._ind, net._ind + net._arity ) : + + if not realSelf._alias : + realNet._alias[i] = {realSelf : i + self._ind - net._ind} + # Alias of an alias + else : + err = "\n[Stratus ERROR] Alias : 2 Alias in a row are not supported.\n" + raise err + # FIXME bug : for now, Alias of Alias are not permitted +# if realSelf._alias[i + self._ind - net._ind] : +# netAlias = realSelf._alias[i + self._ind - net._ind].keys()[0] +# bitAlias = realSelf._alias[i + self._ind - net._ind][netAlias] +# if netAlias._real_net : netAlias = netAlias._real_net +# realNet._alias[i] = {netAlias : bitAlias} +# # Error : more than 2 Alias in a row not supported +# if netAlias._alias : +# err = "\n[Stratus ERROR] Alias : more than 2 Alias in a row are not supported.\n" +# raise err +# else : +# realNet._alias[i] = {realSelf : i + self._ind - net._ind} + + ##### Method Extend ##### + def Extend ( self, width, type ) : + global CELLS + + from st_model import CELLS + from st_const import Zero, One + + cell = CELLS[-1] + + if self._arity >= width : + err = "\n[Stratus ERROR] Extend : the net " + self._name + \ + " can not be extended to " + str(width) + " bits, it's arity is already " + str(self._arity) + ".\n" + raise err + + num_net = len ( cell._TAB_NETS_OUT ) + cell._TAB_NETS_OUT += [Signal ( "%s_ext_%d_%d" % ( self._name, width, num_net ), width )] + + name = "extend_%d_%d_%s" % ( self._arity, width, type ) + + Generate ( "Extend", name, param = { 'nbit0' : self._arity, 'nbit1' : width, 'type' : type } ) + + Inst ( name + , map = { 'i' : self + , 'o' : cell._TAB_NETS_OUT[num_net] + , 'vdd' : cell._st_vdds[0] + , 'vss' : cell._st_vsss[0] + } + ) + + return cell._TAB_NETS_OUT[num_net] + + ################################################################################################################################## + ##### Initialisation of nets ##### + def create_net ( self, nom, nbit, indice = 0, extern = False, direction = None, hType = None ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + # Error : + if re.search ( "[A-Z]", nom ) : + print "[Stratus Warning] : Upper case letters are not supported, the name", nom, "is lowered." + nom.lower () + if re.search ( " ", nom ) : + chaine = re.search ( "st_net\.(.*)", str ( self.__class__ ) ) + classe = chaine.group(1) + err = "\n[Stratus ERROR] " + classe + " : \"" + nom + "\" the name of the net can not contain a space.\n" + raise err + + self._st_cell = cell + self._name = nom + self._arity = nbit + self._ind = indice + self._hur_net = [] + self._alias = [] + self._to_merge = [] + self._to_cat = [] + self._real_net = None + self._ext = extern + if extern : self._direct = direction + + # Error : + if ( nbit == 1 ) and indice : + err = "\n[Stratus ERROR] " + str ( self.__class__ ) + " : " + self._name + " : one can not put an indice for a 1 bit net.\n" + raise err + + if hType : + self._h_type = hType + if hType == "POWER" : self._st_cell._st_vdds.append ( self ) + elif hType == "GROUND" : self._st_cell._st_vsss.append ( self ) + elif hType == "CLOCK" : self._st_cell._st_cks.append ( self ) + + # The net is put in the nets list of the cell + else : + if nbit : + if extern : self._st_cell._st_ports.append ( self ) + else : self._st_cell._st_sigs.append ( self ) + + # Creation of the hurricane net if in hurricane mode + if self._st_cell._hur_cell : self.create_hur_net() + + ##### Initialisation of the hurricane nets for part nets ##### + def create_part_hur_net ( self ) : + if self._ind2 < self._ind : pas = -1 + else : pas = 1 + + if self._real_net._hur_net : # FIXME a priori pb du a l outil d optimisation + for i in range ( self._ind, self._ind2 + pas, pas ) : self._hur_net.append ( self._real_net._hur_net[i] ) + + ##### Initialisation of the hurricane nets ##### + def create_hur_net ( self ) : + if self._arity == 1 : + self.hur_net ( self._name, 0 ) + else : + for i in range ( self._ind, self._arity+self._ind ) : self.hur_net ( self._name + "(" + str(i) + ")", i ) + + ##### hur_net one by one ##### + def hur_net ( self, name, ind ) : + if ( self._alias ) and ( self._alias[ind] ) : + self._hur_net += [self._alias[ind].keys()[0]] # put the right hur_net + return + elif ( self._to_cat ) and ( self._to_cat[ind] ) : + cat = self._to_cat[ind] + self._hur_net += [cat[0]._hur_net[cat[1]]] + return + + net = Net ( self._st_cell._hur_cell, name ) + + net.setType ( TypeLOGICAL ) + + if self._ext : net.setExternal ( True ) + else : net.setExternal ( False ) + + if self._ext : + if self._direct == "IN" : net.setDirection ( DirectionIN ) + elif self._direct == "OUT" : net.setDirection ( DirectionOUT ) + elif self._direct == "INOUT" : net.setDirection ( DirectionINOUT ) + elif self._direct == "TRISTATE" : net.setDirection ( DirectionTRISTATE ) + elif self._direct == "UNKNOWN" : net.setDirection ( DirectionUNDEFINED ) + + if '_h_type' in self.__dict__ : + if self._h_type == "POWER" : net.setType ( TypePOWER ) + elif self._h_type == "GROUND" : net.setType ( TypeGROUND ) + elif self._h_type == "CLOCK" : net.setType ( TypeCLOCK ) + + self._hur_net += [net] + + ##### Hurricane merge ##### + def hur_merge ( self ) : + if self._real_net : realNet = self._real_net + else : realNet = self + + if self._to_cat : + err = "\n[Stratus ERROR] HurricanePlug <= : net " + self._name + " is a Cat net. Forbidden utilisation of <= and Cat.\n" + raise err + + for i in range ( self._ind, self._arity + self._ind ) : + if realNet._to_merge[i] : + + selfToMerge = realNet._to_merge[i][0] + bitToMerge = realNet._to_merge[i][1] + + if selfToMerge._hur_net == [] : + print "[Stratus Warning] HurricanePlug <= : net", selfToMerge._name, "has no hurricane net." + return + + if realNet._hur_net == [] : + err = "\n[Stratus ERROR] HurricanePlug <= : net " + realNet._name + " has no hurricane net.\n" + raise err + + if bitToMerge > ( len ( selfToMerge._hur_net ) - 1 ) : + err = "\n[Stratus ERROR] HurricanePlug <= : net " + selfToMerge._name + " with hur_net : " + str(selfToMerge._hur_net) \ + + " with asked bit : " + str(bitToMerge) + ".\n" + raise err + if i > ( len ( realNet._hur_net ) - 1 ) : + err = "\n[Stratus ERROR] HurricanePlug <= : net " + realNet._name + " with hur_net : " + str(realNet._hur_net) \ + + " with asked bit : " + str(i) + ".\n" + raise err + + selfToMerge._hur_net[bitToMerge].merge ( realNet._hur_net[i] ) +# realNet._hur_net[i] = 0 + +# realNet.Delete() +# del realNet + + ##### Initialisation from a net hurricane ##### + def create_from_hur ( self, hur_net ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + self._st_cell = cell + self._alias = [] + self._to_merge = [] + self._to_cat = [] + self._real_net = None + + self._arity = 1 + self._ind = 0 + + self._name = str ( hur_net.getName() ) + + if hur_net.isExternal() : self._ext = True + else : self._ext = False + + if hur_net.isExternal() : + if hur_net.getDirection() == DirectionIN : self._direct = "IN" + elif hur_net.getDirection() == DirectionOUT : self._direct = "OUT" + elif hur_net.getDirection() == DirectionINOUT : self._direct = "INOUT" + elif hur_net.getDirection() == DirectionTRISTATE : self._direct = "TRISTATE" + elif hur_net.getDirection() == DirectionUNDEFINED : self._direct = "UNDEFINED" + + if hur_net.getType() == TypePOWER : self._h_type = "POWER" + elif hur_net.getType() == TypeGROUND : self._h_type = "GROUND" + elif hur_net.getType() == TypeCLOCK : self._h_type = "CLOCK" + + self._hur_net = [hur_net] + + if ( self._ext ) and ( '_h_type' in self.__dict__ ) : + if self._h_type == "CLOCK" : cell._st_ports.append ( self ) # not alimentations + else : + cell._st_sigs.append ( self ) + +########### +# SignalIn # +########### +class SignalIn ( net ) : + def __init__ ( self, nom, nbit, indice = 0 ) : + + if nbit < 1 : raise "\n[Stratus ERROR] SignalIn : the lenght of the net must be a positive value\n" + + self.create_net ( nom, nbit, indice, True, "IN" ) + +class SignalInFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) + +############ +# SignalOut # +############ +class SignalOut ( net ) : + def __init__ ( self, nom, nbit, indice = 0 ) : + + if nbit < 1 : raise "\n[Stratus ERROR] SignalOut : the lenght of the net must be a positive value\n" + + self.create_net ( nom, nbit, indice, True, "OUT" ) + +class SignalOutFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) + +############## +# SignalInOut # +############## +class SignalInOut ( net ) : + def __init__ ( self, nom, nbit, indice = 0 ) : + + if nbit < 1 : raise "\n[Stratus ERROR] SignalInOut : the lenght of the net must be a positive value\n" + + self.create_net ( nom, nbit, indice, True, "INOUT" ) + +class SignalInOutFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) + +################ +# SignalUnknown # +################ +class SignalUnknown ( net ) : + def __init__ ( self, nom, nbit, indice = 0 ) : + + if nbit < 1 : raise "\n[Stratus ERROR] SignalUnknown : the lenght of the net must be a positive value\n" + + self.create_net ( nom, nbit, indice, True, "UNKNOWN" ) + +class SignalUnknownFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) + +############ +# TriState # +############ +class TriState ( net ) : + def __init__ ( self, nom, nbit, indice = 0 ) : + + if nbit < 1 : raise "\n[Stratus ERROR] TriState : the lenght of the net must be a positive value\n" + + self.create_net ( nom, nbit, indice, True, "TRISTATE" ) + +class SignalTriStateFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) + +######### +# Clock # +######### +class CkIn ( net ) : + def __init__ ( self, nom ) : + self.create_net ( nom, 1, extern = True, direction = "IN", hType = "CLOCK" ) + +class CkInFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) + +################### +# Internal Signal # +################### +class Signal ( net ) : + def __init__ ( self, nom, nbit = 0, indice = 0 ) : + + if nbit < 0 : raise "\n[Stratus ERROR] Signal : the lenght of the net must be a positive value\n" + + self.create_net ( nom, nbit, indice ) + +class SignalFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) + +################ +# Alimentation # +################ +class VddIn ( net ) : + def __init__ ( self, nom ) : self.create_net ( nom, 1, extern = True, direction = "IN", hType = "POWER" ) +class VssIn ( net ) : + def __init__ ( self, nom ) : self.create_net ( nom, 1, extern = True, direction = "IN", hType = "GROUND" ) + +class VddInFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) +class VssInFromHur ( net ) : + def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net ) + +################## +# Virtual signal # +################## +class Sig ( net ) : + def __init__ ( self, net, indiceFort, indiceFaible = -1 ) : + global CELLS + from st_model import CELLS + + if indiceFaible == -1 : indiceFaible = indiceFort + + self._st_cell = CELLS[-1] + self._ind = indiceFaible + self._ind2 = indiceFort + self._alias = [] + self._to_merge = [] + self._to_cat = [] + self._real_net = net + self._ext = net._ext + self._arity = abs ( indiceFort - indiceFaible ) + 1 + + if indiceFort < indiceFaible : self._reverse = True + else : self._reverse = False + + self._hur_net = [] + + self._st_cell._st_partsigs.append ( self ) + + # Initialisation of _hur_net if in hurricanePlug mode +# if CELLS[0]._hur_plug : self.create_part_hur_net() + + if self._ext : self._direct = net._direct + + if '_h_type' in net.__dict__ : self._h_type = net._h_type + + if indiceFort == indiceFaible : self._name = net._name + "[" + str(indiceFaible) + "]" + else : self._name = net._name + "[" + str(indiceFort) + ":" + str(indiceFaible) + "]" diff --git a/stratus1/src/stratus/st_param.py b/stratus1/src/stratus/st_param.py new file mode 100644 index 00000000..aee523ef --- /dev/null +++ b/stratus1/src/stratus/st_param.py @@ -0,0 +1,76 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_param.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +import getopt, sys, re, types + +####################### +def Param ( *tokens ) : + + try : + argum = "" + for i in range ( len ( tokens ) ) : argum += "%s:" + opts = getopt.getopt ( sys.argv[1:], argum % tokens )[0] + + except getopt.GetoptError : + raise "\n[Stratus ERROR] Param.\n" + + if opts == [] : + raise "\n[Stratus ERROR] Param : there is no parameter.\n" + + n = [] + for option, argument in opts : + for i in range ( len ( tokens ) ) : + if option in ( "-%s" % tokens[i] ) : + if re.search ( "^[0-9]+$", argument ) : n.insert ( i, int ( argument ) ) + elif re.search ( "^[0-9]+\.?[0-9]*e?-?[0-9]+$", argument ) : n.insert ( i, float ( argument ) ) + else : n.insert ( i, argument ) # By default, type is str + + if len ( n ) == 1 : return n[0] + + return n diff --git a/stratus1/src/stratus/st_parser.py b/stratus1/src/stratus/st_parser.py new file mode 100644 index 00000000..4297710c --- /dev/null +++ b/stratus1/src/stratus/st_parser.py @@ -0,0 +1,215 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_parser.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + +import xml.parsers.expat +import re, types + +BV = [] +BVg = [] + +I = [] +I0 = [] +I2 = [] +I3 = [] +A = [] + +CK = [] +CMD = [] +CMD0 = [] +CIN = [] + +Q = [] +NQ = [] +S = [] + +############## +class Parser : + + def __init__ ( self ) : + self._p = xml.parsers.expat.ParserCreate () + + self._p.StartElementHandler = self.start_element + self._p.EndElementHandler = self.end_element + self._p.CharacterDataHandler = self.char_data + + self._realCell = {} + self._inOut = {} + + # Handler functions + + ######################################### + def start_element ( self, name, attrs ) : + # Print which the technology is +# if name == 'technology' : +# print "Technology is :", attrs['name'] + + # Modification of attributes + if name == 'model' : + virtName = str(attrs['name']) + + self._realCell[virtName] = str(attrs['realcell']) + + inOutTemp = {} + for key in attrs : + if key not in ( 'name', 'realcell' ) : + inOutTemp[str(key)] = str(attrs[str(key)]) + + self._inOut[str(attrs['name'])] = inOutTemp + + ################################ + def end_element ( self, name ) : pass + + ############################## + def char_data ( self, data ) : pass # print repr(data) + + # Parsing a file + ################ + def Parse ( self, nameFile ) : + self._p.ParseFile ( open ( nameFile, "r" ) ) + +################## +class InitParser : + + def __init__ ( self ) : + self._p = xml.parsers.expat.ParserCreate () + + self._p.StartElementHandler = self.start_element + self._p.EndElementHandler = self.end_element + self._p.CharacterDataHandler = self.char_data + + self._realCell = {} + self._inOut = {} + + # Handler functions + + ######################################### + def start_element ( self, name, attrs ) : + global BV, I, I0, I2, I3, A, CK, CMD, CMD0, CIN, Q, NQ, S + + # Modification of attributes + if name == 'model' : + virtName = str(attrs['name']) + BV.append ( virtName ) + + for key in attrs : + if key == 'i' : I.append ( virtName ) + elif key == 'i0' : I0.append ( virtName ) + elif key == 'i2' : I2.append ( virtName ) + elif key == 'i3' : I3.append ( virtName ) + elif key == 'a' : A.append ( virtName ) + elif key == 'ck' : CK.append ( virtName ) + elif key == 'cmd' : CMD.append ( virtName ) + elif key == 'cmd0' : CMD0.append ( virtName ) + elif key == 'cin' : CIN.append ( virtName ) + elif key == 'q' : Q.append ( virtName ) + elif key == 'nq' : NQ.append ( virtName ) + elif key == 'sout' : S.append ( virtName ) + + ################################ + def end_element ( self, name ) : pass + + ############################## + def char_data ( self, data ) : pass # print repr(data) + + # Parsing a file + ################ + def Parse ( self, nameFile ) : + self._p.ParseFile ( open ( nameFile, "r" ) ) + + # Givien the tab of the name of the cells, contruction of a tab giving the name of the generators (first letter uppered) + for name in BV : + chaine = re.search ( "([a-z])(.+)", name ) + name_g = chaine.group(1).upper() + chaine.group(2) + BVg.append ( name_g ) + +############## +class WeightParser : + + def __init__ ( self ) : + self._p = xml.parsers.expat.ParserCreate () + + self._p.StartElementHandler = self.start_element + self._p.EndElementHandler = self.end_element + self._p.CharacterDataHandler = self.char_data + + self._weightTime = {} + self._weightArea = {} + + # Handler functions + + ######################################### + def start_element ( self, name, attrs ) : + if name == 'model' : + virtName = str(attrs['name']) + + if 'time' in attrs : + temp = float(attrs['time']) + else : +# print 'Warning: no weight done in the file, weight put to 1.' + temp = 1 + + self._weightTime[virtName] = temp + + if 'area' in attrs : + temp = float(attrs['area']) + else : +# print 'Warning: no weight done in the file, weight put to 1.' + temp = 1 + + self._weightArea[virtName] = temp + + ################################ + def end_element ( self, name ) : pass + + ############################## + def char_data ( self, data ) : pass # print repr(data) + + # Parsing a file + ################ + def Parse ( self, nameFile ) : + self._p.ParseFile ( open ( nameFile, "r" ) ) diff --git a/stratus1/src/stratus/st_placeAndRoute.py b/stratus1/src/stratus/st_placeAndRoute.py new file mode 100644 index 00000000..3ec23931 --- /dev/null +++ b/stratus1/src/stratus/st_placeAndRoute.py @@ -0,0 +1,344 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@lip6.fr | +# | =============================================================== | +# | Py Module : "./st_placeAndRoute.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +import CRL +from placeandroute import * +from st_net import * + +import re, string + +global nbCkBuf +nbCkBuf = 0 + + +############### +## PlaceGlue ## +############### +def PlaceGlue ( cell = None, tool = "mistral", greedy = True, nparts = 0 ) : + + if not cell : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if isinstance ( cell, Model ) : # FIXME : a changer, mettre toujours un model et faire utiliser aux etudiants de l'annee prochaine getModel + pyPlaceGlue ( cell._hur_cell ) + + if isinstance ( cell, Inst ) : + pyPlaceGlue ( cell._st_masterCell._hur_cell ) + + +################## +## PlaceCentric ## +################## +def PlaceCentric ( instance ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + pyPlaceCentric ( cell._hur_cell, instance._hur_instance ) + +###################### +## AlimVerticalRail ## +###################### +def AlimVerticalRail ( coordonnee ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + pyAlimVerticalRail ( cell._hur_cell, coordonnee ) + +######################## +## AlimHorizontalRail ## +######################## +def AlimHorizontalRail ( coordonnee ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + pyAlimHorizontalRail ( cell._hur_cell, coordonnee ) + +#################### +## AlimConnectors ## +#################### +def AlimConnectors () : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + pyAlimConnectors ( cell._hur_cell ) + +############# +## RouteCk ## +############# +def RouteCk ( net ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + pyRouteCk ( cell._hur_cell, net._hur_net[0] ) + +################# +## GlobalRoute ## +################# +def GlobalRoute ( cell = None ): + if not cell: + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if isinstance ( cell, Model ): # FIXME : a changer, mettre toujours un model et faire utiliser aux etudiants de l'annee prochaine getModel + pyGlobalRoute ( cell._hur_cell ) + if isinstance ( cell, Inst ): + pyGlobalRoute ( cell._st_masterCell._hur_cell ) + return + +################### +## DetailRoute ## +################### +def DetailRoute ( cell = None ): + if not cell: + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if isinstance ( cell, Model ) : # FIXME : a changer, mettre toujours un model et faire utiliser aux etudiants de l'annee prochaine getModel + pyDetailRoute ( cell._hur_cell ) + if isinstance ( cell, Inst ) : + pyDetailRoute ( cell._st_masterCell._hur_cell ) + return + +########################## +## TimingStaticAnalysis ## +########################## +#def TimingStaticAnalysis ( cell = None ): +# if not cell: +# global CELLS +# from st_model import CELLS +# +# cell = CELLS[-1] +# +# if isinstance ( cell, Model ): # FIXME : a changer, mettre toujours un model et faire utiliser aux etudiants de l'annee prochaine getModel +# pyTimingStaticAnalysis ( cell._hur_cell ) +# if isinstance ( cell, Inst ): +# pyTimingStaticAnalysis ( cell._st_masterCell._hur_cell ) +# return + + +############## +## PadNorth ## +############## +def PadNorth ( *args ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + hur_core = cell.getCore() + + hur_args = [] + for arg in args : + if not arg : + raise "\n[Stratus ERROR] PadNorth : one instance doesn't exist.\n" + if str ( arg.__class__ ) != "st_instance.Inst" : + raise "\n[Stratus ERROR] PadNorth : one argument is not an instance.\n" + + hur_args.append ( arg._hur_instance ) + + pyPadNorth ( cell._hur_cell, hur_core, hur_args ) + +############## +## PadSouth ## +############## +def PadSouth ( *args ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + hur_core = cell.getCore() + + hur_args = [] + for arg in args : + if not arg : + raise "\n[Stratus ERROR] PadSouth : one instance doesn't exist.\n" + if str ( arg.__class__ ) != "st_instance.Inst" : + raise "\n[Stratus ERROR] PadSouth : one argument is not an instance.\n" + + hur_args.append ( arg._hur_instance ) + + pyPadSouth ( cell._hur_cell, hur_core, hur_args ) + +############# +## PasEast ## +############# +def PadEast ( *args ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + hur_core = cell.getCore() + + hur_args = [] + for arg in args : + if not arg : + raise "\n[Stratus ERROR] PadEast : one instance doesn't exist.\n" + if str ( arg.__class__ ) != "st_instance.Inst" : + raise "\n[Stratus ERROR] PadEast : one argument is not an instance.\n" + + hur_args.append ( arg._hur_instance ) + + pyPadEast ( cell._hur_cell, hur_core, hur_args ) + +############# +## PadWest ## +############# +def PadWest ( *args ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + hur_core = cell.getCore() + + hur_args = [] + for arg in args : + if not arg : + raise "\n[Stratus ERROR] PadWest : one instance doesn't exist.\n" + if str ( arg.__class__ ) != "st_instance.Inst" : + raise "\n[Stratus ERROR] PadWest : one argument is not an instance.\n" + + hur_args.append ( arg._hur_instance ) + + pyPadWest ( cell._hur_cell, hur_core, hur_args ) + +############### +## PowerRing ## +############### +def PowerRing ( n ) : + global CELLS + from st_model import CELLS + + cell = CELLS[-1] + + if n < 3 : raise "\n[Stratus ERROR] : PowerRing : must have at least 3 pairs of vdd/vss rings\n" + + hur_core = cell.getCore() + + pyPowerRing ( cell._hur_cell, hur_core, n ) + + +################# +## ClockBuffer ## +################# +class ClockBuffer : + def __init__ ( self, netname ) : + global CELLS + from st_model import CELLS + global nbCkBuf + self.cell = CELLS[-1] + + self.net = self.cell._hur_cell.getNet ( netname ) + self.ck_b = Signal ( "ck_b%d"%nbCkBuf, 1 ) + + modelMasterCell = CRL.getAllianceFramework().getCell ( "buf_x2", CRL.Catalog.State.Views ) + if not modelMasterCell : + err = "Stratus Error : ClockBuffer : Cannot find model cell : buf_x2 in database !\n" + raise err + + inst = Instance ( self.cell._hur_cell, "ck_buffer%d"%nbCkBuf, modelMasterCell ) + nbCkBuf += 1 + + ##### Connection ##### + plugI = inst.getPlug ( modelMasterCell.getNet ( "i" ) ) + plugI.setNet ( self.net ) + + plugQ = inst.getPlug ( modelMasterCell.getNet ( "q" ) ) + plugQ.setNet ( self.ck_b._hur_net[0] ) + + plugGround = inst.getPlug ( iter(modelMasterCell.getGroundNets()).next() ) + plugGround.setNet ( iter(self.cell._hur_cell.getGroundNets()).next() ) + + plugPower = inst.getPlug ( iter(modelMasterCell.getPowerNets()).next() ) + plugPower.setNet ( iter(self.cell._hur_cell.getPowerNets()).next() ) + + def AddFF ( self, netname ) : + net = self.cell._hur_cell.getNet ( netname ) + if not net : + err = "AddFF Error net : " + netname + " not found" + raise err + + instDrive = None + for plug in net.getPlugs(): + if plug.getMasterNet().getDirection() == DirectionOUT : + instDrive = plug.getInstance() + break + + if instDrive == None : + err = "AddFF Error no drive instance found for net " + netname + ".\n" + raise err + + masterCell = instDrive.getMasterCell() + ## ici il vaudrait mieux faire une recherche sur l'ensemble des plugs de l'instDrive et trouver celle accrochee au self.net ## + netCk = masterCell.getNet ( "ck" ) + if instDrive.getPlug ( netCk ).getNet() != self.net : + err = "Stratus Error : AddFF : driver Instance of net " + netname + " is not connected to signal " + str ( self.net.getName() ) + ".\n" + raise err + + instDrive.getPlug ( netCk ).setNet ( self.ck_b._hur_net[0] ) diff --git a/stratus1/src/stratus/st_placement.py b/stratus1/src/stratus/st_placement.py new file mode 100644 index 00000000..94fcc788 --- /dev/null +++ b/stratus1/src/stratus/st_placement.py @@ -0,0 +1,537 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_placement.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from Hurricane import * + +from util_Place import * + +########### +def Place ( ins, sym, ref, plac = FIXED, cell = None ) : + global MYPITCH, MYSLICE + + # Error if x and y found not permitted : + if ref._x % MYPITCH : + err = "\n[Stratus ERROR] Place : " + ins._name + " : coordinate x is not a mutiple of PITCH.\n" + raise err + + if ref._y % MYSLICE : + err = "\n[Stratus ERROR] Place : " + ins._name + " : coordinate y is not a mutiple of SLICE.\n" + raise err + + # Error message : if ref is not a reference + if str ( ref.__class__ ) != "st_ref.XY" : + raise "\n[Stratus ERROR] Place : wrong argument for placement, the coordinates must be put in a XY object.\n" + + # Error message if plac is not one of the permitted values + if ( plac != PLACED ) and ( plac != FIXED ) : raise "\n[Stratus ERROR] Place : wrong argument for placement type.\n" + + #placement ( ins, sym, getUnit(ref._x), getUnit(ref._y), plac, cell = cell ) + placement ( ins, sym, DbU_lambda(ref._x), DbU_lambda(ref._y), plac, cell = cell ) + +############### +def PlaceTop ( ins, symetry, offsetX = 0, offsetY = 0, plac = FIXED ) : + global CELLS + from st_model import CELLS + + global MYPITCH, MYSLICE + + cell = CELLS[-1] + + if offsetX % MYPITCH : + err = "\n[Stratus ERROR] PlaceTop : " + ins._name + " : offsetX is not a mutiple of PITCH.\n" + raise err + + if offsetY % MYSLICE : + err = "\n[Stratus ERROR] PlaceTop : " + ins._name + " : offsetY is not a mutiple of SLICE.\n" + raise err + + if ( plac != PLACED ) and ( plac != FIXED ) : + err = "\n[Stratus ERROR] PlaceTop : " + ins._name + " : wrong argument for placement type.\n" + raise err + + if cell._insref == None : + err = "\n[Stratus ERROR] PlaceTop : " + ins._name + " : no previous instance.\n" + raise err + + x = cell._insref._x + y = cell._insref._y + + if droite ( cell._insref._sym ) : + if vertical ( cell._insref._sym ) : x -= width ( cell._insref ) + else : x -= height ( cell._insref ) + + if bas ( cell._insref._sym ) : + if vertical ( cell._insref._sym ) : y += height ( cell._insref ) + else : y += width ( cell._insref ) + + placement ( ins, symetry, x + DbU_lambda ( offsetX ), y + DbU_lambda ( offsetY ), plac ) + +################# +def PlaceRight ( ins, symetry, offsetX = 0, offsetY = 0, plac = FIXED ) : + global CELLS + from st_model import CELLS + + global MYPITCH, MYSLICE + + cell = CELLS[-1] + + if offsetX % MYPITCH : + err = "\n[Stratus ERROR] PlaceRight : " + ins._name + " : offsetX is not a mutiple of PITCH.\n" + raise err + + if offsetY % MYSLICE : + err = "\n[Stratus ERROR] PlaceRight : " + ins._name + " : offsetY is not a mutiple of SLICE.\n" + raise err + + if ( plac != PLACED ) and ( plac != FIXED ) : + err = "\n[Stratus ERROR] PlaceRight : " + ins._name + " : wrong argument for placement type.\n" + raise err + + if cell._insref == None : + err = "\n[Stratus ERROR] PlaceRight : " + ins._name + " : no previous instance.\n" + raise err + + x = cell._insref._x + y = cell._insref._y + + if gauche ( cell._insref._sym ): + if vertical ( cell._insref._sym ) : x += width ( cell._insref ) + else : x += height ( cell._insref ) + + if haut ( cell._insref._sym ) : + if vertical ( cell._insref._sym ) : y -= height ( cell._insref ) + else : y -= width ( cell._insref ) + + placement ( ins, symetry, x + DbU_lambda ( offsetX ), y + DbU_lambda ( offsetY ), plac ) + +################ +def PlaceLeft ( ins, symetry, offsetX = 0, offsetY = 0, plac = FIXED ) : + global CELLS + from st_model import CELLS + + global MYPITCH, MYSLICE + + cell = CELLS[-1] + + if offsetX % MYPITCH : + err = "\n[Stratus ERROR] PlaceLeft : " + ins._name + " : offsetX is not a mutiple of PITCH.\n" + raise err + + if offsetY % MYSLICE : + err = "\n[Stratus ERROR] PlaceLeft : " + ins._name + " : offsetY is not a mutiple of SLICE.\n" + raise err + + if ( plac != PLACED ) and ( plac != FIXED ) : + err = "\n[Stratus ERROR] PlaceLeft : " + ins._name + " : wrong argument for placement type.\n" + raise err + + if cell._insref == None : + err = "\n[Stratus ERROR] PlaceLeft : " + ins._name + " : no previous instance.\n" + raise err + + x = cell._insref._x + y = cell._insref._y + + sym = transformation ( symetry ) + + if droite ( cell._insref._sym ) : + if vertical ( cell._insref._sym ) : x -= width ( cell._insref ) + else : x -= height ( cell._insref ) + + if haut ( cell._insref._sym ) : + if vertical ( cell._insref._sym ) : y -= height ( cell._insref ) + else : y -= width ( cell._insref ) + + placement ( ins, symetry, x - DbU_lambda ( offsetX ), y + DbU_lambda ( offsetY ), plac, fonction = "Left" ) + +################## +def PlaceBottom ( ins, symetry, offsetX = 0, offsetY = 0, plac = FIXED ) : + global CELLS + from st_model import CELLS + + global MYPITCH, MYSLICE + + cell = CELLS[-1] + + if offsetX % MYPITCH : + err = "\n[Stratus ERROR] PlaceBottom : " + ins._name + " : offsetX is not a mutiple of PITCH.\n" + raise err + + if offsetY % MYSLICE : + err = "\n[Stratus ERROR] PlaceBottom : " + ins._name + " : offsetY is not a mutiple of SLICE.\n" + raise err + + if ( plac != PLACED ) and ( plac != FIXED ) : + err = "\n[Stratus ERROR] PlaceBottom : " + ins._name + " : wrong argument for placement type.\n" + raise err + + if cell._insref == None : + err = "\n[Stratus ERROR] PlaceBottom : " + ins._name + " : no previous instance.\n" + raise err + + x = cell._insref._x + y = cell._insref._y + + sym = transformation ( symetry ) + + if droite ( cell._insref._sym ) : + if vertical ( cell._insref._sym ) : x -= width ( cell._insref ) + else : x -= height ( cell._insref ) + + if haut ( cell._insref._sym ) : + if vertical ( cell._insref._sym ) : y -= height ( cell._insref ) + else : y -= width ( cell._insref ) + + placement ( ins, symetry, x + DbU_lambda ( offsetX ), y - DbU_lambda ( offsetY ), plac, fonction = "Bottom" ) + +################# +def SetRefIns ( ins ) : + global CELLS + from st_model import CELLS + + from util_Place import UNPLACED + + cell = CELLS[-1] + + # Error : SetRefIns on a non existing instance + if not ins : raise "\n[Stratus ERROR] SetRefIns : the instance doesn't exist.\n" + + # Error : SetRefIns on a non placed instance + if ins._plac == UNPLACED : + err = "\n[Stratus ERROR] SetRefIns : the instance " + ins._name + " is not placed.\n" + raise err + + cell._insref = ins + +############ +def DefAb ( ref1, ref2 ) : + global CELLS + from st_model import CELLS + + global MYSLICE, MYPITCH + + cell = CELLS[-1] + + UpdateSession.open () + + # Error message : if ref are not references + if ( str ( ref1.__class__ ) != "st_ref.XY" ) or ( str ( ref2.__class__ ) != "st_ref.XY" ) : + err = "\n[Stratus ERROR] DefAb : wrong argument, the coordinates must be put in a XY object.\n" + raise err + + x1 = ref1._x + y1 = ref1._y + x2 = ref2._x + y2 = ref2._y + + if not cell._hur_cell : + err = "\n[Stratus ERROR] Layout : The hurricane cell has not been created.\n" \ + + "One has to use HurricanePlug before creating the layout.\n" + raise err + + if x1 % MYPITCH or y1 % MYSLICE or x2 % MYPITCH or y2 % MYSLICE : + err = "\nError in DefAb : Coordinates of an abutment Box in y must be multiple of the slice.\n" \ + + " : Coordinates of an abutment Box in x must be multiple of the pitch.\n" + raise err + + boite = cell._hur_cell.getAbutmentBox () + + if not ( boite.isEmpty() ) : + err = "\n[Stratus ERROR] DefAb : an abutment box already exists for cell : " \ + + str ( cell._name ) \ + + ". Maybe you should use ResizeAb function.\n" + raise err + + cell._hur_cell.setAbutmentBox ( Box ( DbU_lambda ( x1 ) + , DbU_lambda ( y1 ) + , DbU_lambda ( x2 ) + , DbU_lambda ( y2 ) + ) + ) + + UpdateSession.close () + +############ +def ResizeAb ( dx1, dy1, dx2, dy2 ) : + global CELLS + from st_model import CELLS + + global MYSLICE, MYPITCH + + cell = CELLS[-1] + + hurCell = cell._hur_cell + ab = hurCell.getAbutmentBox() + + UpdateSession.open () + + if dx1 % MYPITCH or dy1 % MYSLICE or dx2 % MYPITCH or dy2 % MYSLICE : + err = "\n[Stratus ERROR] ResizeAb : Coordinates of an abutment Box in y must be multiple of the slice.\n" \ + + " : Coordinates of an abutment Box in x must be multiple of the pitch.\n" + raise err + + old_xmin = ab.getXMin() + old_xmax = ab.getXMax() + old_ymin = ab.getYMin() + old_ymax = ab.getYMax() + + new_xmin = old_xmin - DbU_lambda ( dx1 ) + new_ymin = old_ymin - DbU_lambda ( dy1 ) + new_xmax = old_xmax + DbU_lambda ( dx2 ) + new_ymax = old_ymax + DbU_lambda ( dy2 ) + + if new_xmin >= new_xmax : + err = "\n[Stratus ERROR] ResizeAb : one of the values of dx1 or dx2 is incompatible with the size of the abutment box.\n" + raise err + + if new_ymin >= new_ymax : + err = "\n[Stratus ERROR] ResizeAb : one of the values of dy1 or dy2 is incompatible with the size of the abutment box.\n" + raise err + + hurCell.setAbutmentBox ( Box ( new_xmin, new_ymin, new_xmax, new_ymax ) ) + + UpdateSession.close () + +############ +def DefInstanceAb ( instance, x1, y1, x2, y2 ) : + + cell = instance._hur_instance.getMasterCell() + + boite = cell.getAbutmentBox() + + if not ( boite.isEmpty() ) : + err = "\n[Stratus ERROR] DefInstanceAb : an abutment box already exists. Maybe you should use ResizeAb function.\n" + raise err + + if x1 % MYPITCH or y1 % MYSLICE or x2 % MYPITCH or y2 % MYSLICE : + err = "\nError in DefAb : Coordinates of an abutment Box in y must be multiple of the slice.\n" \ + + " : Coordinates of an abutment Box in x must be multiple of the pitch.\n" + raise err + + cell.setAbutmentBox ( Box ( DbU_lambda ( x1 ) + , DbU_lambda ( y1 ) + , DbU_lambda ( x2 ) + , DbU_lambda ( y2 ) + ) + ) + + +#################################### +## placement ## +#################################### +def placement ( st_inst, sym, x, y, plac = FIXED, cell = None, fonction = None ) : + global CELLS + from st_model import CELLS + + if not cell : cell = CELLS[-1] + + # Error : placement of a non existing instance + if not st_inst : raise "\n[Stratus ERROR] Placement : the instance doesn't exist.\n" + + # Error : st_inst is not an instance + if str ( st_inst.__class__ ) != "st_instance.Inst" : + err = "\n\n[Stratus ERROR] Placement : the first argument " + st_inst + " is not an instance.\n" + raise err + + # Hurricane instance + hur_inst = st_inst._hur_instance + + # Error : if the hurricane instance does not exist + if not hur_inst : + err = "\n[Stratus ERROR] Layout : The hurricane instance of " + st_inst._name + " has not been created.\n" \ + + "One has to use HurricanePlug before creating the layout.\n" + raise err + + # Error : if the instance is already placed + if hur_inst.getPlacementStatus() == PlacementStatusFIXED : + err = "\n[Stratus ERROR] Placement : the instance " + st_inst._name + " is already placed.\n" + raise err + + ##### Legalization of the symetry ##### + st_inst._sym = transformation ( sym ) + + ##### For PlaceBottom and PlaceLeft : need the size of the instance being placed ##### + if fonction == "Left" : + if vertical ( st_inst._sym ) : x -= width ( st_inst ) + elif horizontal ( st_inst._sym ) : x -= height ( st_inst ) + elif fonction == "Bottom" : + if vertical ( st_inst._sym ) : y -= height ( st_inst ) + elif horizontal ( st_inst._sym ) : y -= width ( st_inst ) + + ##### Initialisation for relative placement ##### + cell._insref = st_inst + + ##### Placement ##### + if st_inst._sym == OrientationID : + st_inst._x = x + st_inst._y = y + + elif st_inst._sym == OrientationMX : + abtemp = ab ( st_inst, cell ) + + st_inst._x = x + abtemp.getWidth () + st_inst._y = y + + elif st_inst._sym == OrientationMY : + abtemp = ab ( st_inst, cell ) + + st_inst._x = x + st_inst._y = y + abtemp.getHeight () + + elif st_inst._sym == OrientationR2 : + abtemp = ab ( st_inst, cell ) + + st_inst._x = x + abtemp.getWidth () + st_inst._y = y + abtemp.getHeight () + + elif st_inst._sym == OrientationR1 : + abtemp = ab ( st_inst, cell ) + + st_inst._x = x + abtemp.getHeight () + st_inst._y = y + + elif st_inst._sym == OrientationR3 : + abtemp = ab ( st_inst, cell ) + + st_inst._x = x + st_inst._y = y + abtemp.getWidth () + + elif st_inst._sym == OrientationYR : + st_inst._x = x + st_inst._y = y + + elif st_inst._sym == OrientationXR : + abtemp = ab ( st_inst, cell ) + + st_inst._x = x + abtemp.getHeight () + st_inst._y = y + abtemp.getWidth () + + else : + raise "\n[Stratus ERROR] Placement : wrong transformation.\n" + + # if the abutment box is not at 0 0 FIXME + if st_inst._sym == OrientationMY : + x = st_inst._x + hur_inst.getAbutmentBox().getXMin() + y = st_inst._y + hur_inst.getAbutmentBox().getYMin() + else : + x = st_inst._x - hur_inst.getAbutmentBox().getXMin() + y = st_inst._y - hur_inst.getAbutmentBox().getYMin() + + UpdateSession.open() + + hur_inst.setTransformation ( Transformation ( x, y, st_inst._sym ) ) + + if plac == PLACED : + cell._hur_cell.setAbutmentBox ( cell._hur_cell.getAbutmentBox ().merge ( hur_inst.getAbutmentBox () ) ) + hur_inst.setPlacementStatus ( PlacementStatusPLACED ) + elif plac == FIXED : + cell._hur_cell.setAbutmentBox ( cell._hur_cell.getAbutmentBox ().merge ( hur_inst.getAbutmentBox () ) ) + hur_inst.setPlacementStatus ( PlacementStatusFIXED ) + elif plac == UNPLACED : + hur_inst.setPlacementStatus ( PlacementStatusUNPLACED ) + else : + raise "\n[Stratus ERROR] Placement : wrong argument for type of placement.\n" + + st_inst._plac = plac + + UpdateSession.close() + + +## Two names for the symetry ## +def transformation ( symetry ) : + if symetry == NOSYM or symetry == OrientationID : transf = OrientationID + elif symetry == SYM_X or symetry == OrientationMX : transf = OrientationMX + elif symetry == SYM_Y or symetry == OrientationMY : transf = OrientationMY + elif symetry == SYMXY or symetry == OrientationR2 : transf = OrientationR2 + elif symetry == ROT_P or symetry == OrientationR1 : transf = OrientationR1 + elif symetry == ROT_M or symetry == OrientationR3 : transf = OrientationR3 + elif symetry == SY_RP or symetry == OrientationYR : transf = OrientationYR + elif symetry == SY_RM or symetry == OrientationXR : transf = OrientationXR + else : + err = "\n[Stratus ERROR] Placement :Illegal transformation.\n" + raise err + + return transf + +## How to get the abutment box ## +def ab ( ins, cell = None ) : + global CELLS + from st_model import CELLS + + if not cell : cell = CELLS[-1] + + return cell._hur_cell.getInstance ( ins._name ).getMasterCell ().getAbutmentBox () + +## the height of the abutment box ## +def height ( ins ) : + return ab ( ins ).getHeight () + +## the width of the abutment box ## +def width ( ins ) : + return ab ( ins ).getWidth () + +## Test of symetry ## +def vertical ( sym ) : + return sym == OrientationID or sym == OrientationMX or sym == OrientationMY or sym == OrientationR2 + +def horizontal ( sym ) : + return sym == OrientationR1 or sym == OrientationR3 or sym == OrientationYR or sym == OrientationXR + +def bas ( sym ) : + return sym == OrientationID or sym == OrientationMX or sym == OrientationR1 or sym == OrientationYR + +def haut ( sym ) : + return sym == OrientationR2 or sym == OrientationMY or sym == OrientationR3 or sym == OrientationXR + +def gauche ( sym ) : + return sym == OrientationID or sym == OrientationMY or sym == OrientationR3 or sym == OrientationYR + +def droite ( sym ) : + return sym == OrientationR2 or sym == OrientationMX or sym == OrientationR1 or sym == OrientationXR diff --git a/stratus1/src/stratus/st_ref.py b/stratus1/src/stratus/st_ref.py new file mode 100644 index 00000000..95ab704e --- /dev/null +++ b/stratus1/src/stratus/st_ref.py @@ -0,0 +1,242 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_ref.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from Hurricane import * + +from util_Place import * + +from ref import * + +import types + +########### +class XY : + def __init__ ( self, x, y ) : + self._x = x + self._y = y + +################################## +def GetRefXY ( pathname, refname ) : + global FRAMEWORK, CELLS + from st_model import FRAMEWORK, CELLS + + cell = CELLS[-1] + + # Check arguments type + if type ( pathname ) != types.StringType : + err = "\n[Stratus ERROR] GetRefXY : The instance's path must be put with a string.\n" + raise err + + if type ( refname ) != types.StringType : + err = "\n[Stratus ERROR] GetRefXY : The reference must be done with it's name : a string.\n" + raise err + + ( x, y ) = pyGetXY ( cell._hur_cell, pathname, refname ) + + return XY ( x, y ) + +############################ +def PlaceRef ( ref, name ) : + global FRAMEWORK, CELLS + from st_model import FRAMEWORK, CELLS + + cell = CELLS[-1] + + # Check arguments type + if ( str ( ref.__class__ ) != "st_ref.XY" ) : + err = "\n[Stratus ERROR] PlaceRef : Wrong argument, the coordinates of the reference must be put in a XY object.\n" + raise err + + if type ( name ) != types.StringType : + err = "\n[Stratus ERROR] PlaceRef : Argument layer must be a string.\n" + raise err + + pyPlaceRef ( cell._hur_cell, name, ref._x, ref._y ) + +################################################### +def PlaceContact ( net, layer, ref, width, height ) : + global FRAMEWORK + from st_model import FRAMEWORK + + # Check arguments type + if type ( layer ) != types.StringType : + err = "\n[Stratus ERROR] PlaceContact : Argument layer must be a string.\n" + raise err + myLayer = getDataBase().getTechnology().getLayer ( layer ) +# if not ( myLayer ) : +# err = "\n[Stratus ERROR] PlaceContact : Argument layer does not exist.\n" +# raise err + + if ( str ( ref.__class__ ) != "st_ref.XY" ) : + err = "\n[Stratus ERROR] PlaceContact : Wrong argument, the coordinates of the contact must be put in a XY object.\n" + raise err + + if ( net._arity > 1 ) : + err = "\n[Stratus ERROR] PlaceContact : Wrong argument, the net must be a 1 bit net.\n" + raise err + + if net._real_net : + indice = net._ind - net._real_net._ind + net = net._real_net + else : + indice = 0 + + pyPlaceContact ( net._hur_net[indice], myLayer, ref._x, ref._y, width, height ) + +################################################### +def PlacePin ( net, layer, direction, ref, width, height ) : + global FRAMEWORK + from st_model import FRAMEWORK + + # Check arguments type + if type ( layer ) != types.StringType : + err = "\n[Stratus ERROR] PlacePin : Argument layer must be a string.\n" + raise err + # No CALU permitted for Pin + calu = re.search ( "CALU", layer ) + if calu : + err = "\n[Stratus ERROR] PlacePin : Illegal layer, CALU not allowed.\n" + raise err + myLayer = getDataBase().getTechnology().getLayer ( layer ) +# if not ( myLayer ) : +# err = "\n[Stratus ERROR] PlacePin : Argument layer does not exist.\n" +# raise err + + if direction == UNDEFINED : direct = PinAccessDirectionUNDEFINED + elif direction == NORTH : direct = PinAccessDirectionNORTH + elif direction == SOUTH : direct = PinAccessDirectionSOUTH + elif direction == EAST : direct = PinAccessDirectionEAST + elif direction == WEST : direct = PinAccessDirectionWEST + else : + err = "\n[Stratus ERROR] PlacePin : Illegal pin access direction. The values are : UNDEFINED, NORTH, SOUTH, EAST, WEST.\n" + raise err + + if ( str ( ref.__class__ ) != "st_ref.XY" ) : + err = "\n[Stratus ERROR] PlacePin : Wrong argument, the coordinates of the pin must be put in a XY object.\n" + raise err + + if ( net._arity > 1 ) : + err = "\n[Stratus ERROR] PlacePin : Wrong argument, the net must be a 1 bit net.\n" + raise err + + if net._real_net : + indice = net._ind - net._real_net._ind + net = net._real_net + else : + indice = 0 + + if ( net._ext == False ) : + err = "\n[Stratus ERROR] PlacePin : Wrong argument, the net must be external.\n" + raise err + + pyPlacePin ( net._hur_net[indice], direct, PinPlacementStatusFIXED, myLayer, ref._x, ref._y, width, height ) + +################################################################# +def PlaceSegment ( net, layer, ref1, ref2, width ) : + global FRAMEWORK + from st_model import FRAMEWORK + + # Check arguments type + if type ( layer ) != types.StringType : + err = "\n[Stratus ERROR] PlaceSegment : Argument layer must be a string.\n" + raise err + + if ( str ( ref1.__class__ ) != "st_ref.XY" ) or ( str ( ref2.__class__ ) != "st_ref.XY" ) : + err = "\n[Stratus ERROR] PlaceSegment : Wrong argument, the coordinates of the segment must be put in XY objects.\n" + raise err + + if ( ref1._x != ref2._x ) and ( ref1._y != ref2._y ) : + err = "\n[Stratus ERROR] PlaceSegment : Segments are vertical or horizontal.\n" + raise err + + if ( net._arity > 1 ) : + err = "\n[Stratus ERROR] PlaceSegment : Wrong argument, the net must be a 1 bit net.\n" + raise err + + if net._real_net : + indice = net._ind - net._real_net._ind + net = net._real_net + else : + indice = 0 + + pyPlaceSegment ( net._hur_net[indice] + , getDataBase().getTechnology().getLayer ( layer ) + , ref1._x, ref1._y + , ref2._x, ref2._y + , width + ) + +################################################# +def CopyUpSegment ( pathname, netname, newnet ) : + global FRAMEWORK, CELLS + from st_model import FRAMEWORK, CELLS + + cell = CELLS[-1] + + # Check arguments type + if type ( pathname ) != types.StringType : + err = "\n[Stratus ERROR] CopyUpSegment : The instance's path must be put with a string.\n" + raise err + + if type ( netname ) != types.StringType : + err = "\n[Stratus ERROR] CopyUpSegment : The segment must be done with it's name : a string.\n" + raise err + + if ( newnet._arity > 1 ) : + err = "\n[Stratus ERROR] PlacePin : Wrong argument, the net must be a 1 bit net.\n" + raise err + + if newnet._real_net : + indice = newnet._ind - newnet._real_net._ind + newnet = newnet._real_net + else : + indice = 0 + + pyCopyUpSegment ( cell._hur_cell, pathname, netname, newnet._hur_net[indice] ) diff --git a/stratus1/src/stratus/st_shifter.py b/stratus1/src/stratus/st_shifter.py new file mode 100644 index 00000000..f5b3f384 --- /dev/null +++ b/stratus1/src/stratus/st_shifter.py @@ -0,0 +1,219 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Roselyne AVOT-CHOTIN - Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_shifter.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + + +def getConfig ( type ) : + def getValue ( pos ) : + if (type & 2**pos) != 0 : return True + else : return False + + config = { 'sticky' : None + , 'type' : {'log' : None, 'arith' : None, 'rot' : None, 'con' : None} + , 'dir' : {'left' : None, 'right' : None, 'con' : None} + } + + config['sticky'] = getValue(5) + config['type']['log'] = getValue(4) + config['type']['arith'] = getValue(3) + config['type']['rot'] = getValue(2) + config['dir']['left'] = getValue(1) + config['dir']['right'] = getValue(0) + + config['dir']['con'] = config['dir']['left'] and config['dir']['right'] + config['type']['con'] = ((config['type']['log'] and config['type']['arith']) + or (config['type']['log'] and config['type']['rot']) + or (config['type']['arith'] and config['type']['rot'])) + + if not (config['dir']['left'] or config['dir']['right']): + raise 'any of left or right directions are set' + if not (config['type']['log'] or config['type']['arith'] or config['type']['rot']) : + raise 'any of log or arith or rot types are set' + + return config + + +class Shifter ( Model ) : + + def __init__ ( self, name, param ) : + + Model.__init__ ( self, name, param ) + + self.nbit = param['nbit'] + + if self.nbit < 2: raise "\n[Stratus ERROR] Shift : input arity should be greater than 1.\n" + + self.config = getConfig(param['type']) + + self.cmd_width = log2 ( self.nbit ) + + def Interface ( self ) : + + self.cmd = SignalIn ( "cmd", self.cmd_width ) + self.i = SignalIn ( "i", self.nbit ) + self.s = SignalOut ( "s", self.nbit ) + + if self.config['sticky'] : self.sticky = SignalOut ( "sticky", 1 ) + if self.config['type']['con'] : self.type = SignalIn ( "typ", 3 ) + if self.config['dir']['con'] : self.dir = SignalIn ( "dir", 1 ) + + self.vdd = VddIn ( "vdd" ) + self.vss = VssIn ( "vss" ) + + def Netlist ( self ) : + + nbStages = self.cmd_width + + MuxOutput = {} + inj_lsb = {} + inj_msb = {} + mux_cmd = {} + + one = Signal ( "one", 1 ) + one <= One ( 1 ) + + zero = Signal ( "zero", 1 ) + zero <= Zero ( 1 ) + + # Normalizing the input signals names + MuxOutput[0] = self.i + + # signal giving the shift direction + if not self.config['dir']['con'] : + if self.config['dir']['left'] : dir = zero.Buffer() + else : dir = one.Buffer() + else : + dir = self.dir + + # signals giving the type of shift + if self.config['type']['con'] : + log = self.type[2].Buffer() + arith = self.type[1].Buffer() + rot = self.type[0].Buffer() + else : + if self.config['type']['log'] : log = one.Buffer() + else : log = zero.Buffer() + + if self.config['type']['arith'] : arith = one.Buffer() + else : arith = zero.Buffer() + + if self.config['type']['rot'] : rot = one.Buffer() + else : rot = zero.Buffer() + + # Building the control signals + c0 = Signal ( "c0", nbStages ) + c1 = Signal ( "c1", nbStages ) + + for stage in range ( nbStages ) : + c1[stage] <= ~self.cmd[stage] + c0[stage] <= c1[stage] | dir + + # Connecting the mux matrix + for stage in range ( nbStages ) : + valDec = 2**stage + + inj_lsb[stage] = Signal ( "inj_lsb%d" % stage, valDec ) + inj_msb[stage] = Signal ( "inj_msb%d" % stage, valDec ) + MuxOutput[stage+1] = Signal ( "mxout%d" % (stage+1), self.nbit ) + + if ( self.nbit-valDec-1 ) == 0 : MuxInput0 = MuxOutput[stage][0] + else : MuxInput0 = MuxOutput[stage][self.nbit-valDec-1:0] + + for i in range ( valDec ) : + inj_lsb[stage][i] <= (((MuxOutput[stage][i] & dir) | (MuxOutput[stage][self.nbit-valDec+i] & ~dir)) & rot) | (dir & ~rot) + + MuxInput0 = Cat ( MuxInput0, inj_lsb[stage] ) + MuxInput1 = MuxOutput[stage] + + # mettre zero, signe ou rot + for i in range ( valDec ) : + inj_msb[stage][i] <= (inj_lsb[stage][i] & rot) | (self.i[self.nbit-1] & arith) | (zero & log) + + if (self.nbit-1) == valDec : MuxInput2 = MuxOutput[stage][self.nbit-1] + else : MuxInput2 = MuxOutput[stage][self.nbit-1:valDec] + + MuxInput2 = Cat ( inj_msb[stage], MuxInput2 ) + mux_cmd[stage] = Cat ( c0[stage], c1[stage] ) + + MuxOutput[stage + 1] <= mux_cmd[stage].Mux ( { '0' : MuxInput0 + , '1' : MuxInput0 + , '2' : MuxInput2 + , '3' : MuxInput1 + } + ) + + # Normalizing the output signal names + self.s <= MuxOutput[nbStages] + + def GetModelName ( cls, param ) : + + modelName = "shifter" + + modelName += "_" + modelName += str(param['nbit']) + modelName += "bits" + + if param['type'] == 0x12 : modelName += "_logical_left" + elif param['type'] == 0xa : modelName += "_arith_left" + elif param['type'] == 0x6 : modelName += "_circular_left" + elif param['type'] == 0x11 : modelName += "_logical_right" + elif param['type'] == 0x9 : modelName += "_arith_right" + elif param['type'] == 0x5 : modelName += "_circular_right" + + return modelName + + GetModelName = classmethod ( GetModelName ) + + def GetParam ( cls ): + + return {'nbit' : 'integer', 'type' : 'integer'} + + GetParam = classmethod ( GetParam ) diff --git a/stratus1/src/stratus/st_slansky.py b/stratus1/src/stratus/st_slansky.py new file mode 100644 index 00000000..1d42a4df --- /dev/null +++ b/stratus1/src/stratus/st_slansky.py @@ -0,0 +1,409 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Roselyne AVOT-CHOTIN - Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./st_slansky.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from stratus import * + +class Sub ( Model ) : + + def __init__(self, name, param): + Model.__init__(self, name, param) + if 'nbit' in param: + self.nbit = param['nbit'] + self.nbit0 = self.nbit + self.nbit1 = self.nbit + else: + self.nbit0 = param['nbit0'] + self.nbit1 = param['nbit1'] + self.nbit = max(self.nbit0,self.nbit1) + + if 'signed' not in param : self._signed = True + else : self._signed = param['signed'] + + if 'extended' not in param : self._extended = False + else : self._extended = param['extended'] + + if (self.nbit < 2): raise "\n[Stratus ERROR] slansky : input arity should be greater than 1.\n" + + def Interface(self): + self.i0 = SignalIn("i0", self.nbit0) + self.i1 = SignalIn("i1", self.nbit1) + if self._extended : self.o = SignalOut("o", self.nbit+1) + else : self.o = SignalOut("o", self.nbit) + + self.vdd = VddIn("vdd") + self.vss = VssIn("vss") + + def Netlist(self): + # extand the inputs to have the same width + if (self.nbit0 < self.nbit) : + i0e = Signal("i0e", self.nbit) + if self._signed : i0e <= self.i0.Extend(self.nbit,'signed') + else : i0e <= self.i0.Extend(self.nbit,'zero') + else: + i0e = self.i0 + if (self.nbit1 < self.nbit) : + i1e = Signal("i1e", self.nbit) + if self._signed : i1e <= self.i1.Extend(self.nbit,'signed') + else : i1e <= self.i1.Extend(self.nbit,'zero') + else: + i1e = self.i1 + + Generate ( "Slansky", "slansky_cin_%d" % ( self.nbit ), param={'nbit':self.nbit,'cin':True, 'extended':self._extended} ) + Inst ( "slansky_cin_%d" % ( self.nbit ) + , map = { 'i0' : i0e + , 'i1' : ~i1e + , 'cin' : One(1) + , 'o' : self.o + , 'vdd' : self.vdd + , 'vss' : self.vss + } + ) + + def GetParam ( cls ): + + return {'nbit' : 'integer', 'nbit0' : 'integer', 'nbit1' : 'integer'} + + GetParam = classmethod ( GetParam ) + + +class Slansky ( Model ) : + + def __init__(self, name, param): + Model.__init__(self, name, param) + if 'nbit' in param: + self.nbit = param['nbit'] + self.nbit0 = self.nbit + self.nbit1 = self.nbit + else: + self.nbit0 = param['nbit0'] + self.nbit1 = param['nbit1'] + self.nbit = max(self.nbit0,self.nbit1) + + if 'signed' not in param : self._signed = True + else : self._signed = param['signed'] + + if 'extended' not in param : self._extended = False + else : self._extended = param['extended'] + + if 'cin' not in param : self._cin = False + else : self._cin = param['cin'] + + if (self.nbit < 2): raise "\n[Stratus ERROR] slansky : input arity should be greater than 1.\n" + + def Interface(self): + self.i0 = SignalIn("i0", self.nbit0) + self.i1 = SignalIn("i1", self.nbit1) + if self._cin : self.cin = SignalIn("cin", 1) + if self._extended : self.o = SignalOut("o", self.nbit+1) + else : self.o = SignalOut("o", self.nbit) + + self.vdd = VddIn("vdd") + self.vss = VssIn("vss") + + def Netlist(self): + # extand the inputs to have the same width + if (self.nbit0 < self.nbit) : + i0e = Signal("i0e", self.nbit) + if self._signed : i0e <= self.i0.Extend(self.nbit,'signed') + else : i0e <= self.i0.Extend(self.nbit,'zero') + else: + i0e = self.i0 + if (self.nbit1 < self.nbit) : + i1e = Signal("i1e", self.nbit) + if self._signed : i1e <= self.i1.Extend(self.nbit,'signed') + else : i1e <= self.i1.Extend(self.nbit,'zero') + else: + i1e = self.i1 + + # pigi preprocessing + [p,g] = pigi(i0e,i1e) + + # Slansky algorithm + [pp,gg] = pg_tree(p,g,'slansky') + + # postprocessing : + if self._cin : self.o[0] <= p[0] ^ self.cin + else : self.o[0] <= p[0].Buffer() + + for i in range(1,self.nbit): + if self._cin : self.o[i] <= p[i] ^ (gg[i-1] | (pp[i-1] & self.cin)) + else : self.o[i] <= p[i] ^ gg[i-1] + + if self._extended: + if self._signed: + ovft = Signal("ovft",1) + if self._cin: + ovft <= (gg[self.nbit-1] | (pp[self.nbit-1] & self.cin)) ^ (gg[self.nbit-2] | (pp[self.nbit-2] & self.cin)) + # pb inout asimut remplacement de o[nbit-1] par sa valeur + # self.o[self.nbit] <= (self.o[self.nbit-1] & ~ovf) | (cout & ovf) + self.o[self.nbit] <= ((p[self.nbit-1] ^ (gg[self.nbit-2] | (pp[self.nbit-2] & self.cin))) & ~ovft) | (gg[self.nbit-1] & ovft) + else: + ovft <= gg[self.nbit-1] ^ gg[self.nbit-2] + # pb inout asimut remplacement de o[nbit-1] par sa valeur + # self.o[self.nbit] <= (self.o[self.nbit-1] & ~ovf) | (cout & ovf) + self.o[self.nbit] <= ((p[self.nbit-1] ^ gg[self.nbit-2]) & ~ovft) | (gg[self.nbit-1] & ovft) + else: + if self._cin: + self.o[self.nbit] <= gg[self.nbit-1] | (pp[self.nbit-1] & self.cin) + else: + self.o[self.nbit] <= gg[self.nbit-1].Buffer() + + def GetModelName ( cls, param ) : + name = 'slansky' + + if 'nbit' in param: + name += '_%d' % (param['nbit']) + else: + if param['nbit0'] != param['nbit1'] : name += '_%dx%d' % (param['nbit0'], param['nbit1']) + else : name += '_%d' % (param['nbit0']) + + name += "bits" + + if ('cin' in param) and (param['cin']) : name += '_cin' + + return name + GetModelName = classmethod ( GetModelName ) + + def GetParam ( cls ): + + return {'nbit' : 'integer', 'nbit0' : 'integer', 'nbit1' : 'integer', 'cin' : 'boolean'} + + GetParam = classmethod ( GetParam ) + +#################################################################################################### +nb_pigi = 0 +nb_pg_tree = 0 + +def pigi(a,b): + global nb_pigi + nb_pigi += 1 + pi = Signal("pi%d_a" %nb_pigi,a._arity) + gi = Signal("gi%d_a" %nb_pigi,a._arity) + Generate ( "st_slansky.PiGiBus", "pigibus%d" % a._arity, param = {'nbit' : a._arity} ) + Inst("pigibus%d" % a._arity, + map = { + 'a' : a, + 'b' : b, + 'pi' : pi, + 'gi' : gi, + 'vdd' : a._st_cell._st_vdds[0], + 'vss' : a._st_cell._st_vsss[0] + }, + ) + return [pi,gi] + +class PiGiBus(Model): + def __init__(self, name, param): + Model.__init__(self, name, param) + self.nbit = param['nbit'] + if self.nbit < 1: + raise 'PiGiBus : input arity should be greater than 0' + + def Interface(self): + self.a = SignalIn("a",self.nbit) + self.b = SignalIn("b",self.nbit) + self.pi = SignalOut("pi",self.nbit) + self.gi = SignalOut("gi",self.nbit) + + self.vdd = VddIn("vdd") + self.vss = VssIn("vss") + + def Netlist(self): + for i in range (self.nbit): + Generate ( "st_slansky.PiGi", "pigi" ) + Inst("pigi", + map = { + 'a' : self.a[i], + 'b' : self.b[i], + 'pi' : self.pi[i], + 'gi' : self.gi[i], + 'vdd': self.vdd, + 'vss': self.vss + } + ) + + def GetParam ( cls ): + + return {'nbit' : 'integer'} + + GetParam = classmethod ( GetParam ) + + +class PiGi(Model): + def Interface(self): + self.a = SignalIn("a",1) + self.b = SignalIn("b",1) + self.pi = SignalOut("pi",1) + self.gi = SignalOut("gi",1) + + self.vdd = VddIn("vdd") + self.vss = VssIn("vss") + + def Netlist(self): + self.pi <= self.a ^ self.b + self.gi <= self.a & self.b + +######################## +def pg_tree(pi,gi,algo): + global nb_pg_tree + nb_pg_tree += 1 + p = Signal("p%d_a" %nb_pg_tree,pi._arity) + g = Signal("g%d_a" %nb_pg_tree,pi._arity) + Generate ( "st_slansky.PGTree", "pgtree%d%s" % ( pi._arity, algo ), param = {'nbit' : pi._arity, 'algo' : algo} ) + Inst("pgtree%d%s" % ( pi._arity, algo ), + map = { + 'pi' : pi, + 'gi' : gi, + 'p' : p, + 'g' : g, + 'vdd' : pi._st_cell._st_vdds[0], + 'vss' : pi._st_cell._st_vsss[0] + } + ) + return [p,g] + +class PGTree(Model): + + def __init__(self, name, param): + Model.__init__(self, name, param) + self.nbit = param['nbit'] + if self.nbit < 1: + raise 'input arity should be greater than 0' + self.algo = param['algo'] + if self.algo != 'slansky': + raise '%s algorithm is not yet implemented' %self.algo + + def Interface(self): + self.pi = SignalIn("pi",self.nbit) + self.gi = SignalIn("gi",self.nbit) + self.p = SignalOut("p",self.nbit) + self.g = SignalOut("g",self.nbit) + + self.vdd = VddIn("vdd") + self.vss = VssIn("vss") + + def Netlist(self): + nb_stages = log2(self.nbit) + matrix = prefixMatrix(self.algo,self.nbit) + p = [] + g = [] + p.append(self.pi) + g.append(self.gi) + # group propagation + Generate ( "st_slansky.PG", "pg" ) + for i in range(0, nb_stages): + p.append(Signal("p%d" %(i+1), self.nbit)) + g.append(Signal("g%d" %(i+1), self.nbit)) + for j in range(0, self.nbit): + if (j % 2**i) == 0: + k = j-1 + if matrix[i][j] == 1: + Inst("pg", + map = { + 'p1' : p[i][j], + 'g1' : g[i][j], + 'p2' : p[i][k], + 'g2' : g[i][k], + 'p' : p[i+1][j], + 'g' : g[i+1][j], + 'vdd' : self.vdd, + 'vss' : self.vss + } + ) + else: + p[i+1][j] <= p[i][j].Buffer() + g[i+1][j] <= g[i][j].Buffer() + self.p <= p[nb_stages].Buffer() + self.g <= g[nb_stages].Buffer() + + def GetParam ( cls ): + + return {'nbit' : 'integer'} + + GetParam = classmethod ( GetParam ) + + +class PG(Model): + def Interface(self): + self.p1 = SignalIn("p1",1) + self.g1 = SignalIn("g1",1) + self.p2 = SignalIn("p2",1) + self.g2 = SignalIn("g2",1) + self.p = SignalOut("p",1) + self.g = SignalOut("g",1) + + self.vdd = VddIn("vdd") + self.vss = VssIn("vss") + + def Netlist(self): + self.p <= self.p1 & self.p2 + self.g <= self.g1 | (self.g2 & self.p1) + +def prefixMatrix(algo,size): + if algo == 'slansky': + nb_stages = log2(size) + matrix = [] + for i in range(0, nb_stages): + matrix.append([]) + connection = True + j = -1 + while (j < size-1): + connection = not connection + k = -1 + while((k < 2**i-1) and (j < size-1)): + j = j + 1 + k = k + 1 + if connection : + matrix[i].append(1) + else: + matrix[i].append(0) + return matrix + else: + raise '%s algorithm is not yet implemented' %algo diff --git a/stratus1/src/stratus/stratus.py b/stratus1/src/stratus/stratus.py new file mode 100644 index 00000000..2955b979 --- /dev/null +++ b/stratus1/src/stratus/stratus.py @@ -0,0 +1,71 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./stratus.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +from st_model import * +from st_net import * +from st_instance import * +from st_placement import * +from st_placeAndRoute import * +from st_ref import * +from st_generate import * +from st_const import * +from st_cat import * +from st_param import * +from st_getrealmodel import GetWeightTime, GetWeightArea + +from util_Const import * +from util_Defs import * +from util_Misc import * +from util_Gen import * +from util_Shift import * +from util_uRom import * +from util import * + +from patterns import * diff --git a/stratus1/src/stratus/util.py b/stratus1/src/stratus/util.py new file mode 100644 index 00000000..206b6690 --- /dev/null +++ b/stratus1/src/stratus/util.py @@ -0,0 +1,61 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_Misc.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +import re + +def getModelName ( model, param ) : + modelName = model.lower() + modelName = re.sub ( "\.", "_", modelName ) + for key in param : + modelName += "_" + modelName += str(key).lower() + modelName += str(param[key]).lower() + + return modelName diff --git a/stratus1/src/stratus/util_Const.py b/stratus1/src/stratus/util_Const.py new file mode 100644 index 00000000..8ad527ad --- /dev/null +++ b/stratus1/src/stratus/util_Const.py @@ -0,0 +1,285 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_Const.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +import sys, types + +XLONG_SIZE = 8 + + +########## +## btol ## +########## +def btol ( aDigit ) : + global LV_const + + digit = 0 + + if aDigit == '0' : digit = 0 + elif aDigit == '1' : digit = 1 + else : + err = "\n[Stratus ERROR] : Invalid digit \'%c\' in boolean string \"%s\"\n" % ( aDigit, LV_const ) + raise err + + return digit + + +########## +## otol ## +########## +def otol ( aDigit ) : + global LV_const + + digit = -1 + + if aDigit >= '0' and aDigit <= '7' : digit = int ( aDigit ) + + if digit < 0 : + err = "\n[Stratus ERROR] : Invalid digit \'%c\' in octal string \"%s\".\n" % ( aDigit, LV_const ) + raise err + + return digit + + +########## +## xtol ## +########## +def xtol ( aDigit ) : + global LV_const + + digit = -1 + + if aDigit >= '0' and aDigit <= '9' : digit = int ( aDigit ) + elif aDigit == 'a' or aDigit == 'A' : digit = 10 + elif aDigit == 'b' or aDigit == 'B' : digit = 11 + elif aDigit == 'c' or aDigit == 'C' : digit = 12 + elif aDigit == 'd' or aDigit == 'D' : digit = 13 + elif aDigit == 'e' or aDigit == 'E' : digit = 14 + elif aDigit == 'f' or aDigit == 'F' : digit = 15 + + if digit < 0 : + err = "\n[Stratus ERROR] : Invalid digit \'%c\' in hexadecimal string \"%s\".\n" % ( aDigit, LV_const ) + raise err + + return digit + + +########## +## ltox ## +########## +def ltox ( aDigit ) : + digit = '\0' + + if aDigit >= 0 and aDigit <= 9 : digit = str ( aDigit ) + elif aDigit == 10 : digit = 'a' + elif aDigit == 11 : digit = 'b' + elif aDigit == 12 : digit = 'c' + elif aDigit == 13 : digit = 'd' + elif aDigit == 14 : digit = 'e' + elif aDigit == 15 : digit = 'f' + + if digit == '\0' : + err = "\n[Stratus ERROR] : Invalid number %d in hexadecimal conversion.\n" % aDigit + raise err + + return digit + + +########### +## newxl ## +########### +class newxl : + + def __init__ ( self ) : + self._size = 0L + self._l = [] + + for i in range ( XLONG_SIZE ) : self._l.append ( 0L ) + + + ########### + ## atoxl ## + ########### + def atoxl ( self, asConst ) : + global LV_const + + LV_const = asConst + + if type ( asConst ) != types.StringType : raise "\n[Stratus ERROR] : the constant must be described in a string.\n" + + base = 1 + offset = 2 + + if asConst[0] == '0' : + if asConst[1] == 'b' or asConst[1] == 'B' : base = 1 + elif asConst[1] == 'x' or asConst[1] == 'X' : base = 4 + elif asConst[1] == 'o' or asConst[1] == 'O' : base = 3 + else : + err = "\n[Stratus ERROR] : one has to specify the basis of the constant : 0b or 0x or 0o.\n" + raise err + else : + err = "\n[Stratus ERROR] : one has to specify the basis of the constant : 0b or 0x or 0o.\n" + raise err + + length = len ( asConst ) + + self._size = (length - offset) * base + + xl_size = self._size / 32 + if self._size % 32 : xl_size += 1 + + for i in range ( xl_size ) : + iRight = length - 1 - ( 32 / base ) * i + iLeft = length - ( 32 / base ) * ( i + 1 ) + + if iLeft < offset : iLeft = offset + + power = 1 + + while iRight >= iLeft : + if base == 1 : +# self._l[i] += btol ( asConst[iRight] ) << ( power - 1 ) + temp1 = power - 1 + temp2 = btol ( asConst[iRight] ) + while temp1 : + temp2 = temp2 * 2 + temp1 = temp1 - 1 + + self._l[i] += temp2 + + elif base == 3 : +# self._l[i] += otol ( asConst[iRight] ) << ( power - 1 ) + temp1 = power - 1 + temp2 = otol ( asConst[iRight] ) + while temp1 : + temp2 = temp2 * 2 + temp1 = temp1 - 1 + + self._l[i] += temp2 + + elif base == 4 : +# self._l[i] += xtol ( asConst[iRight] ) << ( power - 1 ) + temp1 = power - 1 + temp2 = xtol ( asConst[iRight] ) + while temp1 : + temp2 = temp2 * 2 + temp1 = temp1 - 1 + + self._l[i] += temp2 + + power += base + + iRight -= 1 + + + ############## + ## getxlbit ## + ############## + def getxlbit ( self, aBit ) : + i = aBit / 32 + +# mask = ( 1 << ( aBit % 32 ) ) + mask = 1 + temp = aBit % 32 + while temp : + mask = mask * 2 + temp = temp - 1 + + + if i >= XLONG_SIZE : + err = "\n[Stratus ERROR] : Requested bit", aBit, "is out of range\n" + raise err + + if self._l[i] & mask : return 1L + else : return 0L + + + ############### + ## getxlhexa ## + ############### + def getxlhexa ( self, aBit ) : + i = aBit / 32 + shift = aBit % 32 + + if i >= XLONG_SIZE : + err = "\n[Stratus ERROR] : Requested hexa %ld is out of range.\n" % aBit + raise err + + return ( ( self._l[i] ) >> shift ) & 15 + + + ############## + ## xltovhdl ## + ############## + def xltovhdl ( self ) : + pS = '' + + i = self._size + + if i % 4 : + pS = 'B\"' + + while i % 4 : + if self.getxlbit ( i - 1 ) : pS += '1' + else : pS += '0' + + i -= 1 + + if i >= 4 : + if pS != '' : pS += '\" & ' + + pS += 'X\"' + + i -= 4 + for j in range ( i, -1, -4 ) : + pS += ltox ( self.getxlhexa ( j ) ) + + pS += '\"' + + return pS diff --git a/stratus1/src/stratus/util_Defs.py b/stratus1/src/stratus/util_Defs.py new file mode 100644 index 00000000..dd35384f --- /dev/null +++ b/stratus1/src/stratus/util_Defs.py @@ -0,0 +1,122 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_Defs.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +from st_placement import Place, NOSYM, SYM_Y, FIXED +from st_ref import XY +from util_Gen import F_MSB_FIRST + +Y_SLICE = 50 + +# for DpgenAdder +F_ADDER_CIN = 0x00000001 +F_ADDER_SIGN = 0x00000002 +F_ADDER_OVER = 0x00000004 + + + +################ +## slice_to_y ## +################ +def slice_to_y ( s ) : + return s * Y_SLICE + + +################## +## slice_to_sym ## +################## +def slice_to_sym ( s ) : + if s % 2 : return SYM_Y + else : return NOSYM + + +################## +## slice_to_bit ## +################## +def slice_to_bit ( s, N, m ) : + if m : m = N - 1 - s + else : m = s + + return m + + +#################### +## dpgen_port_bit ## +#################### +def dpgen_port_bit ( n, flags, s ) : + return slice_to_bit ( s + , n + , flags & F_MSB_FIRST + ) + + + +################# +## dpgen_place ## +################# +def dpgen_place ( Ins, x, y, plac = FIXED ) : + sym = NOSYM + if ( y / 50 ) % 2 : sym = SYM_Y + + Place ( Ins, sym, XY ( x, y ), plac ) + + +################### +## VHDL_BUS_WIDE ## +################### +def VHDL_BUS_WIDE ( msb, lsb, n, flags ) : + + if flags & F_MSB_FIRST : temp = "to" + else : temp = "downto" + + bus = "(%ld %s %ld)" % ( dpgen_port_bit ( n, flags, msb ) + , temp + , dpgen_port_bit ( n, flags, lsb ) + ) + + return bus diff --git a/stratus1/src/stratus/util_Gen.py b/stratus1/src/stratus/util_Gen.py new file mode 100644 index 00000000..af1a47f0 --- /dev/null +++ b/stratus1/src/stratus/util_Gen.py @@ -0,0 +1,102 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_Gen.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +F_LSB_FIRST = 0x00000000 # flags macro +F_MSB_FIRST = 0x00000001 +F_BEHAV = 0x00000004 + + +DPGEN_INV = 1 +DPGEN_BUFF = 2 +DPGEN_NAND2 = 3 +DPGEN_NAND3 = 4 +DPGEN_NAND4 = 5 +DPGEN_AND2 = 6 +DPGEN_AND3 = 7 +DPGEN_AND4 = 8 +DPGEN_NOR2 = 9 +DPGEN_NOR3 = 10 +DPGEN_NOR4 = 11 +DPGEN_OR2 = 12 +DPGEN_OR3 = 13 +DPGEN_OR4 = 14 +DPGEN_XNOR2 = 15 +DPGEN_XOR2 = 16 +DPGEN_NMUX2 = 17 +DPGEN_MUX2 = 18 +DPGEN_NBUSE = 19 +DPGEN_BUSE = 20 +DPGEN_NAND2MASK = 21 +DPGEN_NOR2MASK = 22 +DPGEN_XNOR2MASK = 23 +DPGEN_ADSB2F = 24 +DPGEN_SHIFT = 25 +DPGEN_NUL = 26 +DPGEN_CONST = 27 +DPGEN_RF1 = 28 +DPGEN_RF1R0 = 29 +DPGEN_RF1D = 30 +DPGEN_RF1DR0 = 31 +DPGEN_FIFO = 32 +DPGEN_RF2 = 33 +DPGEN_RF2R0 = 34 +DPGEN_RF2D = 35 +DPGEN_RF2DR0 = 36 +DPGEN_RAM = 37 +DPGEN_ROM = 38 +DPGEN_ROMTS = 39 +DPGEN_DFF = 40 +DPGEN_DFFT = 41 +DPGEN_SFF = 42 +DPGEN_SFFT = 43 +DPGEN_ROM2 = 44 +DPGEN_ROM4 = 45 +DPGEN_SHROT = 46 +DPGEN_UNKNOWN = 47 diff --git a/stratus1/src/stratus/util_Misc.py b/stratus1/src/stratus/util_Misc.py new file mode 100644 index 00000000..a9dc8767 --- /dev/null +++ b/stratus1/src/stratus/util_Misc.py @@ -0,0 +1,98 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_Misc.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + + +########### +## ilog2 ## +########### +def ilog2 ( x ) : + i = 0 + while x : + i = i + 1 + x = x >> 1 + return i + +########### +## iexp2 ## +########### +def iexp2 ( x ) : + return ( 1 << x ) + +############### +## get_depth ## +############### +def get_depth ( x, depth ) : + mDepth = ilog2 ( x ) + + for i in range ( depth , mDepth + 1, 1 ) : + if x & ( 1 << i ) : return i + + return 0 + +########## +## log2 ## +########## +def log2 ( x ) : + import math + + if x <= 1 : return 0 + +# l = int(math.ceil(math.log(x-0.4999)/math.log(2))) +# if l >= 48 : raise "ERROR in log2." +# return l + + try: + l = int(math.ceil(math.log(x-0.4999)/math.log(2))) + if l>=48: raise OverflowError + # x is small enough : float rounding is accurate enough + return l + except OverflowError: + # x is too large for direct float handling + # with this method, no limit is known + return log2((x+0xffffffffL)/0x100000000L)+32 diff --git a/stratus1/src/stratus/util_Place.py b/stratus1/src/stratus/util_Place.py new file mode 100644 index 00000000..43421564 --- /dev/null +++ b/stratus1/src/stratus/util_Place.py @@ -0,0 +1,70 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_Place.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +NOSYM = 1000 +SYM_X = 1001 +SYM_Y = 1002 +SYMXY = 1003 +ROT_P = 1004 +ROT_M = 1005 +SY_RP = 1006 +SY_RM = 1007 + +UNPLACED = 1010 +PLACED = 1011 +FIXED = 1012 + +UNDEFINED = 1020 +NORTH = 1021 +SOUTH = 1022 +EAST = 1023 +WEST = 1024 + +MYPITCH = 5 +MYSLICE = 50 diff --git a/stratus1/src/stratus/util_Route.py b/stratus1/src/stratus/util_Route.py new file mode 100644 index 00000000..b8185c15 --- /dev/null +++ b/stratus1/src/stratus/util_Route.py @@ -0,0 +1,62 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_Route.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +from Hurricane import * + +# For the placement of the model, for the standard cells mask +POWER = 2 +OCCUPIED = 1 +FREE = 0 + +# For the placement of the pads +CARRE = 800 + +# information sur le placement des couronnes +RING_INTERVAL = DbU_lambda ( 3 ) +RING_WIDTH = DbU_lambda ( 12 ) diff --git a/stratus1/src/stratus/util_Shift.py b/stratus1/src/stratus/util_Shift.py new file mode 100644 index 00000000..f0e8f39a --- /dev/null +++ b/stratus1/src/stratus/util_Shift.py @@ -0,0 +1,67 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_Shift.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +################ +def ln2p ( n ) : + i = 0 + j = n & 1 + + if ( n ) : + i = -1 + while n > 0 : + j += ( n & 1 ) + i += 1 + n >>= 1 + + return i + ( j > 1 ) + +################################ +def SYM ( BitIndex, sym, mys ) : + if BitIndex & 1 : return mys + else : return sym diff --git a/stratus1/src/stratus/util_uRom.py b/stratus1/src/stratus/util_uRom.py new file mode 100644 index 00000000..6c16ae07 --- /dev/null +++ b/stratus1/src/stratus/util_uRom.py @@ -0,0 +1,111 @@ +#!/usr/bin/python + +# This file is part of the Coriolis Project. +# Copyright (C) Laboratoire LIP6 - Departement ASIM +# Universite Pierre et Marie Curie +# +# Main contributors : +# Christophe Alexandre +# Sophie Belloeil +# Hugo Clement +# Jean-Paul Chaput +# Damien Dupuis +# Christian Masson +# Marek Sroka +# +# The Coriolis Project is free software; you can redistribute it +# and/or modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# The Coriolis Project is distributed in the hope that it will be +# useful, but WITHOUT ANY WARRANTY; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with the Coriolis Project; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +# USA +# +# License-Tag +# Authors-Tag +# =================================================================== +# +# x-----------------------------------------------------------------x +# | | +# | C O R I O L I S | +# | S t r a t u s - Netlists/Layouts Description | +# | | +# | Author : Sophie BELLOEIL | +# | E-mail : Sophie.Belloeil@asim.lip6.fr | +# | =============================================================== | +# | Py Module : "./util_uRom.py" | +# | *************************************************************** | +# | U p d a t e s | +# | | +# x-----------------------------------------------------------------x + + +from util_Gen import * + + +## Local constants ## +##################### +ERROR_INDEX = 4096 + +CELLS_ROM2 = 5 +CELLS_ROM4 = 17 + +SIZE_SNAME = 1024 + +## Local Variable ## +#################### +global LV_tsLeafCell + +LV_tsLeafCell = ["dp_rom2_buf", "zero_x0", "buf_x4", "inv_x4", "one_x0", "dp_rom4_buf", "zero_x0", "a2_x4", "a2_x4", "buf_x4", "a2_x4", "buf_x4", "dp_rom4_xr2_x4", "o2_x4", "a2_x4", "dp_rom4_nxr2_x4", "buf_x4", "o2_x4", "buf_x4", "o2_x4", "o2_x4", "one_x0"] + + +## Functions Definitions ## +########################### + +##################################################################################### +def get_index_Cell ( aiSlice, LV_Function, LV_xl0, LV_xl1, LV_xl2 = 0, LV_xl3 = 0 ) : + + index = ERROR_INDEX + + if LV_Function == DPGEN_ROM2 : + index = ( LV_xl1.getxlbit ( aiSlice ) << 1 ) + index += LV_xl0.getxlbit ( aiSlice ) + + elif LV_Function == DPGEN_ROM4 : + index = ( LV_xl3.getxlbit ( aiSlice ) << 3 ) + index += ( LV_xl2.getxlbit ( aiSlice ) << 2 ) + index += ( LV_xl1.getxlbit ( aiSlice ) << 1 ) + index += LV_xl0.getxlbit ( aiSlice ) + + return index + +################################################################### +def get_model_Cell ( aiSlice, LV_Function, aiCell, LV_iLeafCell ) : + global LV_tsLeafCell + + index = ERROR_INDEX + + if LV_Function in ( DPGEN_ROM4, DPGEN_ROM2 ) : index = LV_iLeafCell + 1 + aiCell + + if index >= ERROR_INDEX : return "bug_leaf" + + return LV_tsLeafCell[index] + +###################################### +def get_model_Buffer ( LV_Function, LV_iLeafCell ) : + global LV_tsLeafCell + + index = ERROR_INDEX + + if LV_Function in ( DPGEN_ROM4, DPGEN_ROM2 ) : index = LV_iLeafCell + + if index == ERROR_INDEX : return "bug_buff" + + return LV_tsLeafCell[index]