From ec3c22547acf2f57fb17b9cd352ea34fe6051334 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Mon, 5 Apr 2021 23:53:44 +0200 Subject: [PATCH] Bug fixes in the VST/VHDL driver coupled with BlifParser. * Change: In Hurricane::NetAlias, store additional data in NetAliasName, the external status of the former Net. When a Net::merge() is performed, we must keep track of whether the merged (destroyed) one was external and keep that information. Add NetAliasHook::isExternal() & NetAliasHook::setExternal() virtual methods. * Change: In Net::getNet() add a new optional argument to allow the search of the net name in *internal* aliases. Otherwise only the aliases tagged as *external* will be searched. It was a bug that, when looking for a Plug master net by name we got an homonymous internal net. In that case we must only look for net that are (or where) part of the interface. * New: In Vhdl::VectorSignal, when a vector contains only one bit, unvectorize it, like when it is non-contiguous (we use the isCountiguous() method to carry that information). * New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added a flag UniquifyUpperCase to uniquify the names in uppercases. In case of a clash with the same name in lowercase. Prepend 'u' before all previously uppercased letter. For example 'VexRiscV' becomes 'uvexuriscuv' (urgh!). The Catalog flags is exported to Python for use by the blif2vst script. * Change: In BlifParser, Model::newOne() and Model::newZero(), return a new gate each time it is called instead of making just one for each Model. This way, if two outside nets are connected to one or zero they do not get merged (should work, but will be less clear). * Bug: In BlifParser, Model::connectSubckts(), when looking for the master net in the instances models (by name), limit the search to the *external* aliases names. * Change: In NamingScheme::vlogTovhdl(), reactivate the removal of two consecutive '_'. * Change: In cumulus/bin/blif2vst.py, prefix the master cells (i.e. components) with 'cmpt_' to avoid clash names with signals in VHDL. --- crlcore/src/ccore/alliance/vst/VhdlEntity.cpp | 11 +++- crlcore/src/ccore/alliance/vst/VhdlSignal.cpp | 7 ++- crlcore/src/ccore/alliance/vst/VstDriver.cpp | 7 ++- crlcore/src/ccore/blif/BlifParser.cpp | 38 ++++++------ crlcore/src/ccore/crlcore/Catalog.h | 34 +++++------ crlcore/src/ccore/crlcore/ToolBox.h | 27 ++++++--- crlcore/src/ccore/crlcore/VhdlBit.h | 7 +-- crlcore/src/ccore/crlcore/VhdlEntity.h | 23 ++++---- crlcore/src/ccore/crlcore/VhdlSignal.h | 9 ++- crlcore/src/ccore/toolbox/NamingScheme.cpp | 4 +- crlcore/src/pyCRL/PyCatalogState.cpp | 25 ++++---- cumulus/src/plugins/rsave.py | 2 + cumulus/src/tools/blif2vst.py | 59 ++++++++++--------- cumulus/src/tools/yosys.py | 1 + hurricane/src/hurricane/Cell.cpp | 9 ++- hurricane/src/hurricane/Net.cpp | 33 ++++++++--- hurricane/src/hurricane/NetAlias.cpp | 26 ++++---- hurricane/src/hurricane/hurricane/Cell.h | 2 +- hurricane/src/hurricane/hurricane/Net.h | 27 +++++---- hurricane/src/hurricane/hurricane/NetAlias.h | 9 ++- 20 files changed, 208 insertions(+), 152 deletions(-) diff --git a/crlcore/src/ccore/alliance/vst/VhdlEntity.cpp b/crlcore/src/ccore/alliance/vst/VhdlEntity.cpp index 068af2c8..c949e50e 100644 --- a/crlcore/src/ccore/alliance/vst/VhdlEntity.cpp +++ b/crlcore/src/ccore/alliance/vst/VhdlEntity.cpp @@ -105,7 +105,8 @@ namespace Vhdl { , _globals() , _flags (flags) { - if (flags & VstNoLowerCase) _ns.setNoLowerCase( true ); + if (flags & VstNoLowerCase) _ns.setNoLowerCase( true ); + if (flags & VstUniquifyUpperCase) _ns.setUniquifyUpperCase( true ); if (not _offset) { //_offset = offsetof(EntityProperty,_entity); _offset = (ptrdiff_t)this - (ptrdiff_t)property; @@ -331,8 +332,12 @@ namespace Vhdl { out << "-- \n"; if (_flags & OptionMask) { out << "-- Genarated with options:\n"; - if (_flags & VstUseConcat) out << "-- * VstUseConcat: Use concat (&) in port map.\n"; - if (_flags & VstNoLowerCase) out << "-- * VstNoLowerCase: Identifiers are *not* put in lowercase.\n"; + if (_flags & VstUseConcat) out << "-- * VstUseConcat: Use concat (&) in port map.\n"; + if (_flags & VstNoLowerCase) out << "-- * VstNoLowerCase: Identifiers are *not* put in lowercase.\n"; + if (_flags & VstUniquifyUpperCase) { + out << "-- * VstUniquifyUpperCase: Upper case identifiers are uniquified.\n"; + out << "-- (one 'u' before each lowered letter)\n"; + } out << "-- \n"; } if (isIeeeMode()) { diff --git a/crlcore/src/ccore/alliance/vst/VhdlSignal.cpp b/crlcore/src/ccore/alliance/vst/VhdlSignal.cpp index 2a30fad5..0729e379 100644 --- a/crlcore/src/ccore/alliance/vst/VhdlSignal.cpp +++ b/crlcore/src/ccore/alliance/vst/VhdlSignal.cpp @@ -111,6 +111,7 @@ namespace Vhdl { bool ScalarSignal::isVector () const { return false; } bool ScalarSignal::isExternal () const { return _bit->isExternal(); } bool ScalarSignal::isContiguous () const { return false; } + size_t ScalarSignal::getSize () const { return 1; } const Bit* ScalarSignal::getBit () const { return _bit; } const Bit* ScalarSignal::getBit ( size_t ) const { return _bit; } const Net* ScalarSignal::getNet () const { return _bit->getNet(); } @@ -158,6 +159,7 @@ namespace Vhdl { bool VectorSignal::isScalar () const { return false; } bool VectorSignal::isVector () const { return true; } + size_t VectorSignal::getSize () const { return _bits.size(); } bool VectorSignal::isExternal () const { return (*_bits. begin())->isExternal(); } size_t VectorSignal::getMin () const { return (*_bits.rbegin())->getIndex(); } size_t VectorSignal::getMax () const { return (*_bits. begin())->getIndex(); } @@ -194,13 +196,13 @@ namespace Vhdl { bool VectorSignal::isContiguous () const { + if (_bits.size() < 2) return false; + auto inet1 = _bits.rbegin(); auto inet2 = inet1; - for ( ++inet1; inet1!=_bits.rend() ; ++inet1, ++inet2 ) { if ((*inet1)->getIndex() != (*inet2)->getIndex()+1) return false; } - return true; } @@ -211,7 +213,6 @@ namespace Vhdl { string range = "(" + getString(getMax()) + " downto " + getString(getMin()) + ")"; _toVhdlPort( out, width, flags, getName(), range, getDirection() ); } else { - bool first = true; for ( auto bit : _bits ) { string name = getName() + "_" + getString(bit->getIndex()); diff --git a/crlcore/src/ccore/alliance/vst/VstDriver.cpp b/crlcore/src/ccore/alliance/vst/VstDriver.cpp index 5fe4e4a9..6c5bde2d 100644 --- a/crlcore/src/ccore/alliance/vst/VstDriver.cpp +++ b/crlcore/src/ccore/alliance/vst/VstDriver.cpp @@ -40,9 +40,10 @@ namespace CRL { void vstDriver ( const string cellPath, Cell *cell, unsigned int& saveState ) { unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */; - if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat; - if (saveState & Catalog::State::VstNoLowerCase) entityFlags |= Vhdl::Entity::VstNoLowerCase; - if (saveState & Catalog::State::VstNoLinkage ) entityFlags |= Vhdl::Entity::VstNoLinkage; + if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat; + if (saveState & Catalog::State::VstNoLowerCase ) entityFlags |= Vhdl::Entity::VstNoLowerCase; + if (saveState & Catalog::State::VstUniquifyUpperCase) entityFlags |= Vhdl::Entity::VstUniquifyUpperCase; + if (saveState & Catalog::State::VstNoLinkage ) entityFlags |= Vhdl::Entity::VstNoLinkage; //NamingScheme::toVhdl( cell, NamingScheme::FromVerilog ); Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags ); diff --git a/crlcore/src/ccore/blif/BlifParser.cpp b/crlcore/src/ccore/blif/BlifParser.cpp index a3489863..8bce7300 100644 --- a/crlcore/src/ccore/blif/BlifParser.cpp +++ b/crlcore/src/ccore/blif/BlifParser.cpp @@ -515,14 +515,11 @@ namespace { Net* Model::newOne () { if (not _masterNetOne) return NULL; - if (_oneInstance) return _oneInstance->getPlug( _masterNetOne )->getNet(); - + // if (_oneInstance) return _oneInstance->getPlug( _masterNetOne )->getNet(); ostringstream name; name << "one_" << _supplyCount++; _oneInstance = Instance::create( _cell, name.str(), _oneCell ); - Net* one = Net::create( _cell, name.str() ); _oneInstance->getPlug( _masterNetOne )->setNet( one ); - return one; } @@ -530,14 +527,11 @@ namespace { Net* Model::newZero () { if (not _masterNetZero) return NULL; - if (_zeroInstance) return _zeroInstance->getPlug( _masterNetZero )->getNet(); - + // if (_zeroInstance) return _zeroInstance->getPlug( _masterNetZero )->getNet(); ostringstream name; name << "zero_" << _supplyCount++; _zeroInstance = Instance::create( _cell, name.str(), _zeroCell ); - Net* zero = Net::create( _cell, name.str() ); _zeroInstance->getPlug( _masterNetZero )->setNet( zero ); - return zero; } @@ -553,8 +547,8 @@ namespace { net->setDirection( (Net::Direction::Code)direction ); if (isClock) net->setType( Net::Type::CLOCK ); - // if (_cell->getName() == "ALU_dec19") - // cerr << "ALU_dec19 net create:" << direction << " " << net << endl; + // if (_cell->getName() == "alu_div0") + // cerr << "alu_div0 net create:" << direction << " " << net << endl; } else { net->addAlias( name ); if (isExternal) net->setExternal( true ); @@ -563,8 +557,8 @@ namespace { net->setDirection( (Net::Direction::Code)direction ); if (isClock) net->setType( Net::Type::CLOCK ); - // if (_cell->getName() == "ALU_dec19") - // cerr << "ALU_dec19 net merge:" << direction << " " << net << endl; + // if (_cell->getName() == "alu_div0") + // cerr << "alu_div0 net merge:" << direction << " " << net << endl; } return net; } @@ -607,13 +601,16 @@ namespace { if (not message.str().empty()) cerr << Warning( message.str() ) << endl; return net2; } - if ( (not net1->isExternal() and net2->isExternal()) or ( net1->isExternal() and net2->isExternal() and (net1->getId() > net2->getId()) ) ) { std::swap( net1 , net2 ); std::swap( name1, name2 ); } + + // if (_cell->getName() == "alu_div0") + // cerr << "alu_div0 alias net merge:" << net2 << " -> " << net1 << endl; + net1->merge( net2 ); return net1; } @@ -625,6 +622,9 @@ namespace { if (not net1) { net1 = Net::create( _cell, name1 ); net1->setExternal ( false ); + + // if (_cell->getName() == "alu_div0") + // cerr << "alu_div0 alias net create:" << net1 << endl; } net1->addAlias( name2 ); @@ -683,7 +683,7 @@ namespace { // << "external: <" << netName << ">." // << endl; Net* net = _cell->getNet( netName ); - Net* masterNet = instance->getMasterCell()->getNet(masterNetName); + Net* masterNet = instance->getMasterCell()->getNet(masterNetName,false); if(not masterNet) { Name vlogMasterNetName = NamingScheme::vlogToVhdl( masterNetName, NamingScheme::NoLowerCase ); masterNet = instance->getMasterCell()->getNet(vlogMasterNetName); @@ -721,13 +721,15 @@ namespace { plugNet->addAlias( netName ); } else if (plugNet != net){ // Plus already connected to another net - if (not plugNet->isExternal()) net->merge( plugNet ); + if (not plugNet->isExternal()) { + net->merge( plugNet ); + } else plugNet->merge( net ); } - if (subckt->getModel()->getCell()->getName() == "sm0") { - cerr << "sm0 plug:" << plug->getMasterNet()->getName() << " => net:" << net->getName() << endl; - } + // if (subckt->getModel()->getCell()->getName() == "sm0") { + // cerr << "sm0 plug:" << plug->getMasterNet()->getName() << " => net:" << net->getName() << endl; + // } if (plugNet->isSupply() and not plug->getMasterNet()->isSupply()) { ostringstream message; diff --git a/crlcore/src/ccore/crlcore/Catalog.h b/crlcore/src/ccore/crlcore/Catalog.h index 9239d21f..5d2d8ce1 100644 --- a/crlcore/src/ccore/crlcore/Catalog.h +++ b/crlcore/src/ccore/crlcore/Catalog.h @@ -14,9 +14,7 @@ // +-----------------------------------------------------------------+ -#ifndef CRL_CATALOG_H -#define CRL_CATALOG_H - +#pragma once #include #include #include "hurricane/Name.h" @@ -77,19 +75,20 @@ namespace CRL { class State { public: // Flags Constants. - enum Flags { TerminalNetlist = 1 << 0 - , Feed = 1 << 1 - , Pad = 1 << 2 - , GDS = 1 << 3 - , Delete = 1 << 4 - , Logical = 1 << 5 - , Physical = 1 << 6 - , InMemory = 1 << 7 - , Foreign = 1 << 8 - , VstUseConcat = 1 << 9 - , VstNoLowerCase = 1 << 10 - , VstNoLinkage = 1 << 11 - , Views = Physical|Logical + enum Flags { TerminalNetlist = 1 << 0 + , Feed = 1 << 1 + , Pad = 1 << 2 + , GDS = 1 << 3 + , Delete = 1 << 4 + , Logical = 1 << 5 + , Physical = 1 << 6 + , InMemory = 1 << 7 + , Foreign = 1 << 8 + , VstUseConcat = 1 << 9 + , VstNoLowerCase = 1 << 10 + , VstUniquifyUpperCase = 1 << 11 + , VstNoLinkage = 1 << 12 + , Views = Physical|Logical }; // Constructors. inline State (); @@ -436,6 +435,3 @@ inline std::string getPrint ( const CRL::Catalog &CATAL ) { return CATAL._getPr INSPECTOR_P_SUPPORT(CRL::Catalog); INSPECTOR_P_SUPPORT(CRL::Catalog::State); - - -#endif // CRL_CATALOG_H diff --git a/crlcore/src/ccore/crlcore/ToolBox.h b/crlcore/src/ccore/crlcore/ToolBox.h index acde63f6..70bcbaf1 100644 --- a/crlcore/src/ccore/crlcore/ToolBox.h +++ b/crlcore/src/ccore/crlcore/ToolBox.h @@ -65,19 +65,21 @@ namespace CRL { class NamingScheme { public: - enum Flag { NoFlags = 0x0000 - , Recursive = 0x0001 - , FromVerilog = 0x0002 - , NoLowerCase = 0x0004 + enum Flag { NoFlags = 0x0000 + , Recursive = 0x0001 + , FromVerilog = 0x0002 + , NoLowerCase = 0x0004 + , UniquifyUpperCase = 0x0008 }; public: typedef std::function< Name(const Name&,uint32_t) > converter_t; public: - static Name vlogToVhdl ( const Name& vlogName, uint32_t flags ); - static void toVhdl ( Cell* topCell, uint32_t flags ); - NamingScheme ( uint32_t flags ); - inline void setNoLowerCase ( bool state ); - Name convert ( const Name& ) const; + static Name vlogToVhdl ( const Name& vlogName, uint32_t flags ); + static void toVhdl ( Cell* topCell, uint32_t flags ); + NamingScheme ( uint32_t flags ); + inline void setNoLowerCase ( bool state ); + inline void setUniquifyUpperCase ( bool state ); + Name convert ( const Name& ) const; private: uint32_t _flags; converter_t _converter; @@ -91,6 +93,13 @@ namespace CRL { } + inline void NamingScheme::setUniquifyUpperCase ( bool state ) + { + if (state) _flags |= UniquifyUpperCase; + else _flags &= ~UniquifyUpperCase; + } + + // ------------------------------------------------------------------- // Class : "CRL::SubNetNames". diff --git a/crlcore/src/ccore/crlcore/VhdlBit.h b/crlcore/src/ccore/crlcore/VhdlBit.h index 2a272020..8332d107 100644 --- a/crlcore/src/ccore/crlcore/VhdlBit.h +++ b/crlcore/src/ccore/crlcore/VhdlBit.h @@ -14,9 +14,7 @@ // +-----------------------------------------------------------------+ -#ifndef VHDL_BIT_H -#define VHDL_BIT_H - +#pragma once #include #include #include "hurricane/Name.h" @@ -159,6 +157,3 @@ namespace Vhdl { INSPECTOR_P_SUPPORT(Vhdl::Bit); - - -#endif // VHDL_BIT_H diff --git a/crlcore/src/ccore/crlcore/VhdlEntity.h b/crlcore/src/ccore/crlcore/VhdlEntity.h index 96875be2..fc97a21f 100644 --- a/crlcore/src/ccore/crlcore/VhdlEntity.h +++ b/crlcore/src/ccore/crlcore/VhdlEntity.h @@ -58,18 +58,19 @@ namespace Vhdl { class Entity { public: - enum Flag { NoFlags = 0x0000 - , EntityMode = 0x0001 - , IeeeMode = 0x0002 - , ComponentMode = 0x0004 - , AsPortSignal = 0x0008 - , AsInnerSignal = 0x0010 - , VstUseConcat = 0x0020 - , VstNoLowerCase = 0x0040 - , VstNoLinkage = 0x0080 - , OptionMask = VstUseConcat|VstNoLowerCase|VstNoLinkage + enum Flag { NoFlags = 0x0000 + , EntityMode = 0x0001 + , IeeeMode = 0x0002 + , ComponentMode = 0x0004 + , AsPortSignal = 0x0008 + , AsInnerSignal = 0x0010 + , VstUseConcat = 0x0020 + , VstNoLowerCase = 0x0040 + , VstUniquifyUpperCase = 0x0080 + , VstNoLinkage = 0x0100 + , OptionMask = VstUseConcat|VstNoLowerCase|VstUniquifyUpperCase|VstNoLinkage }; - const unsigned int ModeMask = VstUseConcat|VstNoLowerCase|VstNoLinkage; + const unsigned int ModeMask = VstUseConcat|VstNoLowerCase|VstUniquifyUpperCase|VstNoLinkage; public: static std::vector& getAllEntities (); diff --git a/crlcore/src/ccore/crlcore/VhdlSignal.h b/crlcore/src/ccore/crlcore/VhdlSignal.h index b78ef112..2dbc7e9d 100644 --- a/crlcore/src/ccore/crlcore/VhdlSignal.h +++ b/crlcore/src/ccore/crlcore/VhdlSignal.h @@ -14,9 +14,7 @@ // +-----------------------------------------------------------------+ -#ifndef VHDL_SIGNAL_H -#define VHDL_SIGNAL_H - +#pragma once #include #include "hurricane/Net.h" #include "crlcore/VhdlBit.h" @@ -40,6 +38,7 @@ namespace Vhdl { virtual bool isVector () const = 0; virtual bool isExternal () const = 0; virtual bool isContiguous () const = 0; + virtual size_t getSize () const = 0; inline std::string getName () const; virtual const Bit* getBit () const = 0; virtual const Bit* getBit ( size_t ) const = 0; @@ -80,6 +79,7 @@ namespace Vhdl { virtual bool isVector () const; virtual bool isExternal () const; virtual bool isContiguous () const; + virtual size_t getSize () const; virtual const Bit* getBit () const; virtual const Bit* getBit ( size_t ) const; virtual const Net* getNet () const; @@ -106,6 +106,7 @@ namespace Vhdl { virtual bool isVector () const; virtual bool isExternal () const; virtual bool isContiguous () const; + virtual size_t getSize () const; virtual const Bit* getBit () const; virtual const Bit* getBit ( size_t ) const; virtual const Net* getNet () const; @@ -135,5 +136,3 @@ namespace Vhdl { INSPECTOR_P_SUPPORT(Vhdl::Signal); INSPECTOR_P_SUPPORT(Vhdl::ScalarSignal); INSPECTOR_P_SUPPORT(Vhdl::VectorSignal); - -#endif // VHDL_SIGNAL_H diff --git a/crlcore/src/ccore/toolbox/NamingScheme.cpp b/crlcore/src/ccore/toolbox/NamingScheme.cpp index 0d276494..e547cdf9 100644 --- a/crlcore/src/ccore/toolbox/NamingScheme.cpp +++ b/crlcore/src/ccore/toolbox/NamingScheme.cpp @@ -43,6 +43,8 @@ namespace CRL { if (vlogName[i] == ')') { posRightPar=i; } if (vlogName[i] == ']') { posRightPar=i; } loweredName.push_back( tolower(vlogName[i]) ); + if ( (flags & UniquifyUpperCase) and (vlogName[i] != tolower(vlogName[i])) ) + loweredName.push_back( 'u' ); } char leftPar = (parCount > 1) ? '_' : '('; char rightPar = (parCount > 1) ? '_' : ')'; @@ -84,7 +86,7 @@ namespace CRL { if (translated == '_') { if (vhdlName.empty() ) continue; if (i == refName.size()-1) break; - //if (vhdlName.back() == '_') continue; + if (vhdlName.back() == '_') continue; } vhdlName += translated; diff --git a/crlcore/src/pyCRL/PyCatalogState.cpp b/crlcore/src/pyCRL/PyCatalogState.cpp index 10c2f2dc..4565bb4c 100644 --- a/crlcore/src/pyCRL/PyCatalogState.cpp +++ b/crlcore/src/pyCRL/PyCatalogState.cpp @@ -137,18 +137,19 @@ extern "C" { { PyObject* constant; - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::TerminalNetlist ,"TerminalNetlist"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Feed ,"Feed"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::GDS ,"GDS"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Delete ,"Delete"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Logical ,"Logical"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Physical ,"Physical"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::InMemory ,"InMemory"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Foreign ,"Foreign"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUseConcat ,"VstUseConcat"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLowerCase ,"VstNoLowerCase"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLinkage ,"VstNoLinkage"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::TerminalNetlist ,"TerminalNetlist"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Feed ,"Feed"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::GDS ,"GDS"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Delete ,"Delete"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Logical ,"Logical"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Physical ,"Physical"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::InMemory ,"InMemory"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Foreign ,"Foreign"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUseConcat ,"VstUseConcat"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLowerCase ,"VstNoLowerCase"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUniquifyUpperCase,"VstUniquifyUpperCase"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLinkage ,"VstNoLinkage"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views"); } diff --git a/cumulus/src/plugins/rsave.py b/cumulus/src/plugins/rsave.py index 3acf1cef..c69fdcdb 100644 --- a/cumulus/src/plugins/rsave.py +++ b/cumulus/src/plugins/rsave.py @@ -51,6 +51,8 @@ def rsave ( cell, views=CRL.Catalog.State.Physical, depth=0 ): sviews += ' uses &' if views & CRL.Catalog.State.VstNoLowerCase: if sviews: sviews += ', no lowercase' + if views & CRL.Catalog.State.VstUniquifyUpperCase: + if sviews: sviews += ', uniquify uppercase' if views & CRL.Catalog.State.VstNoLinkage: if sviews: sviews += ', no linkage' sviews += '' diff --git a/cumulus/src/tools/blif2vst.py b/cumulus/src/tools/blif2vst.py index 73c1cb72..5de547b9 100755 --- a/cumulus/src/tools/blif2vst.py +++ b/cumulus/src/tools/blif2vst.py @@ -1,10 +1,11 @@ #!/usr/bin/env python +from __future__ import print_function +import sys +import traceback +import os.path +import optparse try: - import sys - import traceback - import os.path - import optparse import helpers from helpers import showPythonTrace from helpers.io import ErrorMessage, catch @@ -24,34 +25,37 @@ except Exception, e: framework = CRL.AllianceFramework.get() +def renameNMigen( occurrence ): + masterCell = occurrence.getEntity().getMasterCell() + origName = masterCell.getName() + replName = origName.replace( '$$', '_unm' ) + if not masterCell.isTerminalNetlist() and not replName.startswith('cmpt_'): + replName = 'cmpt_' + replName + #for letter in 'ABCDEFGHIJKLMNOPQRSTUVWXYZ': + # replName = replName.replace(letter, '{}u'.format(letter)) + if origName != replName: + print( ' - "{}" => "{}"'.format(origName,replName) ) + masterCell.setName( replName ) + + def renameNMigenUniquify ( topCell ): for occurrence in topCell.getTerminalNetlistInstanceOccurrences(): - masterCell = occurrence.getEntity().getMasterCell() - origName = masterCell.getName() - replName = origName.replace( '$$', '_unm' ) - if origName != replName: - print ' - "%s" => "%s"' % (origName,replName) - masterCell.setName( replName ) - + renameNMigen(occurrence) for occurrence in topCell.getNonTerminalNetlistInstanceOccurrences(): - masterCell = occurrence.getEntity().getMasterCell() - origName = masterCell.getName() - replName = origName.replace( '$$', '_unm' ) - if origName != replName: - print ' - "%s" => "%s"' % (origName,replName) - masterCell.setName( replName ) + renameNMigen(occurrence) return if __name__ == '__main__': parser = optparse.OptionParser() - parser.add_option( '-c', '--cell' , type='string' , dest='cellName' , help='The name of the BLIF to convert, without extension.') - parser.add_option( '-v', '--verbose' , action='store_true', dest='verbose' , help='First level of verbosity.') - parser.add_option( '-V', '--very-verbose' , action='store_true', dest='veryVerbose' , help='Second level of verbosity.') - parser.add_option( '--vst-use-concat' , action='store_true', dest='vstUseConcat' , help='The VST driver will use "&" (concat) in PORT MAP.') - parser.add_option( '--vst-no-lowercase', action='store_true', dest='vstNoLowerCase', help='The VST will keep the case of all identifiers.') - parser.add_option( '--vst-no-linkage' , action='store_true', dest='vstNoLinkage' , help='Undefined direction will be set to "in" instead of "linkage".') + parser.add_option( '-c', '--cell' , type='string' , dest='cellName' , help='The name of the BLIF to convert, without extension.') + parser.add_option( '-v', '--verbose' , action='store_true', dest='verbose' , help='First level of verbosity.') + parser.add_option( '-V', '--very-verbose' , action='store_true', dest='veryVerbose' , help='Second level of verbosity.') + parser.add_option( '--vst-use-concat' , action='store_true', dest='vstUseConcat' , help='The VST driver will use "&" (concat) in PORT MAP.') + parser.add_option( '--vst-no-lowercase' , action='store_true', dest='vstNoLowerCase' , help='The VST will keep the case of all identifiers.') + parser.add_option( '--vst-uniquify-uppercase', action='store_true', dest='vstUniquifyUpperCase', help='The uppercase identifiers will be uniquified.') + parser.add_option( '--vst-no-linkage' , action='store_true', dest='vstNoLinkage' , help='Undefined direction will be set to "in" instead of "linkage".') (options, args) = parser.parse_args() views = CRL.Catalog.State.Logical @@ -60,13 +64,14 @@ if __name__ == '__main__': if options.veryVerbose: Cfg.getParamBool('misc.verboseLevel1').setBool(True) Cfg.getParamBool('misc.verboseLevel2').setBool(True) - if options.vstUseConcat: views |= CRL.Catalog.State.VstUseConcat - if options.vstNoLowerCase: views |= CRL.Catalog.State.VstNoLowerCase - if options.vstNoLinkage: views |= CRL.Catalog.State.VstNoLinkage + if options.vstUseConcat: views |= CRL.Catalog.State.VstUseConcat + if options.vstNoLowerCase: views |= CRL.Catalog.State.VstNoLowerCase + if options.vstUniquifyUpperCase: views |= CRL.Catalog.State.VstUniquifyUpperCase + if options.vstNoLinkage: views |= CRL.Catalog.State.VstNoLinkage cell = CRL.Blif.load( options.cellName ) if cell.getName() == 'top': - print ' o Renaming RTLIL anonymous top cell "top" into "%s".' % options.cellName + print( ' o Renaming RTLIL anonymous top cell "top" into "{}".'.format(options.cellName) ) cell.setName( options.cellName ) renameNMigenUniquify( cell ) CRL.restoreNetsDirection( cell, Cell.Flags_TerminalNetlist ) diff --git a/cumulus/src/tools/yosys.py b/cumulus/src/tools/yosys.py index 57f23b2a..3c7c00ff 100755 --- a/cumulus/src/tools/yosys.py +++ b/cumulus/src/tools/yosys.py @@ -66,6 +66,7 @@ class Yosys ( object ): 'yosys hierarchy -top %(designTop)s\n' tclScript += 'yosys dfflibmap -liberty %(libertyFile)s\n' \ + 'yosys memorydff\n' \ 'yosys abc -liberty %(libertyFile)s\n' \ 'yosys clean\n' \ 'yosys write_blif %(designName)s.blif\n' diff --git a/hurricane/src/hurricane/Cell.cpp b/hurricane/src/hurricane/Cell.cpp index 2a595ee0..1e1c2e9c 100644 --- a/hurricane/src/hurricane/Cell.cpp +++ b/hurricane/src/hurricane/Cell.cpp @@ -727,16 +727,19 @@ Entity* Cell::getEntity(const Signature& signature) const return NULL; } -Net* Cell::getNet ( const Name& name ) const -//****************************************** +Net* Cell::getNet ( const Name& name, bool useAlias ) const +//********************************************************* { Net* net = _netMap.getElement(name); if (net) return net; NetAliasName key(name); AliasNameSet::iterator ialias = _netAliasSet.find( &key ); - if (ialias != _netAliasSet.end()) + if (ialias != _netAliasSet.end()) { + if (not (useAlias or (*ialias)->isExternal())) + return NULL; return (*ialias)->getNet(); + } return NULL; } diff --git a/hurricane/src/hurricane/Net.cpp b/hurricane/src/hurricane/Net.cpp index ce61554f..45f612d1 100644 --- a/hurricane/src/hurricane/Net.cpp +++ b/hurricane/src/hurricane/Net.cpp @@ -526,10 +526,24 @@ bool Net::hasAlias(const Name& name) const return false; } -bool Net::addAlias(const Name& name) -// ********************************* +NetAliasHook* Net::getAlias(const Name& name) const +// ************************************************ { - if (hasAlias(name)) return true; + if (name == _name) return dynamic_cast( const_cast( &_mainName )); + for ( NetAliasHook* alias : getAliases() ) { + if (alias->getName() == name) return alias; + } + return NULL; +} + +bool Net::addAlias(const Name& name, bool isExternal ) +// *************************************************** +{ + NetAliasHook* alias = getAlias( name ); + if (alias) { + if (isExternal) alias->setExternal( true ); + return true; + } if (getCell()->getNet(name)) { cerr << Warning( "Net::addAlias(): Cannot add alias %s to net %s, already taken." @@ -539,7 +553,7 @@ bool Net::addAlias(const Name& name) return false; } - NetAliasName* slave = new NetAliasName ( name ); + NetAliasName* slave = new NetAliasName ( name, isExternal ); _mainName.attach( slave ); getCell()->_addNetAlias( slave ); @@ -677,19 +691,22 @@ void Net::merge(Net* net) } } - Name mergedName = net->getName(); + bool mergedExternal = net->isExternal(); + Name mergedName = net->getName(); NetAliasName* slaves = NULL; if (net->_mainName.isAttached()) { slaves = dynamic_cast( net->_mainName.getNext() ); net->_mainName.detach(); } - if (net->isExternal() and not isExternal()) + if (mergedExternal and not isExternal()) { setExternal( true ); + } net->destroy(); if (slaves) _mainName.attach( slaves ); - addAlias( mergedName ); + addAlias( mergedName, mergedExternal ); + } void Net::_postCreate() @@ -711,6 +728,8 @@ void Net::_preDestroy() // ******************* { cdebug_log(18,1) << "entering Net::_preDestroy: " << this << endl; + if (getName() == "pipe_middle_0_rb[0]") + cerr << "entering Net::_preDestroy: " << this << endl; Inherit::_preDestroy(); diff --git a/hurricane/src/hurricane/NetAlias.cpp b/hurricane/src/hurricane/NetAlias.cpp index 4e15c36e..adf136d8 100644 --- a/hurricane/src/hurricane/NetAlias.cpp +++ b/hurricane/src/hurricane/NetAlias.cpp @@ -158,19 +158,22 @@ namespace Hurricane { } - bool NetMainName::isMaster () const { return true; } - bool NetMainName::isSlave () const { return false; } - Name NetMainName::getName () const { return getNet()->getName(); } - Net* NetMainName::getNet () const { return (Net*)((ptrdiff_t)this - _offset); } - string NetMainName::_getString () const { return ""; } + bool NetMainName::isMaster () const { return true; } + bool NetMainName::isSlave () const { return false; } + bool NetMainName::isExternal () const { return getNet()->isExternal(); } + Name NetMainName::getName () const { return getNet()->getName(); } + Net* NetMainName::getNet () const { return (Net*)((ptrdiff_t)this - _offset); } + string NetMainName::_getString () const { return ""; } + void NetMainName::setExternal ( bool state ) { getNet()->setExternal(state); } // ------------------------------------------------------------------- // Class : "Hurricane::NetAliasName". - NetAliasName::NetAliasName ( Name name ) + NetAliasName::NetAliasName ( Name name, bool isExternal ) : NetAliasHook() , _name (name) + , _isExternal (isExternal) { } @@ -182,9 +185,11 @@ namespace Hurricane { } - bool NetAliasName::isMaster () const { return false; } - bool NetAliasName::isSlave () const { return true; } - Name NetAliasName::getName () const { return _name; } + bool NetAliasName::isMaster () const { return false; } + bool NetAliasName::isSlave () const { return true; } + bool NetAliasName::isExternal () const { return _isExternal; } + Name NetAliasName::getName () const { return _name; } + void NetAliasName::setExternal ( bool state ) { _isExternal=state; } Net* NetAliasName::getNet () const @@ -206,7 +211,8 @@ namespace Hurricane { { Record* record = NetAliasHook::_getRecord(); if (record) { - record->add ( getSlot("_name", &_name) ); + record->add ( getSlot("_name" , &_name ) ); + record->add ( getSlot("_isExternal", &_isExternal) ); } return record; } diff --git a/hurricane/src/hurricane/hurricane/Cell.h b/hurricane/src/hurricane/hurricane/Cell.h index 00d9aac0..3fa03881 100644 --- a/hurricane/src/hurricane/hurricane/Cell.h +++ b/hurricane/src/hurricane/hurricane/Cell.h @@ -431,7 +431,7 @@ class Cell : public Entity { public: Instances getTerminalNetlistInstancesUnder(const Box& area) const; public: Instances getNonTerminalNetlistInstances() const; public: Instances getNonTerminalNetlistInstancesUnder(const Box& area) const; - public: Net* getNet(const Name& name) const; + public: Net* getNet(const Name& name, bool useAlias=true) const; public: DeepNet* getDeepNet( Path, const Net* ) const; public: Nets getNets() const {return _netMap.getElements();}; public: Nets getGlobalNets() const; diff --git a/hurricane/src/hurricane/hurricane/Net.h b/hurricane/src/hurricane/hurricane/Net.h index f95e2835..a239352f 100644 --- a/hurricane/src/hurricane/hurricane/Net.h +++ b/hurricane/src/hurricane/hurricane/Net.h @@ -210,18 +210,19 @@ class Net : public Entity { // Predicates // ********** - public: virtual bool isDeepNet () const {return false;}; - public: bool isGlobal () const {return _isGlobal;}; - public: bool isExternal () const {return _isExternal;}; - public: bool isAutomatic() const {return _isAutomatic;}; - public: bool isBlockage () const {return (_type == Type::BLOCKAGE);}; - public: bool isFused () const {return (_type == Type::FUSED);}; - public: bool isLogical () const {return (_type == Type::LOGICAL);}; - public: bool isClock () const {return (_type == Type::CLOCK);}; - public: bool isPower () const {return (_type == Type::POWER);}; - public: bool isGround () const {return (_type == Type::GROUND);}; - public: bool isSupply () const {return (isPower() || isGround());}; - public: bool hasAlias (const Name& name) const; + public: virtual bool isDeepNet () const {return false;}; + public: bool isGlobal () const {return _isGlobal;}; + public: bool isExternal () const {return _isExternal;}; + public: bool isAutomatic() const {return _isAutomatic;}; + public: bool isBlockage () const {return (_type == Type::BLOCKAGE);}; + public: bool isFused () const {return (_type == Type::FUSED);}; + public: bool isLogical () const {return (_type == Type::LOGICAL);}; + public: bool isClock () const {return (_type == Type::CLOCK);}; + public: bool isPower () const {return (_type == Type::POWER);}; + public: bool isGround () const {return (_type == Type::GROUND);}; + public: bool isSupply () const {return (isPower() || isGround());}; + public: bool hasAlias (const Name& ) const; + public: NetAliasHook* getAlias (const Name& ) const; // Updators // ******** @@ -237,7 +238,7 @@ class Net : public Entity { public: void setRoutingState(uint32_t state); public: void materialize(); public: void unmaterialize(); - public: bool addAlias(const Name& name); + public: bool addAlias(const Name& name, bool isExternal=false); public: bool removeAlias(const Name& name); public: void merge(Net* net); public: Net* getClone(Cell* cloneCell); diff --git a/hurricane/src/hurricane/hurricane/NetAlias.h b/hurricane/src/hurricane/hurricane/NetAlias.h index 0b45f913..30efc8c1 100644 --- a/hurricane/src/hurricane/hurricane/NetAlias.h +++ b/hurricane/src/hurricane/hurricane/NetAlias.h @@ -52,6 +52,7 @@ namespace Hurricane { bool isAttached () const; virtual bool isMaster () const = 0; virtual bool isSlave () const = 0; + virtual bool isExternal () const = 0; virtual Name getName () const = 0; virtual Net* getNet () const = 0; NetAliasHook* getNext () const; @@ -60,6 +61,7 @@ namespace Hurricane { void attach ( NetAliasHook* ); void detach (); void detachAll (); + virtual void setExternal ( bool ) = 0; inline void toJson ( JsonWriter* ) const; virtual std::string _getString () const = 0; virtual Record* _getRecord () const; @@ -81,9 +83,11 @@ namespace Hurricane { public: virtual bool isMaster () const; virtual bool isSlave () const; + virtual bool isExternal () const; virtual Name getName () const; virtual Net* getNet () const; virtual std::string _getString () const; + virtual void setExternal ( bool state ); void clear (); public: NetMainName ( Net* ); @@ -108,19 +112,22 @@ namespace Hurricane { public: virtual bool isMaster () const; virtual bool isSlave () const; + virtual bool isExternal () const; virtual Name getName () const; virtual Net* getNet () const; virtual void toJson ( JsonWriter* ) const; + virtual void setExternal ( bool ); virtual std::string _getString () const; virtual Record* _getRecord () const; public: - NetAliasName ( Name ); + NetAliasName ( Name, bool isExternal=false ); virtual ~NetAliasName (); private: NetAliasName ( const NetAliasName& ); NetAliasName& operator= ( const NetAliasName& ); private: Name _name; + bool _isExternal; };