diff --git a/vlsisapd/examples/dtr/cplusplus/driveDtr.cpp b/vlsisapd/examples/dtr/cplusplus/driveDtr.cpp
index e33d74e3..85c38465 100644
--- a/vlsisapd/examples/dtr/cplusplus/driveDtr.cpp
+++ b/vlsisapd/examples/dtr/cplusplus/driveDtr.cpp
@@ -8,14 +8,14 @@ using namespace std;
 int main(int argc, char * argv[]) {
     DTR::Techno* techno = new DTR::Techno(DTR::Name("MyTech"), DTR::Name("micro"));
 
-    techno->addRule (DTR::Name("transistorMinL"), 0.1 , DTR::Name("0.10"), DTR::Name("ref1"));
-    techno->addRule (DTR::Name("transistorMinW"), 0.2 , DTR::Name("0.20"), DTR::Name("ref2"));
-    techno->addRule (DTR::Name("minWidth")      , 0.15, DTR::Name("0.15"), DTR::Name("ref3"), DTR::Name("metal1"));
-    techno->addRule (DTR::Name("minSpacing")    , 0.2 , DTR::Name("0.20"), DTR::Name("ref4"), DTR::Name("metal1"));
-    techno->addRule (DTR::Name("minSpacing")    , 0.1 , DTR::Name("0.10"), DTR::Name("ref5"), DTR::Name("active"), DTR::Name("poly"));
-    techno->addARule(DTR::Name("minExtension")  , 0.2 , DTR::Name("0.20"), DTR::Name("ref6"), DTR::Name("poly")  , DTR::Name("active"));
+    techno->addRule (DTR::Name("transistorMinL"), 0.1 , DTR::Name("ref1"));
+    techno->addRule (DTR::Name("transistorMinW"), 0.2 , DTR::Name("ref2"));
+    techno->addRule (DTR::Name("minWidth")      , 0.15, DTR::Name("ref3"), DTR::Name("metal1"));
+    techno->addRule (DTR::Name("minSpacing")    , 0.2 , DTR::Name("ref4"), DTR::Name("metal1"));
+    techno->addRule (DTR::Name("minSpacing")    , 0.1 , DTR::Name("ref5"), DTR::Name("active"), DTR::Name("poly"));
+    techno->addARule(DTR::Name("minExtension")  , 0.2 , DTR::Name("ref6"), DTR::Name("poly")  , DTR::Name("active"));
     
-    DTR::Rule* rule = techno->addRule(DTR::Name("minArea"), 0.1, DTR::Name("0.10"), DTR::Name("ref7"), DTR::Name("metal1"));
+    DTR::Rule* rule = techno->addRule(DTR::Name("minArea"), 0.1, DTR::Name("ref7"), DTR::Name("metal1"));
     rule->setType(DTR::Name("area"));
 
     techno->writeToFile("./out.dtr.xml");
diff --git a/vlsisapd/examples/dtr/python/driveDtr.py b/vlsisapd/examples/dtr/python/driveDtr.py
index a0e60774..741441b0 100644
--- a/vlsisapd/examples/dtr/python/driveDtr.py
+++ b/vlsisapd/examples/dtr/python/driveDtr.py
@@ -2,14 +2,14 @@ from pyDTR import *
 
 techno = Techno(Name("myTech"), Name("micro"))
 
-techno.addRule (Name("transistorMinL"), 0.1 , Name("0.10"), Name("ref1"))
-techno.addRule (Name("transistorMinW"), 0.2 , Name("0.20"), Name("ref2"))
-techno.addRule (Name("minWidth")      , 0.15, Name("0.15"), Name("ref3"), Name("metal1"))
-techno.addRule (Name("minSpacing")    , 0.2 , Name("0.20"), Name("ref4"), Name("metal1"))
-techno.addRule (Name("minSpacing")    , 0.1 , Name("0.10"), Name("ref5"), Name("active"), Name("poly"))
-techno.addARule(Name("minExtension")  , 0.2 , Name("0.20"), Name("ref6"), Name("poly"), Name("active"))
+techno.addRule (Name("transistorMinL"), 0.1 , Name("ref1"))
+techno.addRule (Name("transistorMinW"), 0.2 , Name("ref2"))
+techno.addRule (Name("minWidth")      , 0.15, Name("ref3"), Name("metal1"))
+techno.addRule (Name("minSpacing")    , 0.2 , Name("ref4"), Name("metal1"))
+techno.addRule (Name("minSpacing")    , 0.1 , Name("ref5"), Name("active"), Name("poly"))
+techno.addARule(Name("minExtension")  , 0.2 , Name("ref6"), Name("poly"), Name("active"))
 
-rule = techno.addRule(Name("minArea"), 0.1, Name("0.10"), Name("ref7"), Name("metal1"))
+rule = techno.addRule(Name("minArea"), 0.1, Name("ref7"), Name("metal1"))
 rule.setType(Name("area"))
 
 techno.writeToFile("./out.dtr.xml")