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Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel 

Conflicts:
	oroshi/python/dtr.py
This commit is contained in:
Marie-Minerve Louërat 2020-07-22 15:00:19 +02:00
parent e7bf8022f7 34c1795630
commit be0255c27b
15 changed files with 89 additions and 31 deletions
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14
anabatic/src/NetBuilder.cpp
View File

@ -583,7 +583,9 @@ namespace Anabatic {
case Conn_1G_4M1:
case Conn_1G_5M1:
case Conn_1G_6M1:
case Conn_1G_7M1: _do_1G_xM1(); break;
case Conn_1G_7M1:
case Conn_1G_8M1:
case Conn_1G_9M1: _do_1G_xM1(); break;
// End 1G_xM1 cascaded cases.
case Conn_1G_1M2:
@ -604,12 +606,18 @@ namespace Anabatic {
case Conn_2G_4M1:
case Conn_2G_5M1:
case Conn_2G_6M1:
case Conn_2G_7M1:
case Conn_2G_8M1:
case Conn_2G_9M1:
case Conn_3G_1M1: if (_do_xG_1M1()) break;
case Conn_3G_2M1:
case Conn_3G_3M1:
case Conn_3G_4M1:
case Conn_3G_5M1:
case Conn_3G_6M1:
case Conn_3G_7M1:
case Conn_3G_8M1:
case Conn_3G_9M1:
case Conn_3G_2M3:
case Conn_3G_3M3:
case Conn_3G_4M3:
@ -619,7 +627,9 @@ namespace Anabatic {
case Conn_4G_4M1:
case Conn_4G_5M1:
case Conn_4G_6M1:
case Conn_4G_7M1: _do_xG_xM1_xM3(); break;
case Conn_4G_7M1:
case Conn_4G_8M1:
case Conn_4G_9M1: _do_xG_xM1_xM3(); break;
// End xG_xM1_xM3 cascaded cases.
case Conn_4G_1M2: if (_do_4G_1M2()) break;

10
anabatic/src/anabatic/NetBuilder.h
View File

@ -262,6 +262,8 @@ namespace Anabatic {
, Conn_1G_5M1 = CONNEXITY_VALUE( 1, 5, 0, 0, 0 , 0 )
, Conn_1G_6M1 = CONNEXITY_VALUE( 1, 6, 0, 0, 0 , 0 )
, Conn_1G_7M1 = CONNEXITY_VALUE( 1, 7, 0, 0, 0 , 0 )
, Conn_1G_8M1 = CONNEXITY_VALUE( 1, 8, 0, 0, 0 , 0 )
, Conn_1G_9M1 = CONNEXITY_VALUE( 1, 9, 0, 0, 0 , 0 )
, Conn_1G_1M2 = CONNEXITY_VALUE( 1, 0, 1, 0, 0 , 0 )
, Conn_1G_2M2 = CONNEXITY_VALUE( 1, 0, 2, 0, 0 , 0 )
, Conn_1G_3M2 = CONNEXITY_VALUE( 1, 0, 3, 0, 0 , 0 )
@ -279,6 +281,9 @@ namespace Anabatic {
, Conn_2G_4M1 = CONNEXITY_VALUE( 2, 4, 0, 0, 0 , 0 )
, Conn_2G_5M1 = CONNEXITY_VALUE( 2, 5, 0, 0, 0 , 0 )
, Conn_2G_6M1 = CONNEXITY_VALUE( 2, 6, 0, 0, 0 , 0 )
, Conn_2G_7M1 = CONNEXITY_VALUE( 2, 7, 0, 0, 0 , 0 )
, Conn_2G_8M1 = CONNEXITY_VALUE( 2, 8, 0, 0, 0 , 0 )
, Conn_2G_9M1 = CONNEXITY_VALUE( 2, 9, 0, 0, 0 , 0 )
, Conn_2G_1M2 = CONNEXITY_VALUE( 2, 0, 1, 0, 0 , 0 )
, Conn_2G_2M2 = CONNEXITY_VALUE( 2, 0, 2, 0, 0 , 0 )
, Conn_2G_3M2 = CONNEXITY_VALUE( 2, 0, 3, 0, 0 , 0 )
@ -295,6 +300,9 @@ namespace Anabatic {
, Conn_3G_4M1 = CONNEXITY_VALUE( 3, 4, 0, 0, 0 , 0 )
, Conn_3G_5M1 = CONNEXITY_VALUE( 3, 5, 0, 0, 0 , 0 )
, Conn_3G_6M1 = CONNEXITY_VALUE( 3, 6, 0, 0, 0 , 0 )
, Conn_3G_7M1 = CONNEXITY_VALUE( 3, 7, 0, 0, 0 , 0 )
, Conn_3G_8M1 = CONNEXITY_VALUE( 3, 8, 0, 0, 0 , 0 )
, Conn_3G_9M1 = CONNEXITY_VALUE( 3, 9, 0, 0, 0 , 0 )
, Conn_3G_1M2 = CONNEXITY_VALUE( 3, 0, 1, 0, 0 , 0 )
, Conn_3G_2M2 = CONNEXITY_VALUE( 3, 0, 2, 0, 0 , 0 )
, Conn_3G_1M3 = CONNEXITY_VALUE( 3, 0, 0, 1, 0 , 0 )
@ -309,6 +317,8 @@ namespace Anabatic {
, Conn_4G_5M1 = CONNEXITY_VALUE( 4, 5, 0, 0, 0 , 0 )
, Conn_4G_6M1 = CONNEXITY_VALUE( 4, 6, 0, 0, 0 , 0 )
, Conn_4G_7M1 = CONNEXITY_VALUE( 4, 7, 0, 0, 0 , 0 )
, Conn_4G_8M1 = CONNEXITY_VALUE( 4, 8, 0, 0, 0 , 0 )
, Conn_4G_9M1 = CONNEXITY_VALUE( 4, 9, 0, 0, 0 , 0 )
, Conn_4G_1M2 = CONNEXITY_VALUE( 4, 0, 1, 0, 0 , 0 )
, Conn_4G_1M3 = CONNEXITY_VALUE( 4, 0, 0, 1, 0 , 0 )
, Conn_1G_1Pad = CONNEXITY_VALUE( 1, 0, 0, 0, 1 , 0 )

2
crlcore/etc/node180/scn6m_deep_09/__init__.py
View File

@ -39,3 +39,5 @@ import node180.scn6m_deep_09.devices
import node180.scn6m_deep_09.dtr_scn6m_deep_09
Cfg.Configuration.popDefaultPriority()
helpers.tagConfModules()

2
crlcore/etc/node45/freepdk45/__init__.py
View File

@ -38,3 +38,5 @@ import node45.freepdk45.stratus1
import node45.freepdk45.devices
Cfg.Configuration.popDefaultPriority()
helpers.tagConfModules()

2
crlcore/etc/node600/phenitec/__init__.py
View File

@ -38,3 +38,5 @@ import node600.phenitec.stratus1
import node600.phenitec.devices
Cfg.Configuration.popDefaultPriority()
helpers.tagConfModules()

3
crlcore/etc/symbolic/cmos/__init__.py
View File

@ -14,6 +14,7 @@
import Cfg
import helpers
import helpers.io
helpers.io.vprint( 1, ' o Loading "symbolic.cmos" technology.' )
helpers.io.vprint( 2, ' - "%s".' % helpers.truncPath(__file__) )
@ -37,3 +38,5 @@ import symbolic.cmos.plugins
import symbolic.cmos.stratus1
Cfg.Configuration.popDefaultPriority()
helpers.tagConfModules()

1
crlcore/etc/symbolic/cmos/plugins.py
View File

@ -27,3 +27,4 @@ Cfg.getParamInt ( "chip.block.rails.vSpacing" ).setInt ( l( 6) )
Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(600) )
Cfg.getParamString( 'clockTree.buffer' ).setString( 'buf_x2')
Cfg.getParamString( 'clockTree.placerEngine' ).setString( 'Etesian')
Cfg.getParamInt ( 'block.spareSide' ).setInt ( 10 )

2
crlcore/etc/symbolic/cmos45/__init__.py
View File

@ -37,3 +37,5 @@ import symbolic.cmos45.plugins
import symbolic.cmos45.stratus1
Cfg.Configuration.popDefaultPriority()
helpers.tagConfModules()

41
crlcore/python/helpers/__init__.py
View File

@ -10,23 +10,20 @@
# | Author : Jean-Paul Chaput |
# | E-mail : Jean-Paul.Chaput@lip6.fr |
# | =============================================================== |
# | Python : "./crlcore/__init__.py" |
# | Python : "./crlcore/helpers/__init__.py" |
# +-----------------------------------------------------------------+
#
# This is file is mandatory to tell python that 'helpers' is a module
# rather than an ordinary directory, thus enabling the uses of the
# 'dot' notation in import.
#print 'helpers.__init__()'
import sys
import os
import os.path
import re
import traceback
import Hurricane
import Viewer
import CRL
import helpers.io
quiet = False
sysConfDir = None
@ -35,7 +32,17 @@ ndaDir = None
techno = 'symbolic/cmos'
technoDir = None
moduleGlobals = globals()
confModules = [ ]
sysModules = set()
confModules = set()
if not sysModules:
for moduleName in sys.modules.keys():
sysModules.add( moduleName )
import Hurricane
import Viewer
import CRL
import helpers.io
def stype ( o ): return str(type(o)).split("'")[1]
@ -397,9 +404,10 @@ setSysConfDir( False )
def unloadUserSettings ():
global confModules
print ' o Unloading Python user\'s modules.'
global confModules
for moduleName in confModules:
refcount = sys.getrefcount( sys.modules[moduleName] )
warning = ''
@ -411,16 +419,12 @@ def unloadUserSettings ():
# ] )
print ' - %-34s %-35s' % ('"%s".'%moduleName, warning)
del sys.modules[ moduleName ]
confModules = []
confModules = set()
return
def loadUserSettings ():
global confModules
rvalue = False
beforeModules = set()
for moduleName in sys.modules.keys(): beforeModules.add( moduleName )
if os.path.isfile('./coriolis2/settings.py'):
if os.path.isfile('./coriolis2/__init__.py'):
@ -434,17 +438,24 @@ def loadUserSettings ():
else:
import symbolic.cmos
tagConfModules()
return rvalue
def tagConfModules ():
global sysModules
global confModules
confModules = set()
for moduleName in sys.modules.keys():
if not (moduleName in beforeModules):
if not (moduleName in sysModules):
confModules.add( moduleName )
#print 'Configuration modules:'
#for moduleName in confModules:
# print '-', moduleName
return rvalue
def resetCoriolis ():
print ' o Full reset of Coriolis/Hurricane databases.'

2
crlcore/python/helpers/overlay.py
View File

@ -62,6 +62,8 @@ class Configuration:
Cfg.getParamEnumerate(attr).setInt( val )
else:
Cfg.getParamInt(attr).setInt( val )
elif isinstance(val, long):
p = Cfg.getParamInt( attr ) # all params have a type
elif isinstance(val, float):
p = Cfg.getParamDouble( attr ).setDouble( val )
elif '%' in val:

13
crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
View File

@ -52,8 +52,10 @@ namespace Vhdl {
const Signal* signal = entity->getGlobal( getString(masterNet->getName()) );
if (signal) return signal->getBit();
cerr << Error( "PortMap::_lookup() VHDL extension missing on parent of global <%s>."
cerr << Error( "PortMap::_lookup() VHDL extension missing on parent of global \"%s\"\n"
" In parent cell \"%s\"."
, getString(masterNet).c_str()
, getString(instance->getCell()->getName()).c_str()
) << endl;
} else {
Net* net = plug->getNet();
@ -61,12 +63,17 @@ namespace Vhdl {
Bit* bit = BitExtension::get( net );
if (bit) return bit;
cerr << Error( "PortMap::_lookup() VHDL extension missing on <%s>."
cerr << Error( "PortMap::_lookup() VHDL extension missing on \"%s\"."
" In cell \"%s\"."
, getString(net).c_str()
, getString(net->getCell()->getName()).c_str()
) << endl;
} else {
cerr << Error( "PortMap::_lookup() Unconnected <%s>."
cerr << Error( "PortMap::_lookup() Unconnected \"%s\",\n"
" In instance \"%s\" of \"%s\"."
, getString(plug).c_str()
, getString(instance->getName()).c_str()
, getString(instance->getMasterCell()->getName()).c_str()
) << endl;
}
}

1
crlcore/src/ccore/toolbox/NamingScheme.cpp
View File

@ -73,6 +73,7 @@ namespace CRL {
if (translated == '\\') translated = '_';
if (translated == '.' ) translated = '_';
if (translated == '%' ) translated = '_';
if (translated == '$' ) translated = '_';
if (translated == '?' ) translated = '_';
if (translated == ':' ) translated = '_';

16
etesian/src/EtesianEngine.cpp
View File

@ -519,8 +519,8 @@ namespace Etesian {
// if (not getBlockCell()->getAbutmentBox().isEmpty() )
// setFixedAbHeight( getBlockCell()->getAbutmentBox().getHeight() );
// getBlockCell()->setAbutmentBox( Box() );
// getBlockCell()->resetFlags( Cell::Flags::Placed );
getBlockCell()->setAbutmentBox( Box() );
getBlockCell()->resetFlags( Cell::Flags::Placed );
UpdateSession::close();
dots.finish( Dots::Reset );
@ -1002,8 +1002,10 @@ namespace Etesian {
getConfiguration()->print( getCell() );
adjustSliceHeight();
if ( (getCell() == getBlockCell()) and getCell()->getAbutmentBox().isEmpty() ) {
resetPlacement();
if (getBlockCell()->getAbutmentBox().isEmpty()) setDefaultAb();
setDefaultAb();
}
findYSpin();
toColoquinte();
@ -1020,7 +1022,6 @@ namespace Etesian {
preplace();
float_t minPenaltyIncrease, maxPenaltyIncrease, targetImprovement;
int detailedIterations, detailedEffort;
unsigned globalOptions=0, detailedOptions=0;
@ -1085,9 +1086,14 @@ namespace Etesian {
rp->invalidate();
}
}
UpdateSession::close();
getCell()->setFlags( Cell::Flags::Placed );
for ( Occurrence occurrence : getCell()->getNonTerminalNetlistInstanceOccurrences(getBlockInstance()) ) {
Instance* instance = static_cast<Instance*>(occurrence.getEntity());
if (instance->getPlacementStatus() == Instance::PlacementStatus::UNPLACED)
instance->setPlacementStatus( Instance::PlacementStatus::PLACED );
}
UpdateSession::close();
}

1
katana/src/KatanaEngine.cpp
View File

@ -419,6 +419,7 @@ namespace Katana {
return NULL;
}
void KatanaEngine::openSession ()
{ Session::_open(this); }

4
oroshi/python/dtr.py
View File

@ -5,9 +5,7 @@ from helpers import trace
class Rules ( object ):
ruleSet = [ 'minWidth_nWell'
, 'minSpacing_nWell'
, 'minEnclosure_nWell_active'
ruleSet = [ 'minSpacing_nWell'
, 'minWidth_pImplant'
, 'minSpacing_pImplant'
, 'minSpacing_rpolyh_pImplant'