The VHDL driver must not rename Cell/Instance/Net names.

* Change: In CRL Core, the Alliance VHDL (vst) driver was renaming the
    names of Cells, Instances and Nets into their VHDL conterparts.
    But if we still work on the Cell after saving it, the Net renaming
    will cause touble, especially when there are DeepNets. The name
    of the DeepNet is generated from the Occurrence name with the dot
    separator which is *not* a VHDL valid character for name, thus
    after that the DeepNet name has changed it cannot be reassociated
    with the Occurrence path. This was causing double-flattening issues.

crlcore/src/ccore/alliance/vst/VhdlEntity.cpp

@@ -100,7 +100,8 @@ namespace Vhdl {
 
 
   Entity::Entity ( EntityProperty* property, Cell* cell, unsigned int flags )
-    : _signals()
+    : _ns     (NamingScheme::FromVerilog)
+    , _signals()
     , _globals()
     , _flags  (flags)
   {
@@ -163,7 +164,7 @@ namespace Vhdl {
   bool  Entity::parseNetName (  const Net* net, string& stem, size_t& index  )
   {
     string error;
-    string name     = getString(net->getName());
+    string name     = getString(_ns.convert(net->getName()));
     size_t leftpar  = name.find( '(' );
     size_t rightpar = name.find( ')' );
 
@@ -336,11 +337,12 @@ namespace Vhdl {
       out << "use IEEE.numeric_std.all;\n\n\n";
     }
 
-    out << tab++ << "entity " << getCell()->getName() << " is\n";
+    string cellName = getString( _ns.convert( getCell()->getName()) );
+    out << tab++ << "entity " << cellName << " is\n";
     toPort( out );
-    out << --tab << "\nend " << getCell()->getName() << ";\n\n";
+    out << --tab << "\nend " << cellName << ";\n\n";
 
-    out << "architecture structural of " <<  getCell()->getName() << " is\n\n";
+    out << "architecture structural of " <<  cellName << " is\n\n";
     ++tab;
 
     set<Cell*> masterCells;
@@ -371,7 +373,9 @@ namespace Vhdl {
 
   void Entity::toComponent ( ostream& out ) const
   {
-    out << tab++ << "component " << getCell()->getName() << "\n";
+    string cellName = getString( _ns.convert( getCell()->getName()) );
+
+    out << tab++ << "component " << cellName << "\n";
     toPort( out );
     out << "\n" << --tab << "end component;\n";
   }
@@ -379,7 +383,10 @@ namespace Vhdl {
 
   void Entity::toInstance ( ostream& out, Instance* instance ) const
   {
-    out << tab << instance->getName() << " : " << instance->getMasterCell()->getName() << "\n";
+    string instanceName = getString( _ns.convert( instance->getName() ) );
+    string masterName   = getString( _ns.convert( instance->getMasterCell()->getName() ) );
+
+    out << tab << instanceName << " : " << masterName << "\n";
     out << tab << "port map ( ";
 
     Entity* masterEntity = EntityExtension::get( instance->getMasterCell() );

crlcore/src/ccore/alliance/vst/VstDriver.cpp

@@ -38,7 +38,7 @@ namespace CRL {
 
   void  vstDriver ( const string cellPath, Cell *cell, unsigned int &saveState )
   {
-    NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
+  //NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
     Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell
                                                             , Vhdl::Entity::EntityMode
                                                           //| Vhdl::Entity::IeeeMode

crlcore/src/ccore/crlcore/ToolBox.h

@@ -71,6 +71,10 @@ namespace CRL {
     public:
       static Name  vlogToVhdl   ( const Name& vlogName );
       static void  toVhdl       ( Cell* topCell, unsigned int flags );
+                   NamingScheme ( unsigned int flags );
+             Name  convert      ( const Name& ) const;
+    private:
+      converter_t  _converter;
   };
 
 

crlcore/src/ccore/crlcore/VhdlEntity.h

@@ -25,6 +25,7 @@ namespace Hurricane {
   class Net;
   class Instance;
 }
+#include "crlcore/ToolBox.h"
 #include "crlcore/VhdlSignal.h"
 
 
@@ -38,6 +39,7 @@ namespace Vhdl {
   using Hurricane::Cell;
   using Hurricane::Instance;
   using Hurricane::PrivateProperty;
+  using CRL::NamingScheme;
 
   class Signal;
   class ScalarSignal;
@@ -64,7 +66,6 @@ namespace Vhdl {
                 , AsInnerSignal = 0x0010
                 };
     public:
-      static bool             parseNetName    ( const Net*, std::string& stem, size_t& index );
       static std::vector<Entity*>&
                               getAllEntities  ();
     public:           
@@ -83,11 +84,13 @@ namespace Vhdl {
              void             toComponent     ( std::ostream& ) const;
              void             toInstance      ( std::ostream&, Instance* ) const;
              void             toEntity        ( std::ostream& ) const;
+             bool             parseNetName    ( const Net*, std::string& stem, size_t& index );
              std::string      _getString      () const;
              Record*          _getRecord      () const;
     private:
       static std::vector<Entity*>  _entities;
       static std::ptrdiff_t        _offset;
+             NamingScheme          _ns;
              SignalSet             _signals;
              SignalSet             _globals;
              unsigned int          _flags;

crlcore/src/ccore/toolbox/NamingScheme.cpp

@@ -127,4 +127,18 @@ namespace CRL {
   }
 
 
+  NamingScheme::NamingScheme ( unsigned int flags )
+    : _converter(nullptr)
+  {
+    if (flags & FromVerilog) _converter = vlogToVhdl;
+  }
+
+
+  Name  NamingScheme::convert ( const Name& name ) const
+  {
+    if (_converter == nullptr) return name;
+    return _converter(name);
+  }
+
+
 }  // CRL namespace.