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Analog intergration part III. Removing obsoleted vlsisapd/openChams.

This commit is contained in:
Jean-Paul Chaput 2018-10-18 18:26:15 +02:00
parent fcd6d69a2f
commit ac51ac3910
58 changed files with 3 additions and 7089 deletions
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7
vlsisapd/examples/CMakeLists.txt
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@ -1,10 +1,5 @@
ADD_SUBDIRECTORY(cif) ADD_SUBDIRECTORY(cif)
ADD_SUBDIRECTORY(agds) ADD_SUBDIRECTORY(agds)
if( IS_DIRECTORY dtr ) ADD_SUBDIRECTORY(dtr)
ADD_SUBDIRECTORY(dtr)
endif( IS_DIRECTORY dtr )
if( IS_DIRECTORY openChams )
ADD_SUBDIRECTORY(openChams)
endif( IS_DIRECTORY openChams )
ADD_SUBDIRECTORY(liberty) ADD_SUBDIRECTORY(liberty)
ADD_SUBDIRECTORY(spice) ADD_SUBDIRECTORY(spice)

8
vlsisapd/examples/openChams/CMakeLists.txt
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@ -1,8 +0,0 @@
ADD_SUBDIRECTORY(cplusplus)
ADD_SUBDIRECTORY(python)
SET ( XML_FILES inverter.xml
buffer.xml
)
INSTALL ( FILES ${XML_FILES} DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )

92
vlsisapd/examples/openChams/buffer.xml
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@ -1,92 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<circuit name="buffer" techno="myTech">
<subCircuitsPaths>
<path path="."/>
</subCircuitsPaths>
<netlist>
<instances>
<instance name="inv1" model="inverter">
<connectors>
<connector name="vdd"/>
<connector name="vss"/>
<connector name="in" />
<connector name="out"/>
</connectors>
</instance>
<instance name="inv2" model="inverter">
<connectors>
<connector name="vdd"/>
<connector name="vss"/>
<connector name="in" />
<connector name="out"/>
</connectors>
</instance>
</instances>
<nets>
<net name="vdd" type="power" isExternal="True">
<connector instance="inv1" name="vdd"/>
<connector instance="inv2" name="vdd"/>
</net>
<net name="vss" type="ground" isExternal="True">
<connector instance="inv1" name="vss"/>
<connector instance="inv2" name="vss"/>
</net>
<net name="in" type="logical" isExternal="True">
<connector instance="inv1" name="in"/>
</net>
<net name="out" type="logical" isExternal="True">
<connector instance="inv2" name="out"/>
</net>
<net name="internal" type="logical" isExternal="False">
<connector instance="inv1" name="out"/>
<connector instance="inv2" name="in"/>
</net>
</nets>
</netlist>
<schematic>
<instance name="inv1" x="2490" y="2600" orient="ID"/>
<instance name="inv2" x="2490" y="2300" orient="ID"/>
<net name="in">
<port type="inV" idx="0" x="2415" y="2700" orient="MY"/>
<wire>
<connector name="inv1" plug="in"/>
<connector idx="0"/>
</wire>
</net>
<net name="internal">
<wire>
<connector name="inv1" plug="out"/>
<connector name="inv2" plug="in"/>
</wire>
</net>
<net name="out">
<port type="outV" idx="0" x="2415" y="2200" orient="MY"/>
<wire>
<connector name="inv2" plug="out"/>
<connector idx="0"/>
</wire>
</net>
<net name="vdd">
<port type="inH" idx="0" x="2200" y="2500" orient="ID"/>
<wire>
<connector idx="0"/>
<connector name="inv2" plug="vdd"/>
</wire>
<wire>
<connector name="inv1" plug="vdd"/>
<connector name="inv2" plug="vdd"/>
</wire>
</net>
<net name="vss">
<port type="inH" idx="0" x="2700" y="2500" orient="MX"/>
<wire>
<connector idx="0"/>
<connector name="inv2" plug="vss"/>
</wire>
<wire>
<connector name="inv1" plug="vss"/>
<connector name="inv2" plug="vss"/>
</wire>
</net>
</schematic>
</circuit>

8
vlsisapd/examples/openChams/cplusplus/CMakeLists.txt
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@ -1,8 +0,0 @@
INCLUDE_DIRECTORIES ( ${VLSISAPD_SOURCE_DIR}/src/openChams/src ${LIBXML2_INCLUDE_DIR})
ADD_EXECUTABLE ( driveOpenChams driveOpenChams.cpp )
ADD_EXECUTABLE ( parseOpenChams parseOpenChams.cpp )
TARGET_LINK_LIBRARIES ( driveOpenChams openChams ${LIBXML_LIBRARIES}) # 'driveOpenChams' is the name of the executable and 'openChams' the name of the target library in openChams/src/CMakeLists.txt
TARGET_LINK_LIBRARIES ( parseOpenChams openChams ${LIBXML_LIBRARIES})
INSTALL ( TARGETS driveOpenChams parseOpenChams DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )
INSTALL ( FILES driveOpenChams.cpp parseOpenChams.cpp DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )
INSTALL ( FILES cmake.ex DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams RENAME CMakeLists.txt )

18
vlsisapd/examples/openChams/cplusplus/cmake.ex
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@ -1,18 +0,0 @@
PROJECT(PARSEDRIVEOPENCHAMS)
CMAKE_MINIMUM_REQUIRED(VERSION 2.4.0)
SET(CMAKE_MODULE_PATH "$ENV{VLSISAPD_USER_TOP}/share/cmake/Modules"
"$ENV{VLSISAPD_TOP}/share/cmake/Modules"
)
FIND_PACKAGE(VLSISAPD REQUIRED)
FIND_PACKAGE(Libxml2 REQUIRED)
IF(OPENCHAMS_FOUND)
INCLUDE_DIRECTORIES(${OPENCHAMS_INCLUDE_DIR} ${LIBXML2_INCLUDE_DIR})
ADD_EXECUTABLE(driveOpenChams driveOpenChams.cpp)
ADD_EXECUTABLE(parseOpenChams parseOpenChams.cpp)
TARGET_LINK_LIBRARIES(driveOpenChams ${OPENCHAMS_LIBRARY} ${LIBXML2_LIBRARIES})
TARGET_LINK_LIBRARIES(parseOpenChams ${OPENCHAMS_LIBRARY} ${LIBXML2_LIBRARIES})
ENDIF(OPENCHAMS_FOUND)

125
vlsisapd/examples/openChams/cplusplus/driveOpenChams.cpp
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@ -1,125 +0,0 @@
#include <string>
using namespace std;
#include "vlsisapd/openChams/Circuit.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Device.h"
#include "vlsisapd/openChams/Transistor.h"
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/Schematic.h"
#include "vlsisapd/openChams/Sizing.h"
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/Node.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
int main(int argc, char * argv[]) {
OpenChams::Circuit* circuit = new OpenChams::Circuit(OpenChams::Name("design"), OpenChams::Name("myTech"));
// value parameters
circuit->addParameter(OpenChams::Name("temp"), "27.0" );
circuit->addParameter(OpenChams::Name("Vdd") , "1.2" );
circuit->addParameter(OpenChams::Name("Vss") , "0.0" );
circuit->addParameter(OpenChams::Name("L") , "0.1e-6");
circuit->addParameter(OpenChams::Name("Ids") , "30e-6" );
circuit->addParameter(OpenChams::Name("Veg") , "0.12" );
// equation parameters
circuit->addParameter(OpenChams::Name("complex"), "myEq");
// netlist
OpenChams::Netlist* netlist = circuit->createNetlist();
// instances
// nmos1
OpenChams::Device* inst_nmos1 = netlist->addDevice(OpenChams::Name("nmos1"), OpenChams::Name("Transistor"), 1, OpenChams::Name("NMOS"), true);
inst_nmos1->addConnector(OpenChams::Name("G"));
inst_nmos1->addConnector(OpenChams::Name("S"));
inst_nmos1->addConnector(OpenChams::Name("D"));
OpenChams::Transistor* tr_nmos1 = inst_nmos1->addTransistor(OpenChams::Name("m1"));
tr_nmos1->setGate (OpenChams::Name("G")); // the name of the connector of inst_nmos1
tr_nmos1->setSource(OpenChams::Name("S"));
tr_nmos1->setDrain (OpenChams::Name("D"));
tr_nmos1->setBulk (OpenChams::Name("S"));
// pmos1
OpenChams::Device* inst_pmos1 = netlist->addDevice(OpenChams::Name("pmos1"), OpenChams::Name("Transistor"), 2, OpenChams::Name("PMOS"), true);
inst_pmos1->addConnector(OpenChams::Name("G"));
inst_pmos1->addConnector(OpenChams::Name("S"));
inst_pmos1->addConnector(OpenChams::Name("D"));
OpenChams::Transistor* tr_pmos1 = inst_pmos1->addTransistor(OpenChams::Name("m1"));
tr_pmos1->setGate (OpenChams::Name("G")); // the name of the connector of inst_pmos1
tr_pmos1->setSource(OpenChams::Name("S"));
tr_pmos1->setDrain (OpenChams::Name("D"));
tr_pmos1->setBulk (OpenChams::Name("S"));
// nets
OpenChams::Net* _vdd = netlist->addNet(OpenChams::Name("vdd"), OpenChams::Name("power") , true);
OpenChams::Net* _vss = netlist->addNet(OpenChams::Name("vss"), OpenChams::Name("ground") , true);
OpenChams::Net* _in = netlist->addNet(OpenChams::Name("in" ), OpenChams::Name("logical"), true);
OpenChams::Net* _out = netlist->addNet(OpenChams::Name("out"), OpenChams::Name("logical"), true);
_vdd->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("S"));
_vss->connectTo(OpenChams::Name("nmos1"), OpenChams::Name("S"));
_in->connectTo (OpenChams::Name("nmos1"), OpenChams::Name("G"));
_in->connectTo (OpenChams::Name("pmos1"), OpenChams::Name("G"));
_out->connectTo(OpenChams::Name("nmos1"), OpenChams::Name("D"));
_out->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("D"));
// schematic
OpenChams::Schematic* schematic = circuit->createSchematic();
schematic->addInstance(OpenChams::Name("nmos1"), 2490, 2600, OpenChams::Name("ID"));
schematic->addInstance(OpenChams::Name("pmos1"), 2490, 2300, OpenChams::Name("ID"));
_vdd->addPort(OpenChams::Name("inV"), 0, 2490, 2100, OpenChams::Name("ID"));
OpenChams::Wire* wVdd = _vdd->addWire();
wVdd->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("S"));
wVdd->setEndPoint (0);
_vss->addPort(OpenChams::Name("inV"), 0, 2490, 2800, OpenChams::Name("MY"));
OpenChams::Wire* wVss = _vss->addWire();
wVss->setStartPoint(OpenChams::Name("nmos1"), OpenChams::Name("S"));
wVss->setEndPoint (0);
_in->addPort(OpenChams::Name("inH"), 0, 2190, 2500, OpenChams::Name("ID"));
OpenChams::Wire* wIn = _in->addWire();
wIn->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("G"));
wIn->setEndPoint (OpenChams::Name("nmos1"), OpenChams::Name("G"));
OpenChams::Wire* wIn1 = _in->addWire();
wIn1->setStartPoint(0);
wIn1->setEndPoint (OpenChams::Name("pmos1"), OpenChams::Name("G"));
_out->addPort(OpenChams::Name("outH"), 0, 2600, 2500, OpenChams::Name("ID"));
OpenChams::Wire* wOut = _out->addWire();
wOut->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("D"));
wOut->setEndPoint (OpenChams::Name("nmos1"), OpenChams::Name("D"));
OpenChams::Wire* wOut1 = _out->addWire();
wOut1->setStartPoint(OpenChams::Name("nmos1"), OpenChams::Name("D"));
wOut1->setEndPoint (0);
// sizing
OpenChams::Sizing* sizing = circuit->createSizing();
OpenChams::Operator* op_pmos1 = sizing->addOperator(OpenChams::Name("pmos1"), OpenChams::Name("OPVG(Veg)"), OpenChams::Name("BSIM3V3"));
op_pmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
op_pmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids") );
op_pmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L") );
op_pmos1->addConstraint(OpenChams::Name("Veg") , OpenChams::Name("design"), OpenChams::Name("Veg") );
op_pmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("design"), OpenChams::Name("Vdd") , 0.5);
op_pmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd") );
OpenChams::Operator* op_nmos1 = sizing->addOperator(OpenChams::Name("nmos1"), OpenChams::Name("OPW(Vg,Vs)"), OpenChams::Name("BSIM3V3"));
op_nmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
op_nmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids" ));
op_nmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L" ));
op_nmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd" ));
op_nmos1->addConstraint(OpenChams::Name("Vg") , OpenChams::Name("pmos1") , OpenChams::Name("Vg" ));
op_nmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("pmos1") , OpenChams::Name("Vd" ));
op_nmos1->addConstraint(OpenChams::Name("another"), OpenChams::Name("myEq"), -2.5 );
// layout
OpenChams::Layout* layout = circuit->createLayout();
layout->addInstance(OpenChams::Name("pmos1"), OpenChams::Name("Common transistor"));
layout->addInstance(OpenChams::Name("nmos1"), OpenChams::Name("Rotate transistor"));
// create hbtree
OpenChams::Group* g1 = new OpenChams::Group("g1"); // default position is NONE and default parent is NULL
g1->setAlign(OpenChams::Group::VERTICAL);
OpenChams::Bloc* b1 = new OpenChams::Bloc("nmos1", OpenChams::Node::NONE, g1);
g1->setRootNode(b1); // b1 is root node of group g1
OpenChams::Bloc* b2 = new OpenChams::Bloc("pmos1", OpenChams::Node::TOP, b1);
b1->setTop(b2); // b2 is on top of b1
layout->setHBTreeRoot(g1); // g1 is the root of the tree
circuit->writeToFile("./myInverter.xml");
return 0;
}

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vlsisapd/examples/openChams/cplusplus/parseOpenChams.cpp
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@ -1,231 +0,0 @@
#include <iostream>
#include <string>
#include <map>
#include <vector>
using namespace std;
#include "vlsisapd/openChams/Circuit.h"
#include "vlsisapd/openChams/Name.h"
#include "vlsisapd/openChams/Parameters.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Device.h"
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/Transistor.h"
#include "vlsisapd/openChams/Schematic.h"
#include "vlsisapd/openChams/Sizing.h"
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/Node.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
void printHBTree(OpenChams::Node* node, unsigned indent) {
if (!node) return; // since we pass nnode->getRight and node-getTop without checking for NULL
for (unsigned i = 0 ; i < indent ; i++) {
cerr << " |";
}
string pos = "";
switch(node->getPosition()) {
case OpenChams::Node::TOP:
pos = "top";
break;
case OpenChams::Node::RIGHT:
pos = "right";
break;
default:
break;
}
OpenChams::Bloc* bloc = dynamic_cast<OpenChams::Bloc*>(node);
if (bloc) {
cerr << " bloc: " << bloc->getName().getString() << " - " << pos << endl;
printHBTree(bloc->getTop() , indent+1);
printHBTree(bloc->getRight(), indent+1);
return;
}
OpenChams::Group* group = dynamic_cast<OpenChams::Group*>(node);
if (group) {
string align = "none";
switch(group->getAlign()) {
case OpenChams::Group::VERTICAL:
align = "vertical";
break;
case OpenChams::Group::HORIZONTAL:
align = "horizontal";
break;
default:
break;
}
cerr << " group: " << group->getName().getString() << " - " << pos << " - align: " << align << " - isolated: " << group->isIsolated() << " - paired: " << group->isPaired() << endl;
printHBTree(group->getRootNode(), indent+1);
printHBTree(group->getTop() , indent+1);
printHBTree(group->getRight() , indent+1);
return;
}
cerr << "[ERROR] printHBTree: node is nor a bloc nor a group !" << endl;
return;
}
int main(int argc, char * argv[]) {
string file = "";
if (argc == 1)
file = "./inverter.xml";
else if (argc == 2)
file = argv[1];
else {
cerr << "Usage: openChamsParser [filename]" << endl;
exit(1);
}
OpenChams::Circuit* circuit = NULL;
try {
circuit = OpenChams::Circuit::readFromFile(file);
} catch (OpenChams::OpenChamsException& e) {
cerr << e.what() << endl;
exit(48);
}
cerr << circuit->getName().getString() << endl;
cerr << " + parameters" << endl;
OpenChams::Parameters params = circuit->getParameters();
if (!params.isEmpty()) {
for (map<OpenChams::Name, string>::const_iterator it = params.getValues().begin() ; it != params.getValues().end() ; ++it) {
cerr << " | | " << ((*it).first).getString() << " : " << (*it).second << endl;
}
}
cerr << " + netlist" << endl;
cerr << " | + instances" << endl;
OpenChams::Netlist* netlist = circuit->getNetlist();
if (netlist && !netlist->hasNoInstances()) {
for (size_t i = 0 ; i < netlist->getInstances().size() ; i++) {
OpenChams::Instance* inst = netlist->getInstances()[i];
OpenChams::Device* dev = NULL;
if (dynamic_cast<OpenChams::Device*>(inst)) {
dev = static_cast<OpenChams::Device*>(inst);
cerr << " | | + " << dev->getName().getString() << " : " << dev->getModel().getString() << " - " << dev->getOrder() << " - " << dev->getMosType().getString() << " - " << (dev->isSourceBulkConnected()?"true":"false") << endl;
} else {
cerr << " | | + " << inst->getName().getString() << " : " << inst->getModel().getString() << " - " << inst->getOrder() << endl;
}
cerr << " | | | + connectors" << endl;
for (map<OpenChams::Name, OpenChams::Net*>::const_iterator cit = inst->getConnectors().begin() ; cit != inst->getConnectors().end() ; ++cit) {
if ((*cit).second)
cerr << " | | | | " << ((*cit).first).getString() << " : " << ((*cit).second)->getName().getString() << endl;
else
cerr << " | | | | " << ((*cit).first).getString() << endl; // no net connected !
}
if (dev) {
cerr << " | | | + transistors" << endl;
for (size_t j = 0 ; j < dev->getTransistors().size() ; j++) {
OpenChams::Transistor* tr = dev->getTransistors()[j];
cerr << " | | | | name: " << tr->getName().getString() << " - gate: " << tr->getGate().getString() << " - source: " << tr->getSource().getString() << " - drain: " << tr->getDrain().getString() << " - bulk: " << tr->getBulk().getString() << endl;
}
}
}
}
cerr << " | + nets" << endl;
bool schematicNet = false; // define wether net sections are needed in schematic section
if (!netlist->hasNoNets()) {
for (size_t i = 0 ; i < netlist->getNets().size() ; i++) {
OpenChams::Net* net = netlist->getNets()[i];
cerr << " | | + " << net->getName().getString() << " : " << net->getType().getString() << " - " << (net->isExternal()?"true":"false") << endl;
cerr << " | | | + connections" << endl;
for (size_t j = 0 ; j < net->getConnections().size() ; j++) {
OpenChams::Net::Connection* connect = net->getConnections()[j];
cerr << " | | | | " << connect->getInstanceName().getString() << "." << connect->getConnectorName().getString() << endl;
}
if (!net->hasNoPorts() || !net->hasNoWires())
schematicNet = true;
}
}
OpenChams::Schematic* schematic = circuit->getSchematic();
if (schematic && !schematic->hasNoInstances()) {
cerr << " + schematic" << endl;
for (map<OpenChams::Name, OpenChams::Schematic::Infos*>::const_iterator sit = schematic->getInstances().begin() ; sit != schematic->getInstances().end() ; ++sit) {
OpenChams::Schematic::Infos* inf = (*sit).second;
cerr << " | + instance: name: " << ((*sit).first).getString() << " - x: " << inf->getX() << " - y: " << inf->getY() << " - orientation: " << inf->getOrientation().getString() << endl;
}
if (schematicNet) {
for (size_t i = 0 ; i < netlist->getNets().size() ; i++) {
OpenChams::Net* net = netlist->getNets()[i];
cerr << " | + net name: " << net->getName().getString() << endl;
if (!net->hasNoPorts()) {
for (size_t j = 0 ; j < net->getPorts().size() ; j++) {
OpenChams::Port* port = net->getPorts()[j];
cerr << " | | + port type: " << port->getType().getString() << " - idx: " << port->getIndex() << " - x: " << port->getX() << " - y: " << port->getY() << " - orientation: " << port->getOrientation().getString() << endl;
}
}
if (!net->hasNoWires()) {
for (size_t j = 0 ; j < net->getWires().size() ; j++) {
OpenChams::Wire* wire = net->getWires()[j];
cerr << " | | + wire ";
OpenChams::WirePoint* start = wire->getStartPoint();
if (dynamic_cast<OpenChams::InstancePoint*>(start)) {
OpenChams::InstancePoint* iP = static_cast<OpenChams::InstancePoint*>(start);
cerr << "<" << iP->getName().getString() << "," << iP->getPlug().getString() << "> ";
} else if (dynamic_cast<OpenChams::PortPoint*>(start)) {
OpenChams::PortPoint* pP = static_cast<OpenChams::PortPoint*>(start);
cerr << "<" << pP->getIndex() << "> ";
}
for (size_t k = 0 ; k < wire->getIntermediatePoints().size() ; k++) {
OpenChams::IntermediatePoint* iP = wire->getIntermediatePoints()[k];
cerr << "<" << iP->getX() << "," << iP->getY() << "> ";
}
OpenChams::WirePoint* end = wire->getEndPoint();
if (dynamic_cast<OpenChams::InstancePoint*>(end)) {
OpenChams::InstancePoint* iP = static_cast<OpenChams::InstancePoint*>(end);
cerr << "<" << iP->getName().getString() << "," << iP->getPlug().getString() << "> ";
} else if (dynamic_cast<OpenChams::PortPoint*>(end)) {
OpenChams::PortPoint* pP = static_cast<OpenChams::PortPoint*>(end);
cerr << "<" << pP->getIndex() << "> ";
}
cerr << endl;
}
}
}
}
}
OpenChams::Sizing* sizing = circuit->getSizing();
if (sizing) {
cerr << " + sizing" << endl;
if (!sizing->hasNoOperators()) {
for (map<OpenChams::Name, OpenChams::Operator*>::const_iterator oit = sizing->getOperators().begin() ; oit != sizing->getOperators().end() ; ++oit) {
OpenChams::Operator* op = (*oit).second;
cerr << " | + instance name: " << ((*oit).first).getString() << " - operator: " << op->getName().getString() << " - simulModel: " << op->getSimulModel().getString() << endl;
if (!op->hasNoConstraints()) {
for (map<OpenChams::Name, OpenChams::Operator::Constraint*>::const_iterator cit = op->getConstraints().begin() ; cit != op->getConstraints().end() ; ++cit) {
OpenChams::Operator::Constraint* cstr = (*cit).second;
cerr << " | | + param: " << ((*cit).first).getString() << " - ref: " << cstr->getRef().getString() << " - refParam: " << cstr->getRefParam().getString() << " - factor: " << cstr->getFactor() << endl;
}
}
}
}
// To update to the new equations.
// if (!sizing->hasNoEquations()) {
// cerr << " | + equations" << endl;
// for (map<OpenChams::Name, string>::const_iterator eit = sizing->getEquations().begin() ; eit != sizing->getEquations().end() ; ++eit) {
// cerr << " | | " << ((*eit).first).getString() << " : " << (*eit).second << endl;
// }
// }
}
OpenChams::Layout* layout = circuit->getLayout();
if (layout) {
if (!layout->hasNoInstance()) {
cerr << " + layout" << endl;
for (map<OpenChams::Name, OpenChams::Name>::const_iterator lit = layout->getInstances().begin() ; lit != layout->getInstances().end() ; ++lit) {
cerr << " | | instance name: " << ((*lit).first).getString() << " - style: " << ((*lit).second).getString() << endl;
}
}
OpenChams::Node* root = layout->getHBTreeRoot();
if (root) {
cerr << " | + hbtree" << endl;
printHBTree(root, 2);
}
}
return 0;
}

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@ -1,130 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<circuit name="inverter" techno="myTech">
<parameters>
<parameter name="temp" value="27.0"/>
<parameter name="Vdd" value="1.2"/>
<parameter name="Vss" value="0.0"/>
<parameter name="L" value="0.10e-6"/>
<parameter name="Ids" value="30e-6"/>
<parameter name="Veg" value="0.12"/>
<parameterEq name="complex" equation="myEq"/>
</parameters>
<netlist>
<instances>
<instance name="nmos1" model="Transistor" order="1" mostype="NMOS" sourceBulkConnected="True">
<connectors>
<connector name="G"/>
<connector name="D"/>
<connector name="S"/>
</connectors>
<transistors>
<transistor name="m1">
<connection gate="G" source="S" drain="D" bulk="S"/>
</transistor>
</transistors>
</instance>
<instance name="pmos1" model="Transistor" order="2" mostype="PMOS" sourceBulkConnected="True">
<connectors>
<connector name="G"/>
<connector name="D"/>
<connector name="S"/>
</connectors>
<transistors>
<transistor name="m1">
<connection gate="G" source="S" drain="D" bulk="S"/>
</transistor>
</transistors>
</instance>
</instances>
<nets>
<net name="vdd" type="power" isExternal="True">
<connector instance="pmos1" name="S"/>
</net>
<net name="vss" type="ground" isExternal="True">
<connector instance="nmos1" name="S"/>
</net>
<net name="in" type="logical" isExternal="True">
<connector instance="nmos1" name="G"/>
<connector instance="pmos1" name="G"/>
</net>
<net name="out" type="logical" isExternal="True">
<connector instance="nmos1" name="D"/>
<connector instance="pmos1" name="D"/>
</net>
</nets>
</netlist>
<schematic>
<instance name="nmos1" x="2490" y="2600" orient="ID"/>
<instance name="pmos1" x="2490" y="2490" orient="ID"/>
<net name="vdd">
<port type="inV" idx="0" x="2525" y="2430" orient="ID"/>
<wire>
<connector name="pmos1" plug="S"/>
<!--point x="" y=""/-->
<connector idx="0"/>
</wire>
</net>
<net name="vss">
<port type="inV" idx="0" x="2525" y="2740" orient="MY"/>
<wire>
<connector name="nmos1" plug="S"/>
<connector idx="0"/>
</wire>
</net>
<net name="in">
<port type="inH" idx="0" x="2415" y="2520" orient="ID"/>
<wire>
<connector name="pmos1" plug="G"/>
<connector name="nmos1" plug="G"/>
</wire>
<wire>
<connector idx="0"/>
<connector name="pmos1" plug="G"/>
</wire>
</net>
<net name="out">
<port type="outH" idx="0" x="2570" y="2590" orient="ID"/>
<wire>
<connector name="pmos1" plug="D"/>
<connector name="nmos1" plug="D"/>
</wire>
<wire>
<connector name="nmos1" plug="D"/>
<connector idx="0"/>
</wire>
</net>
</schematic>
<sizing>
<instance name="pmos1" operator="OPVG(Veg)" simulModel="BSIM3V3">
<constraint param="Temp" ref="design" refParam="temp"/>
<constraint param="Ids" ref="design" refParam="Ids"/>
<constraint param="L" ref="design" refParam="L"/>
<constraint param="Veg" ref="design" refParam="Veg"/>
<constraint param="Vd" ref="design" refParam="Vdd" factor="0.5"/>
<constraint param="Vs" ref="design" refParam="Vdd"/>
</instance>
<instance name="nmos1" operator="OPW(Vg,Vs)" simulModel="BSIM3V3">
<constraint param="Temp" ref="design" refParam="temp"/>
<constraint param="Ids" ref="design" refParam="Ids"/>
<constraint param="L" ref="design" refParam="L"/>
<constraint param="Vs" ref="design" refParam="Vdd"/>
<constraint param="Vg" ref="pmos1" refParam="Vg"/>
<constraint param="Vd" ref="pmos1" refParam="Vd"/>
<constraint param="another" refEquation="myEq" factor="-2.5"/>
</instance>
<equations>
<eq name="myEq" equation="A/more+complex*equation"/>
</equations>
</sizing>
<layout>
<instance name="pmos1" style="Common transistor"/>
<instance name="nmos1" style="Rotate transistor"/>
<hbtree>
<group name="g1" align="vertical">
<bloc name="nmos1">
<bloc name="pmos1" position="top"/>
</bloc>
</group>
</hbtree>
</layout>
</circuit>

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vlsisapd/examples/openChams/python/CMakeLists.txt
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INSTALL ( FILES driveOpenChams.py parseOpenChams.py DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )

104
vlsisapd/examples/openChams/python/driveOpenChams.py
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@ -1,104 +0,0 @@
from OPENCHAMS import *
circuit = Circuit(Name("design"), Name("myTech"))
# value parameters
circuit.addParameter(Name("temp"), 27.0 )
circuit.addParameter(Name("Vdd") , 1.2 )
circuit.addParameter(Name("Vss") , 0.0 )
circuit.addParameter(Name("L") , 0.1e-6)
circuit.addParameter(Name("Ids") , 30e-6 )
circuit.addParameter(Name("Veg") , 0.12 )
# equation parameters
circuit.addParameter(Name("complex"), "myEq")
# netlist :
netlist = circuit.createNetlist()
# instances
# nmos1
inst_nmos1 = netlist.addDevice("nmos1", "Transistor", 1, "NMOS", True)
inst_nmos1.addConnector("G")
inst_nmos1.addConnector("S")
inst_nmos1.addConnector("D")
tr_nmos1 = inst_nmos1.addTransistor("m1")
tr_nmos1.gate = "G" # the name of the connector of inst_nmos1
tr_nmos1.source = "S"
tr_nmos1.drain = "D"
tr_nmos1.bulk = "S"
# pmos1
inst_pmos1 = netlist.addDevice("pmos1", "Transistor", 2, "PMOS", True)
inst_pmos1.addConnector("G")
inst_pmos1.addConnector("S")
inst_pmos1.addConnector("D")
tr_pmos1 = inst_pmos1.addTransistor("m1")
tr_pmos1.gate = "G" # the name of the connector of inst_pmos1
tr_pmos1.source = "S"
tr_pmos1.drain = "D"
tr_pmos1.bulk = "S"
# nets
_vdd = netlist.addNet("vdd", "power" , True)
_vss = netlist.addNet("vss", "ground" , True)
_in = netlist.addNet("in" , "logical", True)
_out = netlist.addNet("out", "logical", True)
_vdd.connectTo("pmos1", "S")
_vss.connectTo("nmos1", "S")
_in.connectTo ("nmos1", "G")
_in.connectTo ("pmos1", "G")
_out.connectTo("nmos1", "D")
_out.connectTo("pmos1", "D")
# schematic
schematic = circuit.createSchematic()
schematic.addInstance("nmos1", 2490, 2600, "ID")
schematic.addInstance("pmos1", 2490, 2300, "ID")
_vdd.addPort("inV" , 0, 2490, 2100, "ID")
_vss.addPort("inV" , 0, 2490, 2800, "MY")
_in.addPort ("inH" , 0, 2190, 2500, "ID")
_out.addPort("outH", 0, 2600, 2500, "ID")
wireVdd = _vdd.addWire()
wireVdd.setStartPoint("pmos1", "S")
wireVdd.setEndPoint(0)
wireVss = _vss.addWire()
wireVss.setStartPoint("nmos1", "S")
wireVss.setEndPoint(0)
wireIn0 = _in.addWire()
wireIn1 = _in.addWire()
wireIn0.setStartPoint("pmos1", "G")
wireIn0.setEndPoint ("nmos1", "G")
wireIn1.setStartPoint(0)
wireIn1.setEndPoint ("pmos1", "G")
wireOut0 = _out.addWire()
wireOut1 = _out.addWire()
wireOut0.setStartPoint("pmos1", "D")
wireOut0.setEndPoint ("nmos1", "D")
wireOut1.setStartPoint("nmos1", "D")
wireOut1.setEndPoint (0)
# sizing
sizing = circuit.createSizing()
op_pmos1 = sizing.addOperator("pmos1", "OPVG(Veg)" , "BSIM3V3")
op_pmos1.addConstraint("Temp", "design", "temp")
op_pmos1.addConstraint("Ids" , "design", "Ids" )
op_pmos1.addConstraint("L" , "design", "L" )
op_pmos1.addConstraint("Veg" , "design", "Veg" )
op_pmos1.addConstraint("Vd" , "design", "Vdd", 0.5)
op_pmos1.addConstraint("Vs" , "design", "Vdd" )
op_nmos1 = sizing.addOperator("nmos1", "OPW(Vg,Vs)", "BSIM3V3")
op_nmos1.addConstraint("Temp", "design", "temp")
op_nmos1.addConstraint("Ids" , "design", "Ids" )
op_nmos1.addConstraint("L" , "design", "L" )
op_nmos1.addConstraint("Vs" , "design", "Vdd" )
op_nmos1.addConstraint("Vg" , "pmos1" , "Vg" )
op_nmos1.addConstraint("Vd" , "pmos1" , "Vd" )
op_nmos1.addConstraint("another", "myEq", -2.5 )
# layout
layout = circuit.createLayout()
layout.addInstance("pmos1", "Common transistor")
layout.addInstance("nmos1", "Rotate transistor")
# create hbtree
g1 = Group("g1")
g1.align = Group.Align.VERTICAL
b1 = Bloc("nmos1", Node.Position.NONE, g1)
g1.rootNode = b1
b2 = Bloc("pmos1", Node.Position.TOP, b1)
b1.top = b2
layout.hbTreeRoot = g1
circuit.writeToFile("./myInverter.xml")

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vlsisapd/examples/openChams/python/parseOpenChams.py
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@ -1,120 +0,0 @@
import sys
from OPENCHAMS import *
def printHBTree(node, indent):
if node == None:
return
for i in range(indent):
print " |",
if isinstance(node, Bloc):
print " bloc:", node.getName(), "-", node.getPosition()
printHBTree(node.top , indent+1)
printHBTree(node.right, indent+1)
return
if isinstance(node, Group):
print " group:", node.getName(), "-", node.getPosition(), "-", node.align, "-", node.isolated, "-", node.paired
printHBTree(node.rootNode, indent+1)
printHBTree(node.top , indent+1)
printHBTree(node.right , indent+1)
return
def printContents(circuit):
print circuit.name
# circuit parameters
print " + parameters"
for param in circuit.parameters.getValues():
print " | |", param.key, ":", param.value
for param in circuit.parameters.getEqValues():
print " | |", param.key, ":", param.value
# netlist
print " + netlist"
# instances
print " | + instances"
for instance in circuit.netlist.getInstances():
if isinstance(instance, Device):
print " | | +", instance.name, ":", instance.model, instance.order, instance.mosType, instance.sourceBulkConnected
else:
print " | | +", instance.name, ":", instance.model, instance.order
print " | | | + connectors"
for conn in instance.getConnectors():
print " | | | |", conn.key, ":", conn.value.name
if isinstance(instance, Device):
print " | | | + transistors"
for tr in instance.getTransistors():
print " | | | | name:", tr.name, "- gate:", tr.gate, "- source:", tr.source, "- drain:", tr.drain, "- bulk:", tr.bulk
# nets
print " | + nets"
schematicNet = False
for net in circuit.netlist.getNets():
print " | | +", net.name, ":", net.type, net.external
print " | | | + connections"
for conn in net.getConnections():
print " | | | | %s.%s"%(conn.instanceName, conn.connectorName)
if not net.hasNoPorts() or not net.hasNoWires():
schematicNet = True
# schematic
if (circuit.schematic):
print " + schematic"
for instance in circuit.schematic.getInstances():
print " | + instance name:", instance.key, "- x:", instance.value.x, "- y:", instance.value.y, "- orientation:", instance.value.orientation
if schematicNet:
for net in circuit.netlist.getNets():
if net.hasNoPorts() and net.hasNoWires():
continue
print " | + net name:", net.name
for port in net.getPorts():
print " | | + port type:", port.type, "- idx:", port.index, "- x:", port.x, "- y:", port.y, "- orientation:", port.orientation
for wire in net.getWires():
if isinstance(wire.startPoint, InstancePoint):
print " | | + wire <" + wire.startPoint.name.getString() + "," + wire.startPoint.plug.getString() +">"
elif isinstance(wire.startPoint, PortPoint):
print " | | + wire <" + str(wire.startPoint.index) + ">"
else:
print " - - UNKNOWN START POINT"
for point in wire.getIntermediatePoints():
print " | | <" + str(point.x) + "," + str(point.y) + ">"
if isinstance(wire.endPoint, InstancePoint):
print " | | <" + wire.endPoint.name.getString() + "," + wire.endPoint.plug.getString() +">"
elif isinstance(wire.endPoint, PortPoint):
print " | | <" + str(wire.endPoint.index) + ">"
else:
print " - - UNKNOWN END POINT"
# sizing
if (circuit.sizing):
print " + sizing"
for op in circuit.sizing.getOperators():
print " | + instance name:", op.key, "- operator:", op.value.name, "- simulModel:", op.value.simulModel
for constraint in op.value.getConstraints():
print " | | + param:", constraint.key, "- ref:", constraint.value.ref, "- refParam:", constraint.value.refParam, "- factor:", constraint.value.factor
print " | + equations"
for eq in circuit.sizing.getEquations():
print " | |", eq.key, ":", eq.value
# layout
if (circuit.layout):
print " + layout"
for inst in circuit.layout.getInstances():
print " | | instance name:", inst.key, "- style:", inst.value
if circuit.layout.hbTreeRoot != None:
print " | + hbtree"
printHBTree(circuit.layout.hbTreeRoot, 2)
def usage():
print "usage:", sys.argv[0], "[filename]"
sys.exit(48)
def main():
if len(sys.argv) == 1:
filename = "./inverter.xml"
elif len(sys.argv) == 2:
filename = sys.argv[1]
else:
usage()
circuit = Circuit.readFromFile(filename)
printContents(circuit)
if __name__ == "__main__":
main()

11
vlsisapd/src/CMakeLists.txt
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@ -1,15 +1,8 @@
ADD_SUBDIRECTORY(utilities) ADD_SUBDIRECTORY(utilities)
ADD_SUBDIRECTORY(agds) ADD_SUBDIRECTORY(agds)
ADD_SUBDIRECTORY(cif) ADD_SUBDIRECTORY(cif)
IF(IS_DIRECTORY ${VLSISAPD_SOURCE_DIR}/src/openChams) ADD_SUBDIRECTORY(dtr)
ADD_SUBDIRECTORY(openChams) ADD_SUBDIRECTORY(spice)
ENDIF(IS_DIRECTORY ${VLSISAPD_SOURCE_DIR}/src/openChams)
IF(IS_DIRECTORY ${VLSISAPD_SOURCE_DIR}/src/dtr)
ADD_SUBDIRECTORY(dtr)
ENDIF(IS_DIRECTORY ${VLSISAPD_SOURCE_DIR}/src/dtr)
IF(IS_DIRECTORY ${VLSISAPD_SOURCE_DIR}/src/spice)
ADD_SUBDIRECTORY(spice)
ENDIF(IS_DIRECTORY ${VLSISAPD_SOURCE_DIR}/src/spice)
ADD_SUBDIRECTORY(bookshelf) ADD_SUBDIRECTORY(bookshelf)
ADD_SUBDIRECTORY(configuration) ADD_SUBDIRECTORY(configuration)
ADD_SUBDIRECTORY(liberty) ADD_SUBDIRECTORY(liberty)

1
vlsisapd/src/openChams/CMakeLists.txt
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ADD_SUBDIRECTORY(src)

70
vlsisapd/src/openChams/src/CMakeLists.txt
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@ -1,70 +0,0 @@
INCLUDE_DIRECTORIES( ${VLSISAPD_SOURCE_DIR}/src/openChams/src
${LIBXML2_INCLUDE_DIR}
${Boost_INCLUDE_DIRS}
${PYTHON_INCLUDE_PATH}
${HURRICANE_INCLUDE_DIR}
)
SET ( hpps vlsisapd/openChams/Circuit.h
vlsisapd/openChams/Netlist.h
vlsisapd/openChams/Instance.h
vlsisapd/openChams/Device.h
vlsisapd/openChams/Net.h
vlsisapd/openChams/Operator.h
vlsisapd/openChams/Parameters.h
vlsisapd/openChams/Schematic.h
vlsisapd/openChams/SimulModel.h
vlsisapd/openChams/Sizing.h
vlsisapd/openChams/Layout.h
vlsisapd/openChams/Node.h
vlsisapd/openChams/Transistor.h
vlsisapd/openChams/Port.h
vlsisapd/openChams/Wire.h
vlsisapd/openChams/OpenChamsException.h
vlsisapd/openChams/Equation.h
vlsisapd/openChams/HighLevelCstr.h
vlsisapd/openChams/NRCCstr.h
vlsisapd/openChams/DDP.h
vlsisapd/openChams/DesignerCstrOC.h
vlsisapd/openChams/SlicingTree.h
)
SET ( cpps Circuit.cpp
Netlist.cpp
Instance.cpp
Device.cpp
Net.cpp
Operator.cpp
Parameters.cpp
Schematic.cpp
SimulModel.cpp
Sizing.cpp
Layout.cpp
Node.cpp
Transistor.cpp
Wire.cpp
Equation.cpp
HighLevelCstr.cpp
NRCCstr.cpp
DDP.cpp
DesignerCstrOC.cpp
SlicingTree.cpp
)
SET ( pycpps PyOpenChams.cpp
)
ADD_LIBRARY(openChams ${cpps})
TARGET_LINK_LIBRARIES(openChams ${LIBXML2_LIBRARIES})
SET_TARGET_PROPERTIES(openChams PROPERTIES VERSION 1.0 SOVERSION 1)
INSTALL(TARGETS openChams DESTINATION lib${LIB_SUFFIX} )
IF(Boost_FOUND)
ADD_LIBRARY(pyOPENCHAMS MODULE ${pycpps})
SET_TARGET_PROPERTIES(pyOPENCHAMS PROPERTIES
OUTPUT_NAME "OPENCHAMS"
PREFIX ""
)
TARGET_LINK_LIBRARIES(pyOPENCHAMS openChams ${LIBXML2_LIBRARIES} ${Boost_LIBRARIES} ${PYTHON_LIBRARIES})
INSTALL(TARGETS pyOPENCHAMS DESTINATION ${PYTHON_SITE_PACKAGES})
ENDIF(Boost_FOUND)
INSTALL(FILES ${hpps} DESTINATION include/vlsisapd/openChams)

1827
vlsisapd/src/openChams/src/Circuit.cpp
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32
vlsisapd/src/openChams/src/DDP.cpp
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/*
* DDP.cpp
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2010 UPMC / LIP6. All rights reserved.
*
*/
#include <string>
#include <iostream>
using namespace std;
#include "vlsisapd/openChams/DDP.h"
namespace OpenChams {
DDP::DDP()
: Equation()
{}
// This function prints all equations
void DDP::printEquations() {
map<int, string>::iterator it;
cerr << "Printing equations of a DDP : " << endl;
for(it=_equations.begin(); it!=_equations.end(); ++it) {
cerr << (*it).first << "\t" << (*it).second << endl;
}
}
} // namespace

31
vlsisapd/src/openChams/src/DesignerCstrOC.cpp
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@ -1,31 +0,0 @@
/*
* DesignerCstrOC.cpp
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2010 UPMC / LIP6. All rights reserved.
*
*/
#include <string>
#include <iostream>
using namespace std;
#include "vlsisapd/openChams/DesignerCstrOC.h"
namespace OpenChams {
DesignerCstrOC::DesignerCstrOC()
: Equation()
{}
// This function prints all equations
void DesignerCstrOC::printEquations() {
map<int, string>::iterator it;
cerr << "Printing equations of a DesignerCstrOC : " << endl;
for(it=_equations.begin(); it!=_equations.end(); ++it) {
cerr << (*it).first << "\t" << (*it).second << endl;
}
}
} // namespace

58
vlsisapd/src/openChams/src/Device.cpp
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@ -1,58 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Device.cpp" |
// +-----------------------------------------------------------------+
#include <iostream>
using namespace std;
#include "vlsisapd/openChams/Device.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Transistor.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Device::Device ( const string& name
, const string& model
, unsigned order
, const string& mosType
, bool sourceBulkConnected
, Netlist* netlist )
: Instance (name,model,order,netlist)
, _mosType (mosType)
, _sourceBulkConnected(sourceBulkConnected)
, _trans ()
{ }
Device::~Device ()
{ }
Transistor* Device::addTransistor ( const string& name )
{
Transistor* tr = new Transistor(name, this);
if (!tr)
throw OpenChamsException("[ERROR] Cannot create transistor.");
_trans.push_back(tr);
return tr;
}
} // OpenChams namespace

25
vlsisapd/src/openChams/src/Equation.cpp
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@ -1,25 +0,0 @@
/*
* Equation.cpp
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2010 UPMC / LIP6. All rights reserved.
*
*/
#include <string>
using namespace std;
#include "vlsisapd/openChams/Equation.h"
namespace OpenChams {
Equation::Equation()
: _equations()
// , _paramsInEquation()
{}
void Equation::addEquation(std::string eq) {
_equations[_equations.size()] = eq;
}
} // namespace

31
vlsisapd/src/openChams/src/HighLevelCstr.cpp
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@ -1,31 +0,0 @@
/*
* HighLevelCstr.cpp
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2010 UPMC / LIP6. All rights reserved.
*
*/
#include <string>
#include <iostream>
using namespace std;
#include "vlsisapd/openChams/HighLevelCstr.h"
namespace OpenChams {
HighLevelCstr::HighLevelCstr()
: Equation()
{}
// This function prints all equations
void HighLevelCstr::printEquations() {
map<int, string>::iterator it;
cerr << "Printing equations of a HighLevelCstr : " << endl;
for(it=_equations.begin(); it!=_equations.end(); ++it) {
cerr << (*it).first << "\t" << (*it).second << endl;
}
}
} // namespace

86
vlsisapd/src/openChams/src/Instance.cpp
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@ -1,86 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Instance.cpp" |
// +-----------------------------------------------------------------+
#include <iostream>
using namespace std;
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Instance::Instance(const string& name, const string& model, unsigned order, Netlist* netlist)
: _name(name)
, _model(model)
, _order(order)
, _netlist(netlist)
, _params()
, _netMap()
{ }
Instance::~Instance ()
{ }
void Instance::addConnector(const string& name)
{
// si name n'est pas déjà présent dans la map on ajoute name, NULL (pas de net)
map<string, Net*>::iterator it = _netMap.find(name);
if (it == _netMap.end()) {
_netMap[name] = NULL;
}
else {
string error("[ERROR] The same instance cannot have several connectors with same name (");
error += name;
error += ").";
throw OpenChamsException(error);
}
}
void Instance::connect(const string& connectorName, const string& netName)
{
// si connectorName n'est pas déjà présent dans la map :
// on cherche le net associé a netName dans la netlist (getNet(const string&))
// on ajoute cName, net a la map
map<string, Net*>::iterator it = _netMap.find(connectorName);
if (it != _netMap.end()) {
Net* net = _netlist->getNet(netName);
if (!net) {
string error("[ERROR] While connecting instance : net (");
error += netName;
error += ") does not exist.";
throw OpenChamsException(error);
}
else
_netMap[connectorName] = net;
}
else {
string error("[ERROR] While connecting instance : connector (");
error += connectorName;
error += ") does not exist.";
throw OpenChamsException(error);
}
}
} // OpenChams namespace.

47
vlsisapd/src/openChams/src/Layout.cpp
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@ -1,47 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2008-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Layout.cpp" |
// +-----------------------------------------------------------------+
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/Circuit.h"
#include "vlsisapd/openChams/OpenChamsException.h"
using namespace std;
namespace OpenChams {
Layout::Layout ( Circuit* circuit )
: _circuit (circuit)
, _hbTreeRoot(NULL)
, _instances ()
{ }
void Layout::addInstance ( const string& name, const string& style )
{
map<std::string, std::string>::iterator it = _instances.find(name);
if (it != _instances.end()) {
string error("[ERROR] Cannot set several instances with the same name in 'layout' (");
error += name;
error += ").";
throw OpenChamsException(error);
}
_instances[name] = style;
}
} // OpenChams namespace.

33
vlsisapd/src/openChams/src/NRCCstr.cpp
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@ -1,33 +0,0 @@
/*
* NRCCstr.cpp
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2010 UPMC / LIP6. All rights reserved.
*
*/
#include <string>
#include <iostream>
using namespace std;
#include "vlsisapd/openChams/NRCCstr.h"
namespace OpenChams {
NRCCstr::NRCCstr(string controlVoltage)
: Equation()
, _controlVoltage(controlVoltage)
{}
// This function prints all equations
void NRCCstr::printEquations() {
map<int, string>::iterator it;
cerr << "Printing equations of a NRCCstr : " << endl;
cerr << "Control voltage = " << _controlVoltage << endl;
for(it=_equations.begin(); it!=_equations.end(); ++it) {
cerr << (*it).first << "\t" << (*it).second << endl;
}
}
} // namespace

84
vlsisapd/src/openChams/src/Net.cpp
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@ -1,84 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Net.cpp" |
// +-----------------------------------------------------------------+
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
using namespace std;
namespace OpenChams {
Net::Net(const std::string& netName, const std::string& typeName, bool isExternal, Netlist* netlist)
: _name (netName)
, _typeName (typeName)
, _isExternal (isExternal)
, _netlist (netlist)
, _connections()
, _ports ()
, _wires ()
{ }
void Net::connectTo(const std::string& instanceName, const std::string& connectorName)
{
_connections.push_back(new Net::Connection(instanceName, connectorName));
Instance* inst = _netlist->getInstance(instanceName);
if (!inst) {
string error ("[ERROR] While connecting net ");
error += _name;
error += " to instance ";
error += instanceName;
error += ": instance does not exist in netlist !";
throw OpenChamsException(error);
} else {
inst->connect(connectorName, _name);
}
}
Port* Net::addPort(const std::string& type, unsigned idx, double x, double y, const std::string& orient)
{
while (_ports.size() <= idx)
_ports.push_back(NULL);
if (_ports[idx])
throw OpenChamsException("[ERROR] Net::addPort: cannot add port since another one with the same id already exists.");
_ports[idx] = new Port(type, idx, x, y, orient);
return _ports[idx];
}
Wire* Net::addWire() {
Wire* w = new Wire();
_wires.push_back(w);
return w;
}
Net::Connection::Connection(const std::string& instanceName, const std::string& connectorName)
: _instanceName (instanceName)
, _connectorName(connectorName)
{ }
} // OpenChams namespace.

118
vlsisapd/src/openChams/src/Netlist.cpp
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@ -1,118 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Netlist.cpp" |
// +-----------------------------------------------------------------+
#include <iostream>
#include <algorithm>
using namespace std;
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Device.h"
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/Circuit.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Netlist::Netlist(Circuit* circuit)
: _circuit(circuit)
{ }
Instance* Netlist::addInstance(const std::string& name, const std::string& model, unsigned order)
{
for (vector<Instance*>::iterator it = _instances.begin() ; it != _instances.end() ; ++it) {
if ((*it)->getName() == name) {
string error("[ERROR] Cannot define two instances with the same name in netlist (");
error += name;
error += ").";
throw OpenChamsException(error);
}
}
Instance* inst = new Instance(name, model, order, this);
if (!inst)
throw OpenChamsException("[ERROR] Cannot create instance.");
_instances.push_back(inst);
return inst;
}
Device* Netlist::addDevice(const std::string& name, const std::string& model, unsigned order, const std::string& mosType, bool sourceBulkConnected)
{
for (vector<Instance*>::iterator it = _instances.begin() ; it != _instances.end() ; ++it) {
if ((*it)->getName() == name) {
string error("[ERROR] Cannot define two instances with the same name in netlist (");
error += name;
error += ").";
throw OpenChamsException(error);
}
}
Device* dev = new Device(name, model, order, mosType, sourceBulkConnected, this);
if (!dev)
throw OpenChamsException("[ERROR] Cannot create device.");
_instances.push_back(dev);
return dev;
}
Net* Netlist::addNet(const std::string& name, const std::string& type, bool external)
{
for (vector<Net*>::iterator it = _nets.begin() ; it != _nets.end() ; ++it ) {
if ((*it)->getName() == name) {
string error("[ERROR] Cannot define two nets with the same name in netlist (");
error += name;
error += ").";
throw OpenChamsException(error);
}
}
Net* net = new Net(name, type, external, this);
if (!net)
throw OpenChamsException("[ERROR] Cannot create net.");
_nets.push_back(net);
return net;
}
Instance* Netlist::getInstance(const std::string& instanceName)
{
for (size_t i = 0 ; i < _instances.size() ; ++i) {
if (_instances[i]->getName() == instanceName) {
return _instances[i];
}
}
return NULL;
}
Net* Netlist::getNet(const std::string& netName) {
for (size_t i = 0; i < _nets.size(); ++i) {
if (_nets[i]->getName() == netName) {
return _nets[i];
}
}
return NULL;
}
} // OpenChams namespace.

47
vlsisapd/src/openChams/src/Node.cpp
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@ -1,47 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2011-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Node.cpp" |
// +-----------------------------------------------------------------+
#include "vlsisapd/openChams/Node.h"
using namespace std;
namespace OpenChams {
Node::Node(const string& nodeName, Position pos, Node* parent)
: _name (nodeName)
, _position(pos)
, _parent (parent)
, _right (NULL)
, _top (NULL)
{ }
Bloc::Bloc(const string& blocName, Position pos, Node* parent)
: Node(blocName,pos,parent)
{ }
Group::Group(const string& groupName, Position pos, Node* parent)
: Node(groupName,pos,parent)
, _isolated(false)
, _paired(false)
, _align(Group::NONE)
{ }
} // OpenChams namespace.

76
vlsisapd/src/openChams/src/Operator.cpp
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@ -1,76 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Operator.cpp" |
// +-----------------------------------------------------------------+
#include <string>
using namespace std;
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Operator::Operator(const string& operatorName, const string& simulModel)
: _name (operatorName)
, _simulModel(simulModel)
{ }
void Operator::addConstraint(const string& paramName, const string& ref, const string& refParam)
{ addConstraint(paramName, ref, refParam, 1.0); }
void Operator::addConstraint(const string& paramName, const string& ref, const string& refParam, double factor)
{
map<string, Constraint*>::iterator it = _constraints.find(paramName);
if (it != _constraints.end()) {
string error("[ERROR] Cannot set two constraints for the same parameter (");
error += paramName;
error += ").";
throw OpenChamsException(error);
}
_constraints[paramName] = new Operator::Constraint(ref, refParam, factor);
}
void Operator::addConstraint(const string& paramName, const string& refEquation)
{ addConstraint(paramName, refEquation, 1.0); }
void Operator::addConstraint(const string& paramName, const string& refEquation, double factor)
{
map<string, Constraint*>::iterator it = _constraints.find(paramName);
if (it != _constraints.end()) {
string error("[ERROR] Cannot set two constraints for the same parameter (");
error += paramName;
error += ").";
throw OpenChamsException(error);
}
_constraints[paramName] = new Operator::Constraint("", refEquation, factor);
}
Operator::Constraint::Constraint(const string& ref, const string& refParam, double factor)
: _ref (ref)
, _refParam(refParam)
, _factor (factor)
{ }
} // OpenChams namespace.

53
vlsisapd/src/openChams/src/Parameters.cpp
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@ -1,53 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2009-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Parameters.cpp" |
// +-----------------------------------------------------------------+
#include <iostream>
using namespace std;
#include "vlsisapd/openChams/Parameters.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
void Parameters::addParameter ( const string& name, const string& value )
{
map<string,string>::iterator it = _params.find(name);
if ( it != _params.end() ) {
string error("[ERROR] Cannot addParameter ");
error += name;
error += " because it already exists !";
throw OpenChamsException(error);
}
_params[name] = value;
}
const string& Parameters::getValue ( const string& name )
{
map<string,string>::iterator it = _params.find(name);
if (it == _params.end()) {
string error("[ERROR] No parameters named ");
error += name;
throw OpenChamsException(error);
}
return (*it).second;
}
} // OpenChams namespace.

385
vlsisapd/src/openChams/src/PyOpenChams.cpp
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#include <boost/python.hpp>
#include <boost/python/suite/indexing/vector_indexing_suite.hpp>
using namespace boost::python;
#include "vlsisapd/openChams/Parameters.h"
#include "vlsisapd/openChams/Transistor.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Device.h"
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Schematic.h"
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/SimulModel.h"
#include "vlsisapd/openChams/Sizing.h"
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/Node.h"
#include "vlsisapd/openChams/Circuit.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
#include "vlsisapd/openChams/PySTLMapWrapper.h"
using namespace std;
namespace OpenChams {
void translator(OpenChamsException const& e) {
PyErr_SetString(PyExc_UserWarning, e.what());
}
BOOST_PYTHON_MODULE(OPENCHAMS) {
// map wrapping for OpenChams::Parameters
STL_MAP_WRAPPING(std::string, std::string, "ValuesMap")
// class OpenChams::Parameters
class_<Parameters>("Parameters", init<>())
// accessors
.def("getValue" , &Parameters::getValue, return_value_policy<copy_const_reference>())
.def("isEmpty" , &Parameters::isEmpty )
// modifiers
.def("addParameter", static_cast<void(Parameters::*)(const std::string&, const std::string&)>(&Parameters::addParameter))
// stl containers
.def("getValues" , &Parameters::getValues , return_value_policy<copy_const_reference>())
;
{ //this scope is used to define Base as a subenum of SimulModel
// class OpenChams::SimulModel
scope simMod = class_<SimulModel>("SimulModel", init<unsigned, SimulModel::Base, SimulModel::Version, std::string>())
// properties
.add_property("id" , &SimulModel::getId )
.add_property("base" , &SimulModel::getBase )
.add_property("version" , &SimulModel::getVersion )
.add_property("filePath", &SimulModel::getFilePath)
;
enum_<SimulModel::Base>("Base")
.value("BSIM3V3", SimulModel::BSIM3V3)
.value("BSIM4" , SimulModel::BSIM4 )
.value("PSP" , SimulModel::PSP )
;
enum_<SimulModel::Version>("Version")
.value("UNDEFINED", SimulModel::UNDEFINED)
.value("SVT" , SimulModel::SVT )
.value("HVT" , SimulModel::HVT )
.value("LVT" , SimulModel::LVT )
;
}
// class OpenChams::Transistor
class_<Transistor, Transistor*>("Transistor", init<const std::string&, Instance*>())
// properties
.add_property("name" , make_function(&Transistor::getName ,return_value_policy<copy_const_reference>()), &Transistor::setName )
.add_property("gate" , make_function(&Transistor::getGate ,return_value_policy<copy_const_reference>()), &Transistor::setGate )
.add_property("source" , make_function(&Transistor::getSource,return_value_policy<copy_const_reference>()), &Transistor::setSource)
.add_property("drain" , make_function(&Transistor::getDrain ,return_value_policy<copy_const_reference>()), &Transistor::setDrain )
.add_property("bulk" , make_function(&Transistor::getBulk ,return_value_policy<copy_const_reference>()), &Transistor::setBulk )
.add_property("parameters", &Transistor::getParameters ) // no setter => params will be readonly
// modifiers
.def("addParameter", static_cast<void(Transistor::*)(const std::string&, const char*)>(&Transistor::addParameter))
.def("addParameter", static_cast<void(Transistor::*)(const std::string&, const std::string&)>(&Transistor::addParameter))
;
// map wrapping and vector_indexing for OpenChams::Instance
STL_MAP_WRAPPING_PTR(std::string, Net*, "ConnectorsMap")
// class OpenChams::Instance
class_<Instance, Instance*>("Instance", init<const std::string&, const std::string&, unsigned, Netlist*>())
// properties
.add_property("name" , make_function(&Instance::getName ,return_value_policy<copy_const_reference>()))
.add_property("model" , make_function(&Instance::getModel,return_value_policy<copy_const_reference>()))
.add_property("order" , &Instance::getOrder )
.add_property("parameters" , &Instance::getParameters )
.add_property("netlist" , make_function(&Instance::getNetlist ,return_value_policy<reference_existing_object>())) //make_function since we need to specify a return value policy
// accessors
.def("hasNoConnectors" , &Instance::hasNoConnectors )
// modifiers
.def("addConnector" , &Instance::addConnector )
.def("connect" , &Instance::connect )
.def("addParameter" , static_cast<void(Transistor::*)(const std::string&, const char*)>(&Transistor::addParameter))
.def("addParameter" , static_cast<void(Transistor::*)(const std::string&, const std::string&)>(&Transistor::addParameter))
// stl containers
.def("getConnectors" , &Instance::getConnectors , return_internal_reference<>())
;
// vector_indexing for OpenChams::Device
class_<std::vector<Transistor*> >("TransistorsVector")
.def(vector_indexing_suite<std::vector<Transistor*>, true>())
;
// class OpenChams::Device
class_<Device, bases<Instance> >("Device", init<const std::string&, const std::string&, unsigned, const std::string&, bool, Netlist*>())
// properties
.add_property("mosType" , make_function(&Device::getMosType,return_value_policy<copy_const_reference>()) )
.add_property("sourceBulkConnected", &Device::isSourceBulkConnected)
// accessors
.def("hasNoTransistors", &Device::hasNoTransistors)
// modifiers
.def("addTransistor", &Device::addTransistor, return_value_policy<reference_existing_object>())
// stl containers
.def("getTransistors", &Device::getTransistors, return_internal_reference<>())
;
// class OpenChams::Port
class_<Port, Port*>("Port", init<const std::string&, unsigned, double, double, const std::string&>())
// properties
.add_property("type" , make_function(&Port::getType,return_value_policy<copy_const_reference>()))
.add_property("index" , &Port::getIndex )
.add_property("x" , &Port::getX )
.add_property("y" , &Port::getY )
.add_property("orientation", make_function(&Port::getOrientation,return_value_policy<copy_const_reference>()))
;
// class OpenChams::WirePoint
class_<WirePoint, WirePoint*>("WirePoint", init<>())
;
// class OpenChams::InstancePoint
class_<InstancePoint, bases<WirePoint> >("InstancePoint", init<const std::string&, const std::string&>())
// properties
.add_property("name", make_function(&InstancePoint::getName, return_value_policy<copy_const_reference>()))
.add_property("plug", make_function(&InstancePoint::getPlug, return_value_policy<copy_const_reference>()))
;
// class OpenChams::PortPoint
class_<PortPoint, bases<WirePoint> >("PortPoint", init<unsigned>())
// properties
.add_property("index", &PortPoint::getIndex)
;
// class OpenChams::IntermediatePoint
class_<IntermediatePoint, bases<WirePoint> >("IntermediatePoint", init<double, double>())
// properties
.add_property("x", &IntermediatePoint::getX)
.add_property("y", &IntermediatePoint::getY)
;
// vector_indexing for OpenChams::Wire
class_<std::vector<IntermediatePoint*> >("IntermediatePointsVector")
.def(vector_indexing_suite<std::vector<IntermediatePoint*>, true>())
;
// class OpenChams::Wire
class_<Wire, Wire*>("Wire", init<>())
// properties
.add_property("startPoint", make_function(&Wire::getStartPoint, return_value_policy<reference_existing_object>()))
.add_property("endPoint" , make_function(&Wire::getEndPoint , return_value_policy<reference_existing_object>()))
// accessors
.def("hasNoIntermediatePoints", &Wire::hasNoIntermediatePoints)
// modifiers
.def("setStartPoint" , static_cast<void(Wire::*)(const std::string&, const std::string&)>(&Wire::setStartPoint))
.def("setStartPoint" , static_cast<void(Wire::*)(unsigned )>(&Wire::setStartPoint))
.def("setEndPoint" , static_cast<void(Wire::*)(const std::string&, const std::string&)>(&Wire::setEndPoint))
.def("setEndPoint" , static_cast<void(Wire::*)(unsigned )>(&Wire::setEndPoint))
.def("addIntermediatePoint", &Wire::addIntermediatePoint)
// stl containers
.def("getIntermediatePoints" , &Wire::getIntermediatePoints, return_internal_reference<>())
;
// vector_indexing for OpenChams::Net
class_<std::vector<Net::Connection*> >("ConnectionsVector")
.def(vector_indexing_suite<std::vector<Net::Connection*>, true>())
;
class_<std::vector<Port*> >("PortsVector")
.def(vector_indexing_suite<std::vector<Port*>, true>())
;
class_<std::vector<Wire*> >("WiresVector")
.def(vector_indexing_suite<std::vector<Wire*>, true>())
;
{ //this scope is used to define Connection as a subclass of Net
// class OpenChams::Net
scope netScope = class_<Net, Net*>("Net", init<const std::string&, const std::string&, bool, Netlist*>())
// properties
.add_property("name" , make_function(&Net::getName ,return_value_policy<copy_const_reference>()))
.add_property("type" , make_function(&Net::getType ,return_value_policy<copy_const_reference>()))
.add_property("external", &Net::isExternal)
.add_property("netlist" , make_function(&Net::getNetlist, return_value_policy<reference_existing_object>()))
// accessors
.def("hasNoConnections", &Net::hasNoConnections)
.def("hasNoPorts" , &Net::hasNoPorts )
.def("hasNoWires" , &Net::hasNoWires )
// modifiers
.def("connectTo" , &Net::connectTo )
.def("addPort" , &Net::addPort, return_value_policy<reference_existing_object>())
.def("addWire" , &Net::addWire, return_value_policy<reference_existing_object>())
// stl containers
.def("getConnections", &Net::getConnections, return_internal_reference<>())
.def("getPorts" , &Net::getPorts , return_internal_reference<>())
.def("getWires" , &Net::getWires , return_internal_reference<>())
;
// class OpenChams::Net::Connection
class_<Net::Connection, Net::Connection*>("Connection", init<const std::string&, const std::string&>())
.add_property("instanceName" , make_function(&Net::Connection::getInstanceName ,return_value_policy<copy_const_reference>()))
.add_property("connectorName", make_function(&Net::Connection::getConnectorName,return_value_policy<copy_const_reference>()))
;
} // end netScope
// vector_indexing for OpenChams::Netlist
class_<std::vector<Instance*> >("InstancesVector")
.def(vector_indexing_suite<std::vector<Instance*>, true>())
;
class_<std::vector<Net*> >("NetsVector")
.def(vector_indexing_suite<std::vector<Net*>, true>())
;
// class OpenChams::Netlist
class_<Netlist, Netlist*>("Netlist", init<Circuit*>())
// accessors
.def("hasNoInstances", &Netlist::hasNoInstances)
.def("hasNoNets" , &Netlist::hasNoNets )
.def("getInstance" , make_function(&Netlist::getInstance , return_value_policy<reference_existing_object>()))
.def("getNet" , make_function(&Netlist::getNet , return_value_policy<reference_existing_object>()))
// modifiers
.def("addInstance" , &Netlist::addInstance, return_value_policy<reference_existing_object>())
.def("addDevice" , &Netlist::addDevice , return_value_policy<reference_existing_object>())
.def("addNet" , &Netlist::addNet , return_value_policy<reference_existing_object>())
// stl containers
.def("getInstances" , &Netlist::getInstances, return_internal_reference<>())
.def("getNets" , &Netlist::getNets , return_internal_reference<>())
;
// map wrapping for OpenChams::Schematic
STL_MAP_WRAPPING_PTR(std::string, Schematic::Infos*, "SchematicInstancesMap")
{ // this scope is used to define Infos as a subclass of Schematic
// class OpenChams::Schematic
scope schematicScope = class_<Schematic, Schematic*>("Schematic", init<Circuit*>())
// accessors
.def("hasNoInstances", &Schematic::hasNoInstances)
// modifiers
.def("addInstance" , &Schematic::addInstance)
// stl containers
.def("getInstances" , &Schematic::getInstances, return_internal_reference<>())
;
// class OpenChams::Schematic::Infos
class_<Schematic::Infos, Schematic::Infos*>("Infos", init<double, double, const std::string&>())
.add_property("x" , &Schematic::Infos::getX )
.add_property("y" , &Schematic::Infos::getY )
.add_property("orientation", make_function(&Schematic::Infos::getOrientation,return_value_policy<copy_const_reference>()))
;
} // end schematicScope
// map wrapping for OpenChams::Operator
STL_MAP_WRAPPING_PTR(std::string, Operator::Constraint*, "ConstraintsMap")
{ // this scope is used to define Constraint as a subclass of Operator
// class OpenChams::Operator
scope operatorScope = class_<Operator, Operator*>("Operator", init<const std::string&, const std::string&>())
// properties
.add_property("name" , make_function(&Operator::getName , return_value_policy<copy_const_reference>()))
.add_property("simulModel", make_function(&Operator::getSimulModel, return_value_policy<copy_const_reference>()))
// accessors
.def("hasNoConstraints", &Operator::hasNoConstraints)
// modifiers
.def("addConstraint", static_cast<void(Operator::*)(const std::string&, const std::string& )>(&Operator::addConstraint))
.def("addConstraint", static_cast<void(Operator::*)(const std::string&, const std::string&, double )>(&Operator::addConstraint))
.def("addConstraint", static_cast<void(Operator::*)(const std::string&, const std::string&, const std::string& )>(&Operator::addConstraint))
.def("addConstraint", static_cast<void(Operator::*)(const std::string&, const std::string&, const std::string&, double)>(&Operator::addConstraint))
// stl containers
.def("getConstraints", &Operator::getConstraints, return_internal_reference<>())
;
// class OpenChams::Operator::Constraint
class_<Operator::Constraint, Operator::Constraint*>("Constraint", init<const std::string&, const std::string&, double>())
.add_property("ref" , make_function(&Operator::Constraint::getRef , return_value_policy<copy_const_reference>()))
.add_property("refParam", make_function(&Operator::Constraint::getRefParam, return_value_policy<copy_const_reference>()))
.add_property("factor" , &Operator::Constraint::getFactor )
;
} // end operatorScope
/*
// map wrapping for OpenChams::Sizing
STL_MAP_WRAPPING_PTR(std::string, Operator*, "OperatorsMap")
// class OpenChams::Sizing
class_<Sizing, Sizing*>("Sizing", init<Circuit*>())
// accessors
.def("hasNoEquations", &Sizing::hasNoEquations)
.def("hasNoOperators", &Sizing::hasNoOperators)
// modifiers
.def("addEquation", &Sizing::addEquation)
.def("addOperator", &Sizing::addOperator, return_value_policy<reference_existing_object>())
// stl containers
.def("getEquations", &Sizing::getEquations, return_internal_reference<>())
.def("getOperators", &Sizing::getOperators, return_internal_reference<>())
;
*/
// map wrapping for OpenChams::Layout
STL_MAP_WRAPPING(std::string, std::string, "LayoutInstancesMap")
// class OpenChams::Layout
class_<Layout, Layout*>("Layout", init<Circuit*>())
// properties
.add_property("hbTreeRoot", make_function(&Layout::getHBTreeRoot, return_value_policy<reference_existing_object>()), &Layout::setHBTreeRoot)
// accessors
.def("hasNoInstance", &Layout::hasNoInstance)
// modifiers
.def("addInstance", &Layout::addInstance)
// stl containers
.def("getInstances", &Layout::getInstances, return_internal_reference<>())
;
class_<Circuit, Circuit*>("Circuit", init<const std::string&, const std::string&>())
// properties
.add_property("name" , make_function(&Circuit::getName ,return_value_policy<copy_const_reference>()))
.add_property("techno" , make_function(&Circuit::getTechno ,return_value_policy<copy_const_reference>()))
.add_property("parameters" , &Circuit::getParameters )
.add_property("netlist" , make_function(&Circuit::getNetlist , return_value_policy<reference_existing_object>()))
.add_property("schematic" , make_function(&Circuit::getSchematic, return_value_policy<reference_existing_object>()))
.add_property("sizing" , make_function(&Circuit::getSizing , return_value_policy<reference_existing_object>()))
.add_property("layout" , make_function(&Circuit::getLayout , return_value_policy<reference_existing_object>()))
// accessors
.def("getValue", &Circuit::getValue, return_value_policy<copy_const_reference>() )
// modifiers
.def("createNetlist" , &Circuit::createNetlist , return_value_policy<reference_existing_object>())
.def("createSchematic", &Circuit::createSchematic, return_value_policy<reference_existing_object>())
.def("createSizing" , &Circuit::createSizing , return_value_policy<reference_existing_object>())
.def("createLayout" , &Circuit::createLayout , return_value_policy<reference_existing_object>())
.def("addParameter", static_cast<void(Circuit::*)(const std::string&, const char*)>(&Circuit::addParameter))
.def("addParameter", static_cast<void(Circuit::*)(const std::string&, const std::string&)>(&Circuit::addParameter))
// others
.def("readFromFile", &Circuit::readFromFile, return_value_policy<manage_new_object>())
.staticmethod("readFromFile")
.def("writeToFile" , &Circuit::writeToFile)
;
{ //this scope is used to define Position as a subenum of Node
// class OpenChams::Node
scope nod = class_<Node, Node*, boost::noncopyable>("Node", no_init)
// properties
.add_property("top" , make_function(&Node::getTop , return_value_policy<reference_existing_object>()), &Node::setTop )
.add_property("right", make_function(&Node::getRight, return_value_policy<reference_existing_object>()), &Node::setRight)
// accessors
.def("getName" , &Node::getName , return_value_policy<copy_const_reference>())
.def("getPosition", &Node::getPosition)
.def("getParent" , &Node::getParent , return_value_policy<reference_existing_object>())
.def("isRoot" , &Node::isRoot )
;
enum_<Node::Position>("Position")
.value("NONE" , Node::NONE )
.value("RIGHT", Node::RIGHT)
.value("TOP" , Node::TOP )
.export_values()
;
} // end of node scope
// class OpenChams::Bloc
class_<Bloc, bases<Node> >("Bloc", init<const std::string&, optional<Node::Position, Node*> >())
;
{ // this scope is used to define Align as a subenum of Group
// class OpenChams::Group
scope grou = class_<Group, bases<Node> >("Group", init<const std::string&, optional<Node::Position, Node*> >())
.add_property("rootNode", make_function(&Group::getRootNode, return_value_policy<reference_existing_object>()), &Group::setRootNode)
.add_property("isolated", &Group::isIsolated, &Group::setIsolated)
.add_property("paired" , &Group::isPaired , &Group::setPaired )
.add_property("align" , &Group::getAlign , &Group::setAlign )
;
enum_<Group::Align>("Align")
.value("NONE" , Group::NONE )
.value("VERTICAL" , Group::VERTICAL )
.value("HORIZONTAL", Group::HORIZONTAL)
;
} // end of group scope
// OpenChamsException translator
register_exception_translator<OpenChamsException>(translator)
;
}
} // OpenChams namespace.

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vlsisapd/src/openChams/src/Schematic.cpp
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// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC 2010-2018, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Schematic.cpp" |
// +-----------------------------------------------------------------+
#include "vlsisapd/openChams/Schematic.h"
#include "vlsisapd/openChams/OpenChamsException.h"
using namespace std;
namespace OpenChams {
Schematic::Schematic (Circuit* circuit )
: _circuit(circuit)
{ }
void Schematic::addInstance ( const string& instanceName
, double x
, double y
, const string& orient )
{
map<string, Schematic::Infos*>::iterator it = _instances.find(instanceName);
if (it != _instances.end()) {
string error("[ERROR] Cannot set same instance twice in 'schematic' (");
error += instanceName;
error += ").";
throw OpenChamsException(error);
}
_instances[instanceName] = new Schematic::Infos(x, y, orient);
}
Schematic::Infos::Infos(double x, double y, const string& orient)
: _x (x)
, _y (y)
, _orient(orient)
{}
} // OpenChams namespace.

20
vlsisapd/src/openChams/src/SimulModel.cpp
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/*
* SimulModel.cpp
* openChams
*
* Created by damien dupuis on 06/07/10.
* Copyright 2010 UPMC / LIP6. All rights reserved.
*
*/
#include "vlsisapd/openChams/SimulModel.h"
namespace OpenChams {
SimulModel::SimulModel(unsigned id, SimulModel::Base base, SimulModel::Version version, std::string filePath)
: _id(id)
, _base(base)
, _version(version)
, _filePath(filePath) {}
} // namespace

66
vlsisapd/src/openChams/src/Sizing.cpp
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// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Sizing.cpp" |
// +-----------------------------------------------------------------+
#include "vlsisapd/openChams/Sizing.h"
#include "vlsisapd/openChams/Circuit.h"
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/Equation.h"
#include "vlsisapd/openChams/OpenChamsException.h"
using namespace std;
namespace OpenChams {
Sizing::Sizing ( Circuit* circuit )
: _circuit(circuit)
{ }
Operator* Sizing::addOperator ( const string& instanceName
, const string& operatorName
, const string& simulModel )
{
map<string, Operator*>::iterator it = _operators.find(instanceName);
if (it != _operators.end()) {
string error("[ERROR] Cannot set same instance twice in 'sizing' (");
error += instanceName;
error += ").";
throw OpenChamsException(error);
}
Operator* op = new Operator(operatorName, simulModel);
_operators[instanceName] = op;
return op;
}
void Sizing::addEquation ( const string& equationName, Equation* equation)
{
map<string, Equation*>::iterator it = _equations.find(equationName);
if (it != _equations.end()) {
string error("[ERROR] Cannot set several equations with the same name in 'sizing' (");
error += equationName;
error += ").";
throw OpenChamsException(error);
}
_equations[equationName] = equation;
}
} // OpenChams namespace

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vlsisapd/src/openChams/src/SlicingTree.cpp
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71
vlsisapd/src/openChams/src/Transistor.cpp
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// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Transistor.cpp" |
// +-----------------------------------------------------------------+
#include <iostream>
using namespace std;
#include "vlsisapd/openChams/Transistor.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Transistor::Transistor(const std::string& name, Instance* instance)
: _name (name)
, _gate ("")
, _source ("")
, _drain ("")
, _bulk ("")
, _instance(instance)
{ }
void Transistor::setGate(const std::string& gate)
{ if (checkConnector(gate)) _gate = gate; }
void Transistor::setSource(const std::string& source)
{ if (checkConnector(source)) _source = source; }
void Transistor::setDrain(const std::string& drain)
{ if (checkConnector(drain)) _drain = drain; }
void Transistor::setBulk(const std::string& bulk)
{ if (checkConnector(bulk)) _bulk = bulk; }
bool Transistor::checkConnector(const std::string& name)
{
map<string, Net*>::const_iterator it = _instance->getConnectors().find(name);
if (it != _instance->getConnectors().end()) {// si le connecteur existe bien
return true;
} else {
string error("[ERROR] Instance ");
error += _instance->getName();
error += " has no connector named ";
error += name;
error += ".";
throw OpenChamsException(error);
}
}
} // OpenChams namespace.

76
vlsisapd/src/openChams/src/Wire.cpp
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@ -1,76 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2011-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Module : "./Wire.cpp" |
// +-----------------------------------------------------------------+
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
using namespace std;
namespace OpenChams {
void Wire::setStartPoint(const string& name, const string& plug)
{
if (_start)
throw OpenChamsException("[ERROR] Wire::setStartPoint: cannot set start point since it has already been set.");
_start = new InstancePoint(name, plug);
}
void Wire::setStartPoint(unsigned idx)
{
if (_start)
throw OpenChamsException("[ERROR] Wire::setStartPoint: cannot set start point since it has already been set.");
_start = new PortPoint(idx);
}
void Wire::setEndPoint(const string& name, const string& plug)
{
if (!_start)
throw OpenChamsException("[ERROR] Wire::setEndPoint: cannot set end point since start point has not been set.");
if (_end)
throw OpenChamsException("[ERROR] Wire::setEndPoint: cannot set end point since it has already been set.");
_end = new InstancePoint(name, plug);
}
void Wire::setEndPoint(unsigned idx)
{
if (!_start)
throw OpenChamsException("[ERROR] Wire::setEndPoint: cannot set end point since start point has not been set.");
if (_end)
throw OpenChamsException("[ERROR] Wire::setEndPoint: cannot set end point since it has already been set.");
_end = new PortPoint(idx);
}
void Wire::addIntermediatePoint(double x, double y)
{
if (!_start)
throw OpenChamsException("[ERROR] Wire::addIntermediatePoint: cannot add point since start point has not been set.");
if (_end)
throw OpenChamsException("[ERROR] Wire::addIntermediatePoint: cannot add point since end point has already been set.");
_inters.push_back(new IntermediatePoint(x, y));
}
} // OpenChams namespace.

195
vlsisapd/src/openChams/src/vlsisapd/openChams/Circuit.h
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@ -1,195 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2009-2018, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | Eric Lao |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Circuit.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_CIRCUIT_H__
#define __OPENCHAMS_CIRCUIT_H__
#include <vector>
#include <map>
#include <sstream>
#include <libxml/parser.h>
#include <libxml/tree.h>
#include "vlsisapd/openChams/Parameters.h"
#include "vlsisapd/openChams/SimulModel.h"
#include "vlsisapd/openChams/SlicingTree.h"
namespace OpenChams {
class Netlist;
class Instance;
class Device;
class Net;
class Schematic;
class Sizing;
class Transistor;
class Operator;
class Layout;
class Node;
class Circuit {
public:
Circuit ( const std::string&, const std::string& techno );
// Accessors.
inline const std::string& getName ();
inline const std::string& getTechno ();
inline const std::string& getValue ( const std::string& );
inline Netlist* getNetlist ();
inline Schematic* getSchematic ();
inline Sizing* getSizing ();
inline Layout* getLayout ();
inline void addParameter ( const std::string&, const char* );
inline void addParameter ( const std::string&, const std::string& );
inline Parameters getParameters ();
inline void addSubCircuitPath ( std::string );
inline std::vector<std::string>& getSubCircuitPaths ();
inline SlicingNode* getSlicingTree ();
// Mutators.
void addSimulModel ( unsigned
, SimulModel::Base
, SimulModel::Version
, std::string );
inline void setSizing ( Sizing* );
inline void setLayout ( Layout* );
Netlist* createNetlist ();
Schematic* createSchematic ();
Sizing* createSizing ();
Layout* createLayout ();
void setSlicingTree ( SlicingNode* slicingtree );
void driveHBTree ( std::ofstream&, Node*, unsigned );
void driveSlicingTree ( std::ofstream&, SlicingNode*, unsigned );
bool writeToFile ( std::string filePath );
static Circuit* readFromFile ( const std::string filePath );
private:
// Internal methods (XML parser).
std::string readParameter ( xmlNode*, const xmlChar*& );
std::string readParameterEq ( xmlNode*, std::string& );
std::string readConnector ( xmlNode* );
void readSubCircuitsPaths ( xmlNode* );
void readCircuitParameters ( xmlNode* );
void readSimulModels ( xmlNode* );
void readNetList ( xmlNode* );
void readInstances ( xmlNode*, Netlist* );
Instance* readInstance ( xmlNode*, Netlist* );
void readInstanceParameters ( xmlNode*, Instance* );
void readInstanceConnectors ( xmlNode*, Instance* );
void readInstanceTransistors ( xmlNode*, Device* );
void readTransistor ( xmlNode*, Device* );
void readTransistorConnection ( xmlNode*, Transistor* );
void readNets ( xmlNode*, Netlist* );
Net* readNet ( xmlNode*, Netlist* );
void readNetConnector ( xmlNode*, Net* );
void readSchematic ( xmlNode* );
void readInstanceSchematic ( xmlNode*, Schematic* );
void readNetSchematic ( xmlNode*, Circuit* );
void readPortSchematic ( xmlNode*, Net* );
void readWireSchematic ( xmlNode*, Net* );
void readSizing ( xmlNode* );
void readInstanceSizing ( xmlNode*, Sizing* );
void readConstraint ( xmlNode*, Operator* );
// Equation related XML methods.
void readEquations ( xmlNode*, Sizing* );
void readEquation_CircuitLevel ( xmlNode*, Sizing* );
void readEquation_NRC ( xmlNode*, Sizing* );
void readEquation_DDPs ( xmlNode*, Sizing* );
void readEquation_DesignerCstr ( xmlNode*, Sizing* );
// Layout related XML methods.
void readLayout ( xmlNode* );
void readInstanceLayout ( xmlNode*, Layout* );
void readHBTree ( xmlNode*, Layout* );
Node* readNodeOrBloc ( xmlNode*, Node* parent = NULL );
void setAbsolutePath ( const std::string filePath );
// Slicingtree related XML methods.
void readSlicingTree ( xmlNode* );
SlicingNode* readSlicingNode ( xmlNode* xnode, SlicingNode* slicingNode = NULL );
VSlicingNode* createVerticalSlicingNode ( xmlNode* xnode, SlicingNode* slicingNode = NULL );
HSlicingNode* createHorizontalSlicingNode ( xmlNode* xnode, SlicingNode* slicingNode = NULL );
DSlicingNode* createDeviceSlicingNode ( xmlNode* xnode, SlicingNode* slicingNode = NULL );
RSlicingNode* createRoutingSlicingNode ( xmlNode* xnode, SlicingNode* slicingNode = NULL );
void addChildren ( xmlNode*, HVSlicingNode* );
void setHVParameters ( xmlNode*, HVSlicingNode* );
void setHVSymmetries ( xmlNode*, HVSlicingNode* );
// Utilities methods.
void check_uppercase ( std::string& str, std::vector<std::string>& compares, std::string message );
void check_lowercase ( std::string& str, std::vector<std::string>& compares, std::string message );
private:
std::string _name;
std::string _absolutePath;
std::string _techno;
Parameters _params;
Netlist* _netlist;
Schematic* _schematic;
Sizing* _sizing;
Layout* _layout;
std::vector<std::string> _subCircuitsPaths;
std::map<unsigned, SimulModel*> _simulModels;
SlicingNode* _slicingtree;
};
inline const std::string& Circuit::getName () { return _name; }
inline const std::string& Circuit::getTechno () { return _techno; }
inline const std::string& Circuit::getValue (const std::string& name) { return _params.getValue(name); }
inline Netlist* Circuit::getNetlist () { return _netlist; }
inline Schematic* Circuit::getSchematic () { return _schematic; }
inline Sizing* Circuit::getSizing () { return _sizing; }
inline Layout* Circuit::getLayout () { return _layout; }
inline void Circuit::addParameter (const std::string& name, const char* value) { _params.addParameter(name, value); }
inline void Circuit::addParameter (const std::string& name, const std::string& value) { _params.addParameter(name, value); }
inline Parameters Circuit::getParameters () { return _params; }
inline void Circuit::addSubCircuitPath (std::string path) { _subCircuitsPaths.push_back(path); }
inline std::vector<std::string>& Circuit::getSubCircuitPaths () { return _subCircuitsPaths; }
inline SlicingNode* Circuit::getSlicingTree () { return _slicingtree; }
template<typename T>
inline std::string asString ( T value )
{ std::ostringstream output; output << value; return output.str(); }
std::string asStringBool ( bool );
std::string asStringDirection ( long );
template<typename T>
inline T stringAs ( const char* str )
{ T value; std::istringstream input(str); input >> value; return value; }
template<typename T>
inline T stringAs ( const xmlChar* str )
{ T value; std::istringstream input((const char*)str); input >> value; return value; }
template<typename T>
inline T stringAs ( const std::string& str )
{ return stringAs<T>(str.c_str()); }
bool stringAsBool ( const std::string& );
long stringAsDirection ( const std::string& );
} // namespace OpenChams.
#endif

24
vlsisapd/src/openChams/src/vlsisapd/openChams/DDP.h
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@ -1,24 +0,0 @@
/*
* DDP.h
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2008-2010 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_DDP_H__
#define __OPENCHAMS_DDP_H__
#include "vlsisapd/openChams/Equation.h"
namespace OpenChams {
class DDP : public Equation {
public:
DDP();
virtual void printEquations();
};
} // namespace
#endif

24
vlsisapd/src/openChams/src/vlsisapd/openChams/DesignerCstrOC.h
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@ -1,24 +0,0 @@
/*
* DesignerCstrOC.h
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2008-2010 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_DESIGNERCSTROC_H__
#define __OPENCHAMS_DESIGNERCSTROC_H__
#include "vlsisapd/openChams/Equation.h"
namespace OpenChams {
class DesignerCstrOC : public Equation {
public:
DesignerCstrOC();
virtual void printEquations();
};
} // namespace
#endif

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vlsisapd/src/openChams/src/vlsisapd/openChams/Device.h
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// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Instance.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_DEVICE_H__
#define __OPENCHAMS_DEVICE_H__
#include <map>
#include <vector>
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Parameters.h"
namespace OpenChams {
class Netlist;
class Transistor;
class Device : public Instance {
public:
Device ( const std::string& name
, const std::string& model
, unsigned order
, const std::string& mosType
, bool sourceBulkConnected
, Netlist* );
virtual ~Device ();
inline const std::string& getMosType ();
inline bool isSourceBulkConnected ();
// Pour parcourir les transistors
inline bool hasNoTransistors ();
inline const std::vector<Transistor*>& getTransistors ();
Transistor* addTransistor (const std::string&);
private:
std::string _mosType;
bool _sourceBulkConnected;
std::vector<Transistor*> _trans;
};
inline const std::string& Device::getMosType () { return _mosType; };
inline bool Device::isSourceBulkConnected() { return _sourceBulkConnected; };
inline bool Device::hasNoTransistors () { return (_trans.size() == 0)? true : false; };
inline const std::vector<Transistor*>& Device::getTransistors () { return _trans; };
} // namespace
#endif

34
vlsisapd/src/openChams/src/vlsisapd/openChams/Equation.h
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@ -1,34 +0,0 @@
/*
* Equation.h
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2008-2010 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_EQUATION_H__
#define __OPENCHAMS_EQUATION_H__
#include <vector>
#include <map>
//using namespace std;
namespace OpenChams {
class Equation {
public:
Equation();
void addEquation(std::string eq);
inline std::map<int, std::string>& getEquationStr();
virtual void printEquations() = 0;
protected:
std::map<int, std::string> _equations; // this map contains the equation(s)
// std::vector<std::string> _paramsInEquation; //
};
inline std::map<int, std::string>& Equation::getEquationStr() {return _equations;}
} // namespace
#endif

24
vlsisapd/src/openChams/src/vlsisapd/openChams/HighLevelCstr.h
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@ -1,24 +0,0 @@
/*
* HighLevelCstr.h
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2008-2010 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_HIGHLEVELCSTR_H__
#define __OPENCHAMS_HIGHLEVELCSTR_H__
#include "vlsisapd/openChams/Equation.h"
namespace OpenChams {
class HighLevelCstr : public Equation {
public:
HighLevelCstr();
virtual void printEquations();
};
} // namespace
#endif

76
vlsisapd/src/openChams/src/vlsisapd/openChams/Instance.h
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@ -1,76 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Instance.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_INSTANCE_H__
#define __OPENCHAMS_INSTANCE_H__
#include <map>
#include <vector>
#include <string>
#include "vlsisapd/openChams/Parameters.h"
namespace OpenChams {
class Netlist;
class Net;
class Instance {
public:
Instance (const std::string& name, const std::string& model, unsigned, Netlist*);
virtual ~Instance ();
void addConnector (const std::string&);
void connect (const std::string& connectorName, const std::string& netName);
inline void addParameter (const std::string&, const char* );
inline void addParameter (const std::string&, const std::string& );
inline const std::string& getName () const;
inline const std::string& getModel () const;
inline unsigned getOrder ();
inline Netlist* getNetlist ();
inline Parameters getParameters ();
inline bool hasNoConnectors ();
inline const std::map<std::string, Net*>&
getConnectors ();
private:
std::string _name;
std::string _model;
unsigned _order;
Netlist* _netlist;
Parameters _params;
std::map<std::string, Net*> _netMap;
};
inline void Instance::addParameter (const std::string& name, const char* value) { _params.addParameter(name,value); };
inline void Instance::addParameter (const std::string& name, const std::string& value) { _params.addParameter(name,value); };
inline const std::string& Instance::getName () const { return _name; };
inline const std::string& Instance::getModel () const { return _model; };
inline unsigned Instance::getOrder () { return _order; };
inline Netlist* Instance::getNetlist () { return _netlist; };
inline Parameters Instance::getParameters () { return _params; };
inline bool Instance::hasNoConnectors () { return _netMap.empty(); };
inline const std::map<std::string, Net*>& Instance::getConnectors () { return _netMap; };
} // OpenChams namespace.
#endif

55
vlsisapd/src/openChams/src/vlsisapd/openChams/Layout.h
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@ -1,55 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2008-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Layout.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_LAYOUT_H__
#define __OPENCHAMS_LAYOUT_H__
#include <map>
#include <string>
namespace OpenChams {
class Circuit;
class Node;
class Layout {
public:
Layout (Circuit*);
void addInstance (const std::string& name, const std::string& style);
inline bool hasNoInstance ();
inline Node* getHBTreeRoot ();
inline void setHBTreeRoot (Node*);
inline const std::map<std::string, std::string>& getInstances();
private:
Circuit* _circuit;
Node* _hbTreeRoot;
std::map<std::string, std::string> _instances; // device name <-> style (name)
};
inline bool Layout::hasNoInstance () { return _instances.empty(); };
inline Node* Layout::getHBTreeRoot () { return _hbTreeRoot; }
inline void Layout::setHBTreeRoot (Node* root) { _hbTreeRoot = root; }
inline const std::map<std::string, std::string>& Layout::getInstances() { return _instances; }
} // namespace
#endif

33
vlsisapd/src/openChams/src/vlsisapd/openChams/NRCCstr.h
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@ -1,33 +0,0 @@
/*
* NRCCstr.h
* openChams
*
* Created by Farakh JAVID on 25/10/2011.
* Copyright 2008-2010 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_NRCCSTR_H__
#define __OPENCHAMS_NRCCSTR_H__
#include "vlsisapd/openChams/Equation.h"
namespace OpenChams {
class NRCCstr : public Equation {
public:
NRCCstr(string controlVoltage);
inline void setVoltage(std::string s);
inline std::string getVoltage();
virtual void printEquations();
private:
std::string _controlVoltage;
};
inline void NRCCstr::setVoltage(std::string s) {_controlVoltage = s;}
inline std::string NRCCstr::getVoltage() {return _controlVoltage;}
} // namespace
#endif

89
vlsisapd/src/openChams/src/vlsisapd/openChams/Net.h
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@ -1,89 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Net.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_NET_H__
#define __OPENCHAMS_NET_H__
#include <vector>
#include <string>
namespace OpenChams {
class Netlist;
class Port;
class Wire;
class Net {
public:
class Connection {
public:
Connection (const std::string& instanceName, const std::string& connectorName);
inline const std::string& getInstanceName () const;
inline const std::string& getConnectorName() const;
private:
std::string _instanceName;
std::string _connectorName;
};
public:
Net (const std::string& netName, const std::string& typeName, bool, Netlist*);
void connectTo (const std::string& instanceName, const std::string& connectorName);
inline const std::string& getName () const;
inline const std::string& getType ();
inline bool isExternal ();
inline Netlist* getNetlist ();
inline bool hasNoConnections ();
inline const std::vector<Net::Connection*>& getConnections();
// schematic relative methods
Port* addPort (const std::string& type, unsigned idx, double x, double y, const std::string& orient);
Wire* addWire ();
inline bool hasNoPorts ();
inline const std::vector<Port*>& getPorts ();
inline bool hasNoWires ();
inline const std::vector<Wire*>& getWires ();
private:
std::string _name;
std::string _typeName;
bool _isExternal;
Netlist* _netlist;
std::vector<Net::Connection*> _connections; // <instanceName, connectorName>
// schematic relative members
std::vector<Port*> _ports;
std::vector<Wire*> _wires;
};
inline const std::string& Net::getName () const { return _name; }
inline const std::string& Net::getType () { return _typeName; }
inline bool Net::isExternal () { return _isExternal; }
inline Netlist* Net::getNetlist () { return _netlist; }
inline bool Net::hasNoConnections() { return (_connections.size() == 0)? true : false; }
inline const std::vector<Net::Connection*>& Net::getConnections() { return _connections; }
inline bool Net::hasNoPorts () { return (_ports.size() == 0)? true : false; }
inline const std::vector<Port*>& Net::getPorts () { return _ports; }
inline bool Net::hasNoWires () { return (_wires.size() == 0)? true : false; }
inline const std::vector<Wire*>& Net::getWires () { return _wires; }
inline const std::string& Net::Connection::getInstanceName () const { return _instanceName; };
inline const std::string& Net::Connection::getConnectorName() const { return _connectorName; };
} // namespace
#endif

61
vlsisapd/src/openChams/src/vlsisapd/openChams/Netlist.h
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@ -1,61 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Netlist.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_NETLIST_H__
#define __OPENCHAMS_NETLIST_H__
#include <vector>
namespace OpenChams {
class Instance;
class Device;
class Net;
class Circuit;
class Netlist {
public:
Netlist (Circuit*);
Instance* addInstance (const std::string& name, const std::string& model, unsigned);
Device* addDevice (const std::string& name, const std::string& model, unsigned, const std::string& mosType, bool);
Net* addNet (const std::string& name, const std::string& type , bool);
Instance* getInstance (const std::string&);
Net* getNet (const std::string&);
inline bool hasNoInstances ();
inline bool hasNoNets ();
inline const std::vector<Instance*>& getInstances ();
inline const std::vector<Net*>& getNets ();
inline Circuit* getCircuit ();
private:
Circuit* _circuit;
std::vector<Instance*> _instances;
std::vector<Net*> _nets;
};
inline bool Netlist::hasNoInstances() { return _instances.empty(); }
inline bool Netlist::hasNoNets () { return _nets.empty(); }
inline const std::vector<Instance*>& Netlist::getInstances () { return _instances; }
inline const std::vector<Net*>& Netlist::getNets () { return _nets; }
inline Circuit* Netlist::getCircuit () { return _circuit; }
} // OpenChams namespace.
#endif

101
vlsisapd/src/openChams/src/vlsisapd/openChams/Node.h
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@ -1,101 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2011-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Node.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_NODE_H__
#define __OPENCHAMS_NODE_H__
#include <string>
namespace OpenChams {
class Node {
public:
enum Position { NONE=0, RIGHT=1, TOP=2 };
public:
inline const std::string& getName () const;
inline Position getPosition () const;
inline Node* getParent ();
inline Node* getRight ();
inline Node* getTop ();
inline bool isRoot ();
inline void setRight (Node*);
inline void setTop (Node*);
protected:
Node (const std::string& nodeName, Position pos, Node* parent);
virtual ~Node () {};
private:
std::string _name;
Position _position;
Node* _parent;
Node* _right;
Node* _top;
};
inline const std::string& Node::getName () const { return _name; }
inline Node::Position Node::getPosition() const { return _position; }
inline Node* Node::getParent () { return _parent; }
inline Node* Node::getRight () { return _right; }
inline Node* Node::getTop () { return _top; }
inline bool Node::isRoot () { return _parent == NULL; }
inline void Node::setRight (Node* right) { _right = right; }
inline void Node::setTop (Node* top) { _top = top; }
class Bloc : public Node {
public:
Bloc(const std::string& blocName, Position pos=Node::NONE, Node* parent=NULL);
};
class Group : public Node {
public:
enum Align { NONE=0 , VERTICAL=1 , HORIZONTAL=2 };
public:
Group (const std::string& groupName, Position pos=Node::NONE, Node* parent=NULL);
inline void setRootNode (Node*);
inline void setIsolated (bool);
inline void setPaired (bool);
inline void setAlign (Align);
inline Node* getRootNode ();
inline bool isIsolated ();
inline bool isPaired ();
inline Align getAlign ();
private:
Node* _root;
bool _isolated;
bool _paired;
Align _align;
};
inline void Group::setRootNode(Node* root) { _root = root; }
inline void Group::setIsolated(bool isolated) { _isolated = isolated; }
inline void Group::setPaired (bool paired) { _paired = paired; }
inline void Group::setAlign (Group::Align align) { _align = align; }
inline Node* Group::getRootNode() { return _root; }
inline bool Group::isIsolated () { return _isolated; }
inline bool Group::isPaired () { return _paired; }
inline Group::Align Group::getAlign () { return _align; }
} // OpenChams namespace.
#endif

28
vlsisapd/src/openChams/src/vlsisapd/openChams/OpenChamsException.h
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@ -1,28 +0,0 @@
/*
* OpenChamsException.h
* openChams
*
* Created by damien dupuis on 20/01/10.
* Copyright 2010 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_EXCEPTION_NET_H__
#define __OPENCHAMS_EXCEPTION_NET_H__
#include <exception>
#include <string>
namespace OpenChams {
class OpenChamsException {
public:
OpenChamsException(const std::string& what) throw() : _what(what) {}
virtual const char* what() const throw() { return _what.c_str(); }
virtual ~OpenChamsException() throw() {}
private:
std::string _what;
};
} // namespace
#endif

74
vlsisapd/src/openChams/src/vlsisapd/openChams/Operator.h
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@ -1,74 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Operator.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_OPERATOR_H__
#define __OPENCHAMS_OPERATOR_H__
#include <map>
namespace OpenChams {
class Operator {
public:
class Constraint {
public:
Constraint ( const std::string& ref
, const std::string& refParam
, double factor );
inline const std::string& getRef ();
inline const std::string& getRefParam ();
inline double getFactor ();
private:
std::string _ref;
std::string _refParam;
double _factor;
};
public:
Operator (const std::string& operatorName, const std::string& simulModel);
void addConstraint (const std::string& paramName, const std::string& ref, const std::string& refParam);
void addConstraint (const std::string& paramName, const std::string& ref, const std::string& refParam, double factor);
void addConstraint (const std::string& paramName, const std::string& refEquation);
void addConstraint (const std::string& paramName, const std::string& refEquation, double factor);
inline const std::string& getName ();
inline const std::string& getSimulModel ();
inline bool hasNoConstraints ();
inline const std::map<std::string, Constraint*>& getConstraints();
private:
std::string _name;
std::string _simulModel;
std::map<std::string, Constraint*> _constraints;
};
inline const std::string& Operator::getName () { return _name; };
inline const std::string& Operator::getSimulModel () { return _simulModel; };
inline bool Operator::hasNoConstraints () { return _constraints.empty(); };
inline const std::map<std::string, Operator::Constraint*>& Operator::getConstraints() { return _constraints; };
inline const std::string& Operator::Constraint::getRef () { return _ref; };
inline const std::string& Operator::Constraint::getRefParam () { return _refParam; };
inline double Operator::Constraint::getFactor () { return _factor; };
} // namespace
#endif

48
vlsisapd/src/openChams/src/vlsisapd/openChams/Parameters.h
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@ -1,48 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2008-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Parameters.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_PARAMETERS_H__
#define __OPENCHAMS_PARAMETERS_H__
#include <map>
#include <string>
namespace OpenChams {
class Parameters {
public:
inline Parameters ();
inline bool isEmpty ();
const std::string& getValue (const std::string&);
inline const std::map<std::string,std::string>& getValues ();
void addParameter (const std::string&, const std::string&);
private:
std::map<std::string,std::string> _params;
};
inline Parameters::Parameters () { }
inline bool Parameters::isEmpty () { return (_params.size() == 0); }
inline const std::map<std::string,std::string>& Parameters::getValues () { return _params; };
} // OpenChams namespace.
#endif

68
vlsisapd/src/openChams/src/vlsisapd/openChams/Port.h
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@ -1,68 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2011-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Port.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_PORT_H__
#define __OPENCHAMS_PORT_H__
namespace OpenChams {
class Port {
public:
inline Port ( const std::string& type
, unsigned idx
, double x
, double y
, const std::string& orient );
inline ~Port ();
inline const std::string& getType () const;
inline unsigned getIndex () const;
inline double getX () const;
inline double getY () const;
inline const std::string& getOrientation() const;
private:
std::string _type;
unsigned _idx;
double _x;
double _y;
std::string _orient;
};
inline Port::Port (const std::string& type
, unsigned idx
, double x
, double y
, const std::string& orient)
: _type(type), _idx(idx), _x(x), _y(y), _orient(orient)
{ }
inline Port::~Port ()
{ }
inline const std::string& Port::getType () const { return _type; }
inline unsigned Port::getIndex () const { return _idx; }
inline double Port::getX () const { return _x; }
inline double Port::getY () const { return _y; }
inline const std::string& Port::getOrientation() const { return _orient; }
} // OpenChams namespace.
#endif

87
vlsisapd/src/openChams/src/vlsisapd/openChams/PySTLMapWrapper.h
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@ -1,87 +0,0 @@
#include <map>
#include <boost/python.hpp>
namespace OpenChams {
// since we want to wrap std::map<type, Class*> with cimple pointers (no boost::shared_ptr),
// we cannot use map_indexing_suite which has not the right return_value_policy.
// std::maps with no points value are wrapped using map_indexing_suite technique.
//
// This templated map_item struct is intended to be used for 'manual' wrapping:
template<class Key, class Val>
struct map_item {
typedef std::map<Key,Val> Map;
static Val get(Map & self, const Key idx) {
if (self.find(idx) == self.end()) {
PyErr_SetString(PyExc_KeyError,"Map key not found");
throw_error_already_set();
}
return self[idx];
}
static void set(Map& self, const Key idx, const Val val) { self[idx]=val; }
static void del(Map& self, const Key n) { self.erase(n); }
static bool in (Map const& self, const Key n) { return self.find(n) != self.end(); }
static list keys(Map const& self) {
list t;
for(typename Map::const_iterator it = self.begin() ; it!=self.end() ; ++it)
t.append(it->first);
return t;
}
static list values(Map const& self) {
list t;
for(typename Map::const_iterator it=self.begin(); it!=self.end(); ++it)
t.append(it->second);
return t;
}
static list items(Map const& self) {
list t;
for(typename Map::const_iterator it=self.begin(); it!=self.end(); ++it)
t.append( make_tuple(it->first, it->second) );
return t;
}
};
#define STL_MAP_WRAPPING_PTR(KEY_TYPE, VALUE_TYPE, PYTHON_TYPE_NAME) \
class_<std::pair<const KEY_TYPE, VALUE_TYPE> >((std::string(PYTHON_TYPE_NAME)+std::string("DATA")).c_str()) \
.def_readonly ("key" , &std::pair<const KEY_TYPE, VALUE_TYPE>::first ) \
.def_readwrite("value", &std::pair<const KEY_TYPE, VALUE_TYPE>::second) \
; \
class_<std::map<KEY_TYPE, VALUE_TYPE> >(PYTHON_TYPE_NAME) \
.def("__len__" , &std::map<KEY_TYPE, VALUE_TYPE>::size) \
.def("__iter__" , boost::python::iterator<std::map<KEY_TYPE, VALUE_TYPE>, return_internal_reference<> >()) \
.def("__getitem__" , &map_item<KEY_TYPE, VALUE_TYPE>().get, return_internal_reference<>()) \
.def("__setitem__" , &map_item<KEY_TYPE, VALUE_TYPE>().set ) \
.def("__delitem__" , &map_item<KEY_TYPE, VALUE_TYPE>().del ) \
.def("__contains__", &map_item<KEY_TYPE, VALUE_TYPE>().in ) \
.def("clear" , &std::map<KEY_TYPE, VALUE_TYPE>::clear ) \
.def("has_key" , &map_item<KEY_TYPE, VALUE_TYPE>().in ) \
.def("keys" , &map_item<KEY_TYPE, VALUE_TYPE>().keys ) \
.def("values" , &map_item<KEY_TYPE, VALUE_TYPE>().values) \
.def("items" , &map_item<KEY_TYPE, VALUE_TYPE>().items ) \
;
#define STL_MAP_WRAPPING(KEY_TYPE, VALUE_TYPE, PYTHON_TYPE_NAME) \
class_<std::pair<const KEY_TYPE, VALUE_TYPE> >((std::string(PYTHON_TYPE_NAME)+std::string("DATA")).c_str()) \
.def_readonly ("key" , &std::pair<const KEY_TYPE, VALUE_TYPE>::first ) \
.def_readwrite("value", &std::pair<const KEY_TYPE, VALUE_TYPE>::second) \
; \
class_<std::map<KEY_TYPE, VALUE_TYPE> >(PYTHON_TYPE_NAME) \
.def("__len__" , &std::map<KEY_TYPE, VALUE_TYPE>::size) \
.def("__iter__" , boost::python::iterator<std::map<KEY_TYPE, VALUE_TYPE>, return_internal_reference<> >()) \
.def("__getitem__" , &map_item<KEY_TYPE, VALUE_TYPE>().get ) \
.def("__setitem__" , &map_item<KEY_TYPE, VALUE_TYPE>().set ) \
.def("__delitem__" , &map_item<KEY_TYPE, VALUE_TYPE>().del ) \
.def("__contains__", &map_item<KEY_TYPE, VALUE_TYPE>().in ) \
.def("clear" , &std::map<KEY_TYPE, VALUE_TYPE>::clear ) \
.def("has_key" , &map_item<KEY_TYPE, VALUE_TYPE>().in ) \
.def("keys" , &map_item<KEY_TYPE, VALUE_TYPE>().keys ) \
.def("values" , &map_item<KEY_TYPE, VALUE_TYPE>().values) \
.def("items" , &map_item<KEY_TYPE, VALUE_TYPE>().items ) \
;
} // namespace

67
vlsisapd/src/openChams/src/vlsisapd/openChams/Schematic.h
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@ -1,67 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC 2010-2018, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Schematic.h" |
// +-----------------------------------------------------------------+
#ifndef VLSISAPD_OPENCHAMS_SCHEMATIC_H
#define VLSISAPD_OPENCHAMS_SCHEMATIC_H
#include <map>
#include <string>
namespace OpenChams {
class Circuit;
class Schematic {
public:
class Infos {
public:
Infos (double x, double y, const std::string& orient);
inline double getX ();
inline double getY ();
inline const std::string& getOrientation();
private:
double _x;
double _y;
std::string _orient;
};
public:
Schematic ( Circuit* );
void addInstance ( const std::string& instanceName
, double x
, double y
, const std::string& orient );
inline bool hasNoInstances ();
inline const std::map<std::string, Infos*>& getInstances();
private:
Circuit* _circuit;
std::map<std::string, Infos*> _instances;
};
inline bool Schematic::hasNoInstances() { return _instances.empty(); };
inline const std::map<std::string, Schematic::Infos*>& Schematic::getInstances () { return _instances; };
inline double Schematic::Infos::getX () { return _x; };
inline double Schematic::Infos::getY () { return _y; };
inline const std::string& Schematic::Infos::getOrientation() { return _orient; };
} // OpenChams namespace.
#endif

50
vlsisapd/src/openChams/src/vlsisapd/openChams/SimulModel.h
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@ -1,50 +0,0 @@
/*
* SimulModel.h
* openChams
*
* Created by damien dupuis on 06/07/10.
* Copyright 2010 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_SIMULMODEL_H__
#define __OPENCHAMS_SIMULMODEL_H__
#include <string>
namespace OpenChams {
class SimulModel {
public:
enum Base { BSIM3V3=0,
BSIM4=1,
PSP=2
};
enum Version { UNDEFINED=0,
SVT=1,
HVT=2,
LVT=3
};
SimulModel(unsigned, Base, Version, std::string);
inline unsigned getId() const;
inline Base getBase();
inline Version getVersion();
inline std::string getFilePath();
private:
unsigned _id;
Base _base;
Version _version;
std::string _filePath;
};
inline unsigned SimulModel::getId() const { return _id; };
inline SimulModel::Base SimulModel::getBase() { return _base; };
inline SimulModel::Version SimulModel::getVersion() { return _version; };
inline std::string SimulModel::getFilePath() { return _filePath;};
} // namespace
#endif

64
vlsisapd/src/openChams/src/vlsisapd/openChams/Sizing.h
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@ -1,64 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Sizing.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_SIZING_H__
#define __OPENCHAMS_SIZING_H__
#include <map>
#include <string>
namespace OpenChams {
class Circuit;
class Operator;
class Equation;
//class HighLevelCstr;
//class NRCCstr;
//class DDP;
class Sizing {
public:
Sizing ( Circuit* );
Operator* addOperator ( const std::string& instanceName
, const std::string& operatorName
, const std::string& simulModel);
// void addEquation ( const std::string& equationName, HighLevelCstr* );
// void addEquation ( const std::string& equationName, NRCCstr* );
// void addEquation ( const std::string& equationName, DDP* );
void addEquation ( const std::string& equationName, Equation* );
inline bool hasNoOperators ();
inline bool hasNoEquations ();
inline const std::map<std::string, Operator*>& getOperators();
inline const std::map<std::string, Equation*>& getEquations();
private:
Circuit* _circuit;
std::map<std::string, Operator*> _operators; // instanceName <-> operator
std::map<std::string, Equation*> _equations; // equationName <-> equation (string)
};
inline bool Sizing::hasNoOperators() { return _operators.empty(); };
inline bool Sizing::hasNoEquations() { return _equations.empty(); };
inline const std::map<std::string, Operator*>& Sizing::getOperators() { return _operators; };
inline const std::map<std::string, Equation*>& Sizing::getEquations() { return _equations; };
} // OpenChams namespace
#endif

394
vlsisapd/src/openChams/src/vlsisapd/openChams/SlicingTree.h
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@ -1,394 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2008-2018, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Eric Lao |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/SlicingTree.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_SLICINGTREE_H__
#define __OPENCHAMS_SLICINGTREE_H__
#include <vector>
#include <list>
#include <string>
#include <iostream>
#include <sstream>
#include <fstream>
namespace OpenChams {
enum Flags { UnknownType = 1 << 0
, HorizontalSNode = 1 << 1
, VerticalSNode = 1 << 2
, DeviceSNode = 1 << 3
, RoutingSNode = 1 << 4
, UnknownAlignment = 1 << 5
, AlignLeft = 1 << 6
, AlignRight = 1 << 7
, AlignCenter = 1 << 8
, AlignTop = 1 << 9
, AlignBottom = 1 << 10
};
// -----------------------------------------------------------------------------------------------//
// Class : SlicingNode
// -----------------------------------------------------------------------------------------------//
class SlicingNode
{
public:
SlicingNode( SlicingNode* parent = NULL );
virtual ~SlicingNode(){};
public:
virtual unsigned int getType () const { return UnknownType; }
virtual void print () const {};
inline void recursiveDestroy ();
void setParent ( SlicingNode* parent );
SlicingNode* getParent () const;
inline bool isRoot () const;
virtual void setAlignment ( std::string alignment );
std::string alignmentToString() const;
//Error Methods
virtual std::string getInstanceName () const;
virtual unsigned int getAlignment () const;
virtual bool getPreset () const;
virtual double getX () const;
virtual double getY () const;
virtual int getNFing () const;
virtual double getStart () const;
virtual double getStep () const;
virtual double getCount () const;
virtual void setInstanceName ( std::string instanceName );
virtual void setPreset ( std::string preset );
virtual void setX ( std::string x );
virtual void setY ( std::string y );
virtual void setNFing ( std::string nfing );
virtual void setStart ( std::string start );
virtual void setStep ( std::string step );
virtual void setCount ( std::string count );
virtual void setPreset ( bool preset );
virtual void setX ( double x );
virtual void setY ( double y );
virtual void setNFing ( int nfing );
virtual void setStart ( double start );
virtual void setStep ( double step );
virtual void setCount ( double count );
virtual const std::vector<SlicingNode*> getChildren () const;
virtual const std::list<std::pair <int,int> > getSymmetries () const;
virtual double getToleranceRatioH() const;
virtual double getToleranceRatioW() const;
virtual double getToleranceBandH () const;
virtual double getToleranceBandW () const;
virtual void setToleranceRatioH( std::string value );
virtual void setToleranceRatioW( std::string value );
virtual void setToleranceBandH ( std::string value );
virtual void setToleranceBandW ( std::string value );
virtual void setToleranceRatioH( double value );
virtual void setToleranceRatioW( double value );
virtual void setToleranceBandH ( double value );
virtual void setToleranceBandW ( double value );
virtual void push_back ( SlicingNode* node );
virtual void addSymmetry ( std::string source, std::string target );
virtual void addSymmetry ( int source, int target );
virtual double getValue () const;
virtual void setValue ( std::string value );
virtual void toXML ( std::ofstream& file, unsigned indent ){};
virtual std::string presetToString () const;
virtual std::string xToString () const;
virtual std::string yToString () const;
virtual std::string nfingToString () const;
virtual std::string startToString () const;
virtual std::string stepToString () const;
virtual std::string countToString () const;
virtual std::string valueToString () const;
virtual std::string toleranceRatioHToString() const;
virtual std::string toleranceRatioWToString() const;
virtual std::string toleranceBandHToString () const;
virtual std::string toleranceBandWToString () const;
virtual bool hasSameParentToleranceRatioH () const;
virtual bool hasSameParentToleranceRatioW () const;
virtual bool hasSameParentToleranceBandH () const;
virtual bool hasSameParentToleranceBandW () const;
virtual bool checkInitialPlacement( int& cpt ) const;
virtual std::list<SlicingNode*> getLeaves () const;
protected:
SlicingNode* _parent;
unsigned int _alignment;
};
inline void SlicingNode::recursiveDestroy(){ delete(this); }
inline bool SlicingNode::isRoot () const { return (_parent == NULL); }
// -----------------------------------------------------------------------------------------------//
// Class : DeviceSNode
// -----------------------------------------------------------------------------------------------//
class DSlicingNode : public SlicingNode
{
private:
DSlicingNode( std::string instanceName, SlicingNode* parent = NULL );
~DSlicingNode(){};
public:
inline static DSlicingNode* create ( std::string instanceName, SlicingNode* parent = NULL );
inline std::string getInstanceName () const;
inline unsigned int getAlignment () const;
inline bool getPreset () const;
inline double getX () const;
inline double getY () const;
inline int getNFing () const;
inline double getStart () const;
inline double getStep () const;
inline double getCount () const;
inline unsigned int getType () const;
void setInstanceName ( std::string instanceName );
void setPreset ( std::string preset );
void setX ( std::string x );
void setY ( std::string y );
void setNFing ( std::string nfing );
void setStart ( std::string start );
void setStep ( std::string step );
void setCount ( std::string count );
inline void setPreset ( bool preset );
inline void setX ( double x );
inline void setY ( double y );
inline void setNFing ( int nfing );
inline void setStart ( double start );
inline void setStep ( double step );
inline void setCount ( double count );
void print () const;
void toXML ( std::ofstream& file, unsigned indent );
inline std::string presetToString () const;
inline std::string xToString () const;
inline std::string yToString () const;
inline std::string nfingToString () const;
inline std::string startToString () const;
inline std::string stepToString () const;
inline std::string countToString () const;
bool checkInitialPlacement ( int& cpt ) const;
private:
std::string _instanceName;
bool _preset;
double _x;
double _y;
int _nfing;
double _start;
double _step;
double _count;
};
inline DSlicingNode* DSlicingNode::create ( std::string instanceName, SlicingNode* parent ){ return new DSlicingNode( instanceName ); }
inline std::string DSlicingNode::getInstanceName () const { return _instanceName ; }
inline unsigned int DSlicingNode::getAlignment () const { return _alignment ; }
inline bool DSlicingNode::getPreset () const { return _preset ; }
inline double DSlicingNode::getX () const { return _x ; }
inline double DSlicingNode::getY () const { return _y ; }
inline int DSlicingNode::getNFing () const { return _nfing ; }
inline double DSlicingNode::getStart () const { return _start ; }
inline double DSlicingNode::getStep () const { return _step ; }
inline double DSlicingNode::getCount () const { return _count ; }
inline unsigned int DSlicingNode::getType () const { return DeviceSNode ; }
inline void DSlicingNode::setPreset ( bool preset ) { _preset = preset; }
inline void DSlicingNode::setX ( double x ) { _x = x ; }
inline void DSlicingNode::setY ( double y ) { _y = y ; }
inline void DSlicingNode::setNFing ( int nfing ) { _nfing = nfing ; }
inline void DSlicingNode::setStart ( double start ) { _start = start ; }
inline void DSlicingNode::setStep ( double step ) { _step = step ; }
inline void DSlicingNode::setCount ( double count ) { _count = count ; }
inline std::string DSlicingNode::presetToString () const { return _preset ? "true" : "false"; }
inline std::string DSlicingNode::xToString () const { return std::to_string(_x ); }
inline std::string DSlicingNode::yToString () const { return std::to_string(_y ); }
inline std::string DSlicingNode::nfingToString () const { return std::to_string(_nfing); }
inline std::string DSlicingNode::startToString () const { return std::to_string(_start); }
inline std::string DSlicingNode::stepToString () const { return std::to_string(_step ); }
inline std::string DSlicingNode::countToString () const { return std::to_string(_count); }
// -----------------------------------------------------------------------------------------------//
// Class : HVSlicingNode
// -----------------------------------------------------------------------------------------------//
class HVSlicingNode : public SlicingNode
{
protected:
HVSlicingNode( SlicingNode* parent = NULL );
virtual ~HVSlicingNode(){};
public:
inline unsigned int getAlignment () const;
inline double getToleranceRatioH() const;
inline double getToleranceRatioW() const;
inline double getToleranceBandH () const;
inline double getToleranceBandW () const;
inline const std::vector<SlicingNode*> getChildren () const;
inline const std::list<std::pair <int,int> > getSymmetries() const;
void setToleranceRatioH( std::string value );
void setToleranceRatioW( std::string value );
void setToleranceBandH ( std::string value );
void setToleranceBandW ( std::string value );
void setToleranceRatioH( double value );
void setToleranceRatioW( double value );
void setToleranceBandH ( double value );
void setToleranceBandW ( double value );
void push_back ( SlicingNode* node );
void addSymmetry ( std::string source, std::string target );
void addSymmetry ( int source, int target );
void recursiveDestroy ();
void print () const;
inline std::string toleranceRatioHToString () const;
inline std::string toleranceRatioWToString () const;
inline std::string toleranceBandHToString () const;
inline std::string toleranceBandWToString () const;
bool hasSameParentToleranceRatioH () const;
bool hasSameParentToleranceRatioW () const;
bool hasSameParentToleranceBandH () const;
bool hasSameParentToleranceBandW () const;
bool checkInitialPlacement ( int& cpt ) const;
std::list<SlicingNode*> getLeaves () const;
protected:
double _toleranceRatioH;
double _toleranceRatioW;
double _toleranceBandH;
double _toleranceBandW;
std::list<std::pair <int,int> > _symmetries;
std::vector<SlicingNode*> _children;
};
inline unsigned int HVSlicingNode::getAlignment () const { return _alignment ; }
inline double HVSlicingNode::getToleranceRatioH() const { return _toleranceRatioH; }
inline double HVSlicingNode::getToleranceRatioW() const { return _toleranceRatioW; }
inline double HVSlicingNode::getToleranceBandH () const { return _toleranceBandH ; }
inline double HVSlicingNode::getToleranceBandW () const { return _toleranceBandW ; }
inline const std::vector<SlicingNode*> HVSlicingNode::getChildren () const { return _children ; }
inline const std::list<std::pair<int,int> > HVSlicingNode::getSymmetries() const { return _symmetries ; }
inline std::string HVSlicingNode::toleranceRatioHToString() const { return std::to_string(_toleranceRatioH); }
inline std::string HVSlicingNode::toleranceRatioWToString() const { return std::to_string(_toleranceRatioW); }
inline std::string HVSlicingNode::toleranceBandHToString () const { return std::to_string(_toleranceBandH); }
inline std::string HVSlicingNode::toleranceBandWToString () const { return std::to_string(_toleranceBandW); }
// -----------------------------------------------------------------------------------------------//
// Class : HSlicingNode
// -----------------------------------------------------------------------------------------------//
class HSlicingNode: public HVSlicingNode
{
private:
HSlicingNode( SlicingNode* parent = NULL );
~HSlicingNode(){};
public:
inline static HSlicingNode* create ( SlicingNode* parent = NULL );
inline unsigned int getType () const;
void print () const;
void toXML ( std::ofstream& file, unsigned indent );
};
inline HSlicingNode* HSlicingNode::create ( SlicingNode* parent ){ return new HSlicingNode(parent); }
inline unsigned int HSlicingNode::getType() const { return HorizontalSNode ; }
// -----------------------------------------------------------------------------------------------//
// Class : VSlicingNode
// -----------------------------------------------------------------------------------------------//
class VSlicingNode: public HVSlicingNode
{
private:
VSlicingNode( SlicingNode* parent = NULL );
~VSlicingNode(){};
public:
inline static VSlicingNode* create ( SlicingNode* parent = NULL );
inline unsigned int getType () const;
void print () const;
void toXML ( std::ofstream& file, unsigned indent );
};
inline VSlicingNode* VSlicingNode::create ( SlicingNode* parent ){ return new VSlicingNode(parent); }
inline unsigned int VSlicingNode::getType() const { return VerticalSNode ; }
// -----------------------------------------------------------------------------------------------//
// Class : RoutingSNode
// -----------------------------------------------------------------------------------------------//
class RSlicingNode: public SlicingNode
{
private:
RSlicingNode( std::string value, SlicingNode* parent = NULL );
RSlicingNode( double value, SlicingNode* parent = NULL );
~RSlicingNode(){};
public:
inline static RSlicingNode* create ( std::string value, SlicingNode* parent = NULL );
inline static RSlicingNode* create ( double value, SlicingNode* parent = NULL );
inline void recursiveDestroy ();
inline double getValue () const;
void setValue ( std::string value );
inline unsigned int getType () const;
void print () const;
void setAlignment ( std::string alignment) {};
void toXML ( std::ofstream& file, unsigned indent );
inline std::string valueToString () const;
private:
double _value;
};
inline RSlicingNode* RSlicingNode::create ( std::string value, SlicingNode* parent ){ return new RSlicingNode( value, parent ); }
inline RSlicingNode* RSlicingNode::create ( double value, SlicingNode* parent ){ return new RSlicingNode( value, parent ); }
inline double RSlicingNode::getValue () const{ return _value ; }
inline unsigned int RSlicingNode::getType () const{ return RoutingSNode; }
inline std::string RSlicingNode::valueToString () const { return std::to_string(_value); }
} // OpenChams namespace
#endif

75
vlsisapd/src/openChams/src/vlsisapd/openChams/Transistor.h
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@ -1,75 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2010-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Transistor.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_TRANSISTOR_H__
#define __OPENCHAMS_TRANSISTOR_H__
#include <map>
#include "vlsisapd/openChams/Parameters.h"
namespace OpenChams {
class Instance;
class Net;
class Transistor {
public:
Transistor (const std::string&, Instance*);
inline void addParameter (const std::string&, const char*);
inline void addParameter (const std::string&, const std::string&);
inline Parameters getParameters ();
inline void setName (const std::string&);
inline const std::string& getName ();
inline const std::string& getGate ();
inline const std::string& getSource ();
inline const std::string& getDrain ();
inline const std::string& getBulk ();
void setGate (const std::string&);
void setSource (const std::string&);
void setDrain (const std::string&);
void setBulk (const std::string&);
private:
bool checkConnector (const std::string&);
private:
std::string _name;
std::string _gate; // le nom du connecteur de _instance auquel la gate est reliée
std::string _source; // le nom du connecteur de _instance auquel la source est reliée
std::string _drain; // le nom du connecteur de _instance auquel le drain est relié
std::string _bulk; // le nom du connecteur de _instance auquel le bulk est relié
Instance* _instance;
Parameters _params;
};
inline void Transistor::addParameter (const std::string& name, const char* value) { _params.addParameter(name,value); };
inline void Transistor::addParameter (const std::string& name, const std::string& value) { _params.addParameter(name,value); };
inline Parameters Transistor::getParameters () { return _params; };
inline void Transistor::setName (const std::string& name) { _name = name; };
inline const std::string& Transistor::getName () { return _name; };
inline const std::string& Transistor::getGate () { return _gate; };
inline const std::string& Transistor::getSource () { return _source; };
inline const std::string& Transistor::getDrain () { return _drain; };
inline const std::string& Transistor::getBulk () { return _bulk; };
} // OpenChams namespace.
#endif

124
vlsisapd/src/openChams/src/vlsisapd/openChams/Wire.h
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@ -1,124 +0,0 @@
// -*- C++ -*-
//
// This file is part of the VLSI SAPD Software.
// Copyright (c) UPMC/LIP6 2011-2012, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | V L S I S A P D |
// | OpenChams Circuit Data Base |
// | |
// | Author : Damien Dupuis |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== |
// | C++ Header : "./vlsisapd/openChams/Wire.h" |
// +-----------------------------------------------------------------+
#ifndef __OPENCHAMS_WIRE_H__
#define __OPENCHAMS_WIRE_H__
#include <string>
#include <vector>
namespace OpenChams {
class WirePoint {
public:
WirePoint() {}
virtual ~WirePoint() {};
};
class InstancePoint: public WirePoint {
public:
inline InstancePoint (const std::string& name, const std::string& plug);
inline virtual ~InstancePoint ();
inline const std::string& getName ();
inline const std::string& getPlug ();
private:
std::string _name;
std::string _plug;
};
class PortPoint: public WirePoint {
public:
inline PortPoint (unsigned idx);
inline virtual ~PortPoint ();
inline unsigned getIndex ();
private:
unsigned _idx;
};
class IntermediatePoint: public WirePoint {
public:
inline IntermediatePoint (double x, double y);
inline virtual ~IntermediatePoint ();
inline double getX ();
inline double getY ();
private:
double _x;
double _y;
};
class Wire {
public:
inline Wire ();
inline ~Wire ();
// Accessors
inline WirePoint* getStartPoint ();
inline WirePoint* getEndPoint ();
inline bool hasNoIntermediatePoints();
inline const std::vector<IntermediatePoint*>& getIntermediatePoints();
// Modifiers
void setStartPoint (const std::string& name, const std::string& plug);
void setStartPoint (unsigned idx);
void setEndPoint (const std::string& name, const std::string& plug);
void setEndPoint (unsigned idx);
void addIntermediatePoint (double x, double y);
private:
WirePoint* _start;
WirePoint* _end;
std::vector<IntermediatePoint*> _inters;
};
// Inlines of InstancePoint.
inline InstancePoint::InstancePoint (const std::string& name, const std::string& plug) : _name(name), _plug(plug) {}
inline InstancePoint::~InstancePoint () {}
inline const std::string& InstancePoint::getName () { return _name; }
inline const std::string& InstancePoint::getPlug () { return _plug; }
// Inlines of PortPoint.
inline PortPoint::PortPoint (unsigned idx): _idx(idx) {}
inline PortPoint::~PortPoint () {}
inline unsigned PortPoint::getIndex () { return _idx; }
// Inlines of IntermediatePoint.
inline IntermediatePoint::IntermediatePoint (double x, double y): _x(x), _y(y) {}
inline IntermediatePoint::~IntermediatePoint() {}
inline double IntermediatePoint::getX () { return _x; }
inline double IntermediatePoint::getY () { return _y; }
// Inlines of Wire.
inline Wire::Wire () : _start(NULL), _end(NULL), _inters() {}
inline Wire::~Wire () {}
inline WirePoint* Wire::getStartPoint () { return _start; }
inline WirePoint* Wire::getEndPoint () { return _end; }
inline bool Wire::hasNoIntermediatePoints() { return _inters.empty(); }
inline const std::vector<IntermediatePoint*>& Wire::getIntermediatePoints() { return _inters; }
} // namespace
#endif