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In CRL::NamingScheme::vlogTovhdl(), remove '%' invalid VHDL character.

This commit is contained in:
Jean-Paul Chaput 2020-07-14 19:53:34 +02:00
parent 8ce2a7e318
commit 960e0cda18
2 changed files with 11 additions and 3 deletions
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13
crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
View File

@ -52,8 +52,10 @@ namespace Vhdl {
const Signal* signal = entity->getGlobal( getString(masterNet->getName()) );
if (signal) return signal->getBit();
cerr << Error( "PortMap::_lookup() VHDL extension missing on parent of global <%s>."
cerr << Error( "PortMap::_lookup() VHDL extension missing on parent of global \"%s\"\n"
" In parent cell \"%s\"."
, getString(masterNet).c_str()
, getString(instance->getCell()->getName()).c_str()
) << endl;
} else {
Net* net = plug->getNet();
@ -61,12 +63,17 @@ namespace Vhdl {
Bit* bit = BitExtension::get( net );
if (bit) return bit;
cerr << Error( "PortMap::_lookup() VHDL extension missing on <%s>."
cerr << Error( "PortMap::_lookup() VHDL extension missing on \"%s\"."
" In cell \"%s\"."
, getString(net).c_str()
, getString(net->getCell()->getName()).c_str()
) << endl;
} else {
cerr << Error( "PortMap::_lookup() Unconnected <%s>."
cerr << Error( "PortMap::_lookup() Unconnected \"%s\",\n"
" In instance \"%s\" of \"%s\"."
, getString(plug).c_str()
, getString(instance->getName()).c_str()
, getString(instance->getMasterCell()->getName()).c_str()
) << endl;
}
}

1
crlcore/src/ccore/toolbox/NamingScheme.cpp
View File

@ -73,6 +73,7 @@ namespace CRL {
if (translated == '\\') translated = '_';
if (translated == '.' ) translated = '_';
if (translated == '%' ) translated = '_';
if (translated == '$' ) translated = '_';
if (translated == '?' ) translated = '_';
if (translated == ':' ) translated = '_';