Added support for Tristate and bidir pads in CoreToChip.
* New: In Cumulus/plugins/CoreToChip, added support for Tristate ouput
pads and bidirectional pads.
Added capability to name the I/O pad instance and their external
terminals so we can override the default naming scheme.
Mandatory anyway for bidirectional and tristate I/O pad as we
cannot guess the core net grouping (in/out/enable).
Support is available for symbolic CMOS and AMS c35b4 (but not
published due to NDA).
* Change: In Cumulus/plugins/chip/Configuration.py, the configuration
file is now named simply "ioring.py" instead of being prefixed by
the design name. As a consequence we can have only one chip per
directory. But now all the tools, for any design in that directory
can peek datas into it.
This commit is contained in:
Jean-Paul Chaput
parent
acc3a38f60
commit
86c4e9cb17
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@ -67,6 +67,7 @@ def ScriptMain ( **kw ):
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cell, editor = plugins.kwParseMain( **kw )
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conf = chip.Configuration.loadConfiguration( cell, editor )
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conf.chipValidate()
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if not conf.validated: return False
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placeChip = chip.Chip.PlaceRoute( conf )
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@ -68,6 +68,7 @@ def ScriptMain ( **kw ):
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cell, editor = plugins.kwParseMain( **kw )
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conf = chip.Configuration.loadConfiguration( cell, editor )
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conf.chipValidate()
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if not conf.validated: return False
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prChip = chip.Chip.PlaceRoute( conf )
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@ -51,7 +51,7 @@ def ScriptMain ( **kw ):
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raise ErrorMessage( 1, 'CoreToChip_cmos.ScriptMain(): No cell (core) loaded in the editor yet.' )
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chip_cmos = core2chip.cmos.cmos( cell )
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chip_cmos.buildChip( 'chip' )
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chip_cmos.buildChip()
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if editor: editor.setCell( chip_cmos.chip )
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@ -108,6 +108,82 @@ def destroyNetComponents ( net ):
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return
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# -------------------------------------------------------------------
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# Class : "IoPadConf".
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class IoPadConf ( object ):
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# self._datas is a table of 6 elements, the five first coming from
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# the configuration itself. Direction are taken from the core point
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# of view.
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#
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# Meaning of the table element's:
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#
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# +---------+-----------------------------------------------------------+
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# | Index | Type |
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# +=========+===========================================================+
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# | 0 | Pad instance name |
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# +---------+-----------------------------------------------------------+
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# | 1 | Pad connected signal name. |
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# | | The name of the external signal at chip level |
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# +---------+-----------------------------------------------------------+
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# | 2 | The name of the signal going *from* the pad to the core. |
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# | | OUT direction in the core |
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# +---------+-----------------------------------------------------------+
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# | 3 | The name of the signal going *to* the pad from the core. |
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# | | IN direction in core |
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# +---------+-----------------------------------------------------------+
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# | 4 | The enable signal, coming from the core |
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# +---------+-----------------------------------------------------------+
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# | 5 | The IoPad associated object. It is set to None initially |
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# +---------+-----------------------------------------------------------+
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def __init__ ( self, datas ):
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if not isinstance(datas,list):
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raise ErrorMessage( 1, [ 'IoPadConf.__init__(): The "datas" parameter is not a list.'
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, str(datas) ] )
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if len(datas) < 3 and len(datas) > 5:
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raise ErrorMessage( 1, [ 'IoPadConf.__init__(): The "datas" list must have between 3 to 5 elements.'
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, str(datas) ] )
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self._datas = datas
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self._datas.append( None )
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return
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@property
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def padInstanceName ( self ): return self._datas[0]
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@property
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def padNetName ( self ): return self._datas[1]
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@property
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def fromCoreNet ( self ): return self._datas[2]
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@property
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def toCoreNet ( self ): return self._datas[3]
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@property
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def enableNet ( self ): return self._datas[-2]
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@property
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def nets ( self ): return self._datas[2:-1]
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@property
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def udata ( self ): return self._datas[-1]
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@udata.setter
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def udata ( self, data ): self._datas[-1] = data
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def isTristate ( self ): return len(self._datas) == 5
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def isBidir ( self ): return len(self._datas) == 6
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def __repr__ ( self ):
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s = '<IoPadConf %s pad:%s from:%s' % (self.padInstanceName,self.padNetName,self.fromCoreNet)
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if self.isBidir():
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s += ' to:%s en:%s' % (self.toCoreNet,self.enableNet)
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s += '>'
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return s
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# -------------------------------------------------------------------
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# Class : "Configuration.GaugeConf".
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@ -448,9 +524,15 @@ class ChipConf ( object ):
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return useClockTree
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@staticmethod
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def _readChipName( chipConfigDict ):
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if chipConfigDict.has_key('chip.name'): return chipConfigDict['chip.name']
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return 'chip'
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def _loadIoPadGauge ( self, chipConfigDict ):
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if not chipConfigDict.has_key('pads.ioPadGauge'):
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raise ErrorMessage( 1, 'The IO pad gauge configuration paramater "pads.ioPadGauge" is missing.' )
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#raise ErrorMessage( 1, 'The IO pad gauge configuration parameter "pads.ioPadGauge" is missing.' )
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return
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self.gaugeConf._loadIoPadGauge( chipConfigDict['pads.ioPadGauge'] )
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return
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@ -481,30 +563,30 @@ class ChipConf ( object ):
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% (i,keyword) )
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continue
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instance = self.cell.getInstance( instanceName )
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if not instance:
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raise ErrorMessage( 1, 'The pad [%d] (%s) of list %s do not exists in netlist (skipped).'
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% (i,instanceName,keyword) )
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continue
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if (instance.getMasterCell().getAbutmentBox().getHeight() != self.gaugeConf.getIoPadHeight()):
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raise ErrorMessage( 1, 'The pad [%d] (%s) of list %s is not an instance of a pad cell (skipped).'
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% (i,instanceName,keyword) )
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continue
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padList.append( [ position, instance ] )
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padList.append( [ position, instanceName ] )
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return padList
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def _readPadInstances ( self, chipConfigDict ):
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if not chipConfigDict.has_key('pads.instances'): return [ ]
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padInstancesConf = chipConfigDict['pads.instances']
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if not isinstance(padInstancesConf,list):
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raise ErrorMessage( 1, 'The "%s" entry is not a list.' )
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return [ ]
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padInstances = [ ]
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for entry in padInstancesConf:
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padInstances.append( IoPadConf( entry ) )
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return padInstances
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def __init__ ( self, chipConfigDict, cell, viewer=None ):
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trace( 550, '\tONE LAMBDA = %s\n' % DbU.getValueString(DbU.fromLambda(1.0)) )
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if not isinstance(chipConfigDict,dict):
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raise ErrorMessage( 1, 'The "chip" variable is not a dictionnary.' )
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self.chipMode = True
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if len(chipConfigDict.keys()) == 0: self.chipMode = False
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self.validated = True
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self.gaugeConf = GaugeConf()
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@ -523,32 +605,36 @@ class ChipConf ( object ):
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self.coronaVss = None
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self.coronaCk = None
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self.blockageNet = None
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if self.chipMode:
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self._loadIoPadGauge( chipConfigDict )
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self.coronas = []
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self.cores = []
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if self.chipMode:
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self.padsHavePosition = False
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self.southPads = self._readPads( chipConfigDict, 'pads.south' )
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self.northPads = self._readPads( chipConfigDict, 'pads.north' )
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self.eastPads = self._readPads( chipConfigDict, 'pads.east' )
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self.westPads = self._readPads( chipConfigDict, 'pads.west' )
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self.coreSize = ChipConf._readCoreSize( chipConfigDict )
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self.chipSize = ChipConf._readChipSize( chipConfigDict )
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self.useClockTree = ChipConf._readClockTree( chipConfigDict )
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self._loadIoPadGauge( chipConfigDict )
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minHCorona = self.railsNb*(self.hRailWidth + self.hRailSpace) + self.hRailSpace
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minVCorona = self.railsNb*(self.vRailWidth + self.vRailSpace) + self.vRailSpace
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if minHCorona > minVCorona: self.minCorona = minHCorona*2
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else: self.minCorona = minVCorona*2
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self.checkPads()
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self.checkCorona()
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self.computeChipSize()
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#self.checkChipSize()
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self.findPowerAndClockNets()
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self.padsHavePosition = False
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self.padInstances = self._readPadInstances( chipConfigDict )
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self.southPads = self._readPads( chipConfigDict, 'pads.south' )
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self.northPads = self._readPads( chipConfigDict, 'pads.north' )
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self.eastPads = self._readPads( chipConfigDict, 'pads.east' )
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self.westPads = self._readPads( chipConfigDict, 'pads.west' )
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self.coreSize = ChipConf._readCoreSize ( chipConfigDict )
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self.chipSize = ChipConf._readChipSize ( chipConfigDict )
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self.useClockTree = ChipConf._readClockTree( chipConfigDict )
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self.chipName = ChipConf._readChipName ( chipConfigDict )
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minHCorona = self.railsNb*(self.hRailWidth + self.hRailSpace) + self.hRailSpace
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minVCorona = self.railsNb*(self.vRailWidth + self.vRailSpace) + self.vRailSpace
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if minHCorona > minVCorona: self.minCorona = minHCorona*2
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else: self.minCorona = minVCorona*2
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return
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def chipValidate ( self ):
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self.checkPads()
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self.checkCorona()
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self.computeChipSize()
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#self.checkChipSize()
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self.findPowerAndClockNets()
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return
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@ -857,24 +943,42 @@ class ChipConf ( object ):
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def checkPads ( self ):
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def contains ( padList, pad ):
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for padPair in padList:
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if padPair[1] == pad: return True
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def contains ( padList, side, padInstance ):
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for i in range(len(padList)):
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if padList[i][1] == padInstance.getName():
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if (padInstance.getMasterCell().getAbutmentBox().getHeight() != self.gaugeConf.getIoPadHeight()):
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raise ErrorMessage( 1, 'The pad [%d] %s (%s) on %s side is not an instance of a pad cell.'
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% (i,padInstance.getName(),padInstance.getModel().getName(),side) )
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padList[i][1] = padInstance
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return True
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return False
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def checkNotFounds ( padList, side ):
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for i in range(len(padList)):
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if not isinstance(padList[i][1],Instance):
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print ErrorMessage( 1, 'The pad [%d] (%s) of list %s do not exists in netlist (skipped).'
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% (i,padList[i][1],side) )
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return
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af = CRL.AllianceFramework.get()
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cellPads = []
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for instance in self.cell.getInstances():
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if contains(self.southPads,instance): continue
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if contains(self.northPads,instance): continue
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if contains(self.eastPads ,instance): continue
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if contains(self.westPads ,instance): continue
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if contains(self.southPads,'south',instance): continue
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if contains(self.northPads,'north',instance): continue
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if contains(self.eastPads ,'east' ,instance): continue
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if contains(self.westPads ,'west' ,instance): continue
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if (instance.getMasterCell().getAbutmentBox().getHeight() == self.gaugeConf.getIoPadHeight()):
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raise ErrorMessage( 1, 'Pad "%s" is not on any side (N/S/E/W).' % instance.getName() )
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self.validated = False
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else:
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self.coronas.append( instance )
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checkNotFounds( self.southPads, 'south' )
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checkNotFounds( self.northPads, 'north' )
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checkNotFounds( self.eastPads , 'east' )
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checkNotFounds( self.westPads , 'west' )
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if len(self.coronas) > 1:
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message = [ 'Chip "%s" have more than one corona:' % self.cell.getName() ]
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for i in range(len(self.coronas)):
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@ -1117,7 +1221,8 @@ class ChipConf ( object ):
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def loadConfiguration ( cell, viewer=None ):
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sys.path.append( os.getcwd() )
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confFile = cell.getName()+'_ioring'
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#confFile = cell.getName()+'_ioring'
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confFile = 'ioring'
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if not os.path.isfile(confFile+'.py'):
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raise ErrorMessage( 1, 'ChipPlugin configuration file <%s.py> is missing.' % confFile )
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@ -22,6 +22,7 @@ from CRL import Catalog
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from CRL import AllianceFramework
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from helpers import netDirectionToStr
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from helpers.io import ErrorMessage
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import chip.Chip
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# -------------------------------------------------------------------
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@ -30,30 +31,45 @@ from helpers.io import ErrorMessage
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class IoNet ( object ):
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IsElem = 0x0001
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IsEnable = 0x0002
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IsBidir = 0x0004
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reVHDLVector = re.compile( r'(?P<name>[^(]*)\((?P<index>[\d]+)\)$' )
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def __init__ ( self, coreToChip, coreNet ):
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self.coreToChip = coreToChip
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self.coreNet = coreNet
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self.coronaNet = None # Corona net going from core to corona.
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self.chipIntNet = None # Chip net going from corona to I/O pad.
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self.chipExtNet = None # Chip net going from I/O pad to the outside world.
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self.pads = [ ]
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self.coreToChip = coreToChip
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self._flags = 0
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self._chipExtNetName = None # In the case of bidir pad, force external net name.
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self.coreNet = coreNet
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self.coronaNet = None # Corona net going from core to corona.
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self.chipIntNet = None # Chip net going from corona to I/O pad.
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self.chipExtNet = None # Chip net going from I/O pad to the outside world.
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m = IoNet.reVHDLVector.match( self.coreNet.getName() )
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if m:
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self._isElem = True
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self._flags |= IoNet.IsElem
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self._name = m.group('name')
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self._index = m.group('index')
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else:
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self._isElem = False
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self._name = self.coreNet.getName()
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self._index = 0
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self._type = self.coreToChip.getNetType( self._name )
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return
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def isElem ( self ): return self._isElem
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def __repr__ ( self ):
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s = '<IoNet "%s" ext:' % self.coreNet.getName()
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if self.chipExtNet: s += self.chipExtNet.getName()
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else: s += 'None'
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s += ' int:'
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if self.chipIntNet: s += self.chipIntNet.getName()
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else: s += 'None'
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s += '>'
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return s
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def isElem ( self ): return self._flags & IoNet.IsElem
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def isEnable ( self ): return self._flags & IoNet.IsEnable
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def isBidir ( self ): return self._flags & IoNet.IsBidir
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def isGlobal ( self ): return self.isGlobal( self._name )
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@ -69,25 +85,46 @@ class IoNet ( object ):
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@property
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def coronaNetName ( self ):
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s = self._name + '_core'
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if self._isElem: s += '(' + self._index + ')'
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if self._flags & IoNet.IsElem: s += '(' + self._index + ')'
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return s
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@property
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def padNetName ( self ):
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if self._chipExtNetName is not None: return self._chipExtNetName
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s = self._name
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if self._isElem: s += '(' + self._index + ')'
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if self._flags & IoNet.IsElem: s += '(' + self._index + ')'
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return s
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@padNetName.setter
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def padNetName ( self, name ): self._chipExtNetName = name
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@property
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def padInstanceName ( self ):
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s = self._name
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if self._isElem: s += '_' + self._index
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if self._flags & IoNet.IsElem: s += '_' + self._index
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return s
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def setChipExtNetName ( self, name ): self.chipExtNetName = name
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def setEnable ( self, state ):
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if state == True: self._flags |= IoNet.IsEnable
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else: self._flags &= ~IoNet.IsEnable
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return
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def setBidir ( self, state ):
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if state == True: self._flags |= IoNet.IsBidir
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else: self._flags &= ~IoNet.IsBidir
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return
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def buildNets ( self ):
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self.chipExtNet = Net.create( self.coreToChip.chip, self.padNetName )
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self.chipExtNet.setExternal ( True )
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self.chipExtNet.setDirection( self.coreNet.getDirection() )
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if self.chipIntNet != None: return
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if not self.isBidir () \
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or (not self.isEnable() and self.coreNet.getDirection() == Net.Direction.OUT):
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self.chipExtNet = Net.create( self.coreToChip.chip, self.padNetName )
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self.chipExtNet.setExternal ( True )
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self.chipExtNet.setDirection( self.coreNet.getDirection() )
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self.chipIntNet = Net.create( self.coreToChip.chip, self.coronaNetName )
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@ -110,6 +147,110 @@ class IoNet ( object ):
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return
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# -------------------------------------------------------------------
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# Class : "IoPad".
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class IoPad ( object ):
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IN = 0x0001
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OUT = 0x0002
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BIDIR = 0x0004
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TRI_OUT = 0x0008
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UNSUPPORTED = 0x0010
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@staticmethod
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def directionToStr ( direction ):
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if direction == IoPad.IN: return "IN"
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if direction == IoPad.OUT: return "OUT"
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if direction == IoPad.BIDIR: return "BIDIR"
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if direction == IoPad.TRI_OUT: return "TRI_OUT"
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if direction == IoPad.UNSUPPORTED: return "UNSUPPORTED"
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return "Invalid value"
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def __init__ ( self, coreToChip, padInstanceName ):
|
||||
self.coreToChip = coreToChip
|
||||
self.padInstanceName = padInstanceName
|
||||
self.direction = 0
|
||||
self.nets = [ ]
|
||||
self.pads = [ ]
|
||||
return
|
||||
|
||||
|
||||
def __str__ ( self ):
|
||||
s = '<IoPad "%s" ' % self.padInstanceName
|
||||
for ioNet in self.nets:
|
||||
s += ' %s' % ioNet.coreNetName
|
||||
s += '>'
|
||||
return s
|
||||
|
||||
|
||||
def addNet ( self, ioNet ):
|
||||
self.nets.append( ioNet )
|
||||
if len(self.nets) == 1:
|
||||
if self.nets[0].coreNet.getDirection() == Net.Direction.IN: self.direction = IoPad.IN
|
||||
elif self.nets[0].coreNet.getDirection() == Net.Direction.OUT: self.direction = IoPad.OUT
|
||||
else:
|
||||
raise ErrorMessage( 1, 'IoPad.addNet(): Unsupported direction %d (%s) for core net "%s" in I/O pad \"%s\".' \
|
||||
% ( self.nets[0].coreNet.getDirection()
|
||||
, netDirectionToStr(self.nets[0].coreNet.getDirection())
|
||||
, self.nets[0].coreNet.getName()
|
||||
, self.padInstanceName ) )
|
||||
elif len(self.nets) == 2:
|
||||
self.direction = IoPad.TRI_OUT
|
||||
elif len(self.nets) == 3:
|
||||
self.direction = IoPad.BIDIR
|
||||
else:
|
||||
message = [ 'IoPad.addNet(): More than three core nets on I/O pad "%s".' % self.padInstanceName ]
|
||||
for ioNet in self.nets:
|
||||
message += [ "%s" % ioNet.coreNet ]
|
||||
raise ErrorMessage( 1, message )
|
||||
|
||||
return
|
||||
|
||||
|
||||
def createPad ( self ):
|
||||
fromCoreNet = None
|
||||
toCoreNet = None
|
||||
enableNet = None
|
||||
|
||||
for ioNet in self.nets:
|
||||
ioNet.buildNets()
|
||||
if self.direction == IoPad.TRI_OUT:
|
||||
if ioNet.isEnable(): enableNet = ioNet
|
||||
else: fromCoreNet = ioNet
|
||||
elif self.direction == IoPad.BIDIR:
|
||||
if ioNet.coreNet.getDirection() == Net.Direction.IN: toCoreNet = ioNet
|
||||
if ioNet.coreNet.getDirection() == Net.Direction.OUT:
|
||||
if ioNet.isEnable(): enableNet = ioNet
|
||||
else: fromCoreNet = ioNet
|
||||
else:
|
||||
fromCoreNet = ioNet
|
||||
|
||||
if not self.coreToChip.ioPadInfos.has_key(self.direction):
|
||||
raise ErrorMessage( 1, 'IoPad.createPad(): Unsupported direction %d (%s) for pad "%s".' \
|
||||
% (self.direction
|
||||
,IoPad.directionToStr(self.direction)
|
||||
,self.padInstanceName) )
|
||||
padInfo = self.coreToChip.ioPadInfos[ self.direction ]
|
||||
|
||||
self.pads.append( Instance.create( self.coreToChip.chip
|
||||
, self.padInstanceName
|
||||
, self.coreToChip.getCell(padInfo.name) ) )
|
||||
|
||||
CoreToChip._connect( self.pads[0], fromCoreNet.chipExtNet, padInfo.padNet )
|
||||
CoreToChip._connect( self.pads[0], fromCoreNet.chipIntNet, padInfo.coreNets[0] )
|
||||
|
||||
if toCoreNet: CoreToChip._connect( self.pads[0], toCoreNet.chipIntNet, padInfo.coreNets[-2] )
|
||||
if enableNet: CoreToChip._connect( self.pads[0], enableNet.chipIntNet, padInfo.coreNets[-1] )
|
||||
|
||||
self.coreToChip._connectRing( self.pads[0] )
|
||||
self.coreToChip.chipPads += self.pads
|
||||
return
|
||||
|
||||
|
||||
# -------------------------------------------------------------------
|
||||
# Class : "CoreToChip".
|
||||
|
||||
|
|
@ -147,8 +288,9 @@ class CoreToChip ( object ):
|
|||
return
|
||||
|
||||
def __init__ ( self, core ):
|
||||
self.conf = chip.Configuration.loadConfiguration( core )
|
||||
self.ringNetNames = [ ]
|
||||
self.ioPads = { }
|
||||
self.ioPadInfos = { }
|
||||
self.chipPads = [ ]
|
||||
self.padLib = None
|
||||
self.core = core
|
||||
|
|
@ -156,11 +298,29 @@ class CoreToChip ( object ):
|
|||
self.corona = None
|
||||
self.icorona = None
|
||||
self.icore = None
|
||||
self._ioNets = { }
|
||||
self.powerPadCount = 0
|
||||
self.groundPadCount = 0
|
||||
self.clockPadCount = 0
|
||||
return
|
||||
|
||||
|
||||
def hasIoNet ( self, netName ):
|
||||
if self._ioNets.has_key(netName): return True
|
||||
return False
|
||||
|
||||
|
||||
def getIoNet ( self, coreNet ):
|
||||
if isinstance(coreNet,str):
|
||||
if self._ioNets.has_key(coreNet): return self._ioNet[ coreNet ]
|
||||
raise ErrorMessage( 1, 'CoreToChip.getIoNet(): Cannot lookup net "%s" by name.' % coreNet )
|
||||
|
||||
if not self._ioNets.has_key(coreNet.getName()):
|
||||
self._ioNets[ coreNet.getName() ] = IoNet( self, coreNet )
|
||||
|
||||
return self._ioNets[ coreNet.getName() ]
|
||||
|
||||
|
||||
def _connectRing ( self, padInstance ):
|
||||
for ringNetName in self.ringNetNames:
|
||||
if isinstance(ringNetName,tuple):
|
||||
|
|
@ -179,12 +339,13 @@ class CoreToChip ( object ):
|
|||
return
|
||||
|
||||
def _buildStandardPad ( self, ioNet ):
|
||||
if not self.ioPads.has_key(ioNet.coreNet.getDirection()):
|
||||
raise ErrorMessage( 1, 'CoreToChip._buildStandardPad(): Unsupported direction %d for core net "%s".' \
|
||||
% (netDirectionToStr(ioNet.coreNet.getDirection())
|
||||
if not self.ioPadInfos.has_key(ioNet.coreNet.getDirection()):
|
||||
raise ErrorMessage( 1, 'CoreToChip._buildStandardPad(): Unsupported direction %d (%s) for core net "%s".' \
|
||||
% (ioNet.coreNet.getDirection()
|
||||
,netDirectionToStr(ioNet.coreNet.getDirection())
|
||||
,ioNet.coreNet.getName()) )
|
||||
|
||||
padInfo = self.ioPads[ ioNet.coreNet.getDirection() ]
|
||||
padInfo = self.ioPadInfos[ ioNet.coreNet.getDirection() ]
|
||||
|
||||
ioNet.pads.append( Instance.create( self.chip
|
||||
, ioNet.padInstanceName
|
||||
|
|
@ -204,29 +365,69 @@ class CoreToChip ( object ):
|
|||
def _buildClockPads ( self, ioNet ):
|
||||
raise ErrorMessage( 1, 'coreToChip._buildClockPads(): This method must be overloaded.' )
|
||||
|
||||
def buildChip ( self, chipName ):
|
||||
def buildChip ( self ):
|
||||
af = AllianceFramework.get()
|
||||
|
||||
UpdateSession.open()
|
||||
|
||||
self.chip = af.createCell( chipName )
|
||||
self.chip = af.createCell( self.conf.chipName )
|
||||
self.corona = af.createCell( 'corona' )
|
||||
self.icore = Instance.create( self.corona, 'core' , self.core )
|
||||
self.icorona = Instance.create( self.chip , 'corona', self.corona )
|
||||
|
||||
self._buildRingNets()
|
||||
|
||||
ioPads = [ ]
|
||||
clockIoNets = [ ]
|
||||
|
||||
for padConf in self.conf.padInstances:
|
||||
padConf.udata = IoPad( self, padConf.padInstanceName )
|
||||
|
||||
for netName in padConf.nets:
|
||||
coreNet = self.core.getNet(netName)
|
||||
if not coreNet:
|
||||
raise ErrorMessage( 1, 'CoreToChip.buildChip(): "%s" doesn\'t have a "%s" net.'
|
||||
% (self.core.getName(),netName) )
|
||||
ioNet = self.getIoNet( coreNet )
|
||||
ioNet.padNetName = padConf.padNetName
|
||||
|
||||
if padConf.isBidir() or padConf.isTristate():
|
||||
ioNet.setBidir( True )
|
||||
if coreNet.getName() == padConf.enableNet:
|
||||
ioNet.setEnable( True )
|
||||
|
||||
padConf.udata.addNet( ioNet )
|
||||
ioPads.append( padConf )
|
||||
|
||||
for coreNet in self.core.getNets():
|
||||
if not coreNet.isExternal(): continue
|
||||
|
||||
ioNet = IoNet( self, coreNet )
|
||||
ioNet.buildNets()
|
||||
# Case of special nets (power, ground & clocks).
|
||||
if coreNet.isPower():
|
||||
self._buildPowerPads( IoNet( self, coreNet ) )
|
||||
continue
|
||||
elif coreNet.isGround():
|
||||
self._buildGroundPads( IoNet( self, coreNet ) )
|
||||
continue
|
||||
elif coreNet.isClock():
|
||||
clockIoNets.append( IoNet( self, coreNet ) )
|
||||
continue
|
||||
|
||||
if coreNet.isPower(): self._buildPowerPads ( ioNet )
|
||||
elif coreNet.isGround(): self._buildGroundPads ( ioNet )
|
||||
elif coreNet.isClock(): clockIoNets.append( ioNet )
|
||||
else: self._buildStandardPad( ioNet )
|
||||
if self.hasIoNet(coreNet.getName()):
|
||||
continue
|
||||
|
||||
# Remaining non configured Standard I/O pads.
|
||||
ioNet = IoNet( self, coreNet )
|
||||
directPad = chip.Configuration.IoPadConf( [ ioNet.padInstanceName
|
||||
, ioNet.padNetName
|
||||
, ioNet.coreNetName
|
||||
] )
|
||||
directPad.udata = IoPad( self, directPad.padInstanceName )
|
||||
directPad.udata.addNet( ioNet )
|
||||
ioPads.append( directPad )
|
||||
|
||||
for ioPad in ioPads:
|
||||
ioPad.udata.createPad()
|
||||
|
||||
for clockIoNet in clockIoNets:
|
||||
self._buildClockPads( clockIoNet )
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ import Viewer
|
|||
from CRL import Catalog
|
||||
from CRL import AllianceFramework
|
||||
from helpers.io import ErrorMessage
|
||||
from core2chip.CoreToChip import IoPad
|
||||
from core2chip.CoreToChip import CoreToChip
|
||||
|
||||
|
||||
|
|
@ -34,8 +35,10 @@ class cmos ( CoreToChip ):
|
|||
def __init__ ( self, core ):
|
||||
CoreToChip.__init__ ( self, core )
|
||||
self.ringNetNames = [ 'vsse', 'vssi', 'vdde', 'vddi', ('cki', 'ck') ]
|
||||
self.ioPads = { Net.Direction.IN : CoreToChip.IoPadInfo( 'pi_px', 'pad', ['t',] )
|
||||
, Net.Direction.OUT : CoreToChip.IoPadInfo( 'po_px', 'pad', ['i',] )
|
||||
self.ioPadInfos = { IoPad.IN : CoreToChip.IoPadInfo( 'pi_px' , 'pad', ['t',] )
|
||||
, IoPad.OUT : CoreToChip.IoPadInfo( 'po_px' , 'pad', ['i',] )
|
||||
, IoPad.TRI_OUT : CoreToChip.IoPadInfo( 'pot_px' , 'pad', ['i', 'b' ] )
|
||||
, IoPad.BIDIR : CoreToChip.IoPadInfo( 'piot_px', 'pad', ['i', 't', 'b' ] )
|
||||
}
|
||||
self._getPadLib()
|
||||
return
|
||||
|
|
@ -68,6 +71,7 @@ class cmos ( CoreToChip ):
|
|||
return cell
|
||||
|
||||
def _buildGroundPads ( self, ioNet ):
|
||||
ioNet.buildNets()
|
||||
vssi = self.chip.getNet( 'vssi' )
|
||||
vssi.setExternal( True )
|
||||
vssi.setGlobal ( True )
|
||||
|
|
@ -82,22 +86,24 @@ class cmos ( CoreToChip ):
|
|||
vsse.merge( ioNet.chipExtNet )
|
||||
ioNet.chipExtNet = vsse
|
||||
|
||||
ioNet.pads.append( Instance.create( self.chip
|
||||
, ioNet.padInstanceName + '_i_%d' % self.groundPadCount
|
||||
, self.getCell('pvssick_px') ) )
|
||||
ioNet.pads.append( Instance.create( self.chip
|
||||
, ioNet.padInstanceName + '_o_%d' % self.groundPadCount
|
||||
, self.getCell('pvsseck_px') ) )
|
||||
pads = []
|
||||
pads.append( Instance.create( self.chip
|
||||
, 'p_' + ioNet.padInstanceName + 'ick_%d' % self.groundPadCount
|
||||
, self.getCell('pvssick_px') ) )
|
||||
pads.append( Instance.create( self.chip
|
||||
, 'p_' + ioNet.padInstanceName + 'eck_%d' % self.groundPadCount
|
||||
, self.getCell('pvsseck_px') ) )
|
||||
|
||||
CoreToChip._connect( ioNet.pads[0], ioNet.chipIntNet, 'vssi' )
|
||||
CoreToChip._connect( ioNet.pads[1], ioNet.chipExtNet, 'vsse' )
|
||||
CoreToChip._connect( pads[0], ioNet.chipIntNet, 'vssi' )
|
||||
CoreToChip._connect( pads[1], ioNet.chipExtNet, 'vsse' )
|
||||
|
||||
for pad in ioNet.pads: self._connectRing( pad )
|
||||
for pad in pads: self._connectRing( pad )
|
||||
self.groundPadCount += 1
|
||||
self.chipPads += ioNet.pads
|
||||
self.chipPads += pads
|
||||
return
|
||||
|
||||
def _buildPowerPads ( self, ioNet ):
|
||||
ioNet.buildNets()
|
||||
vddi = self.chip.getNet( 'vddi' )
|
||||
vddi.setExternal( True )
|
||||
vddi.setGlobal ( True )
|
||||
|
|
@ -112,31 +118,34 @@ class cmos ( CoreToChip ):
|
|||
vdde.merge( ioNet.chipExtNet )
|
||||
ioNet.chipExtNet = vdde
|
||||
|
||||
ioNet.pads.append( Instance.create( self.chip
|
||||
, ioNet.padInstanceName + '_i_%d' % self.powerPadCount
|
||||
, self.getCell('pvddick_px') ) )
|
||||
ioNet.pads.append( Instance.create( self.chip
|
||||
, ioNet.padInstanceName + '_o_%d' % self.powerPadCount
|
||||
, self.getCell('pvddeck_px') ) )
|
||||
pads = [ ]
|
||||
pads.append( Instance.create( self.chip
|
||||
, 'p_' + ioNet.padInstanceName + 'ick_%d' % self.powerPadCount
|
||||
, self.getCell('pvddick_px') ) )
|
||||
pads.append( Instance.create( self.chip
|
||||
, 'p_' + ioNet.padInstanceName + 'eck_%d' % self.powerPadCount
|
||||
, self.getCell('pvddeck_px') ) )
|
||||
|
||||
CoreToChip._connect( ioNet.pads[0], ioNet.chipIntNet, 'vddi' )
|
||||
CoreToChip._connect( ioNet.pads[1], ioNet.chipExtNet, 'vdde' )
|
||||
CoreToChip._connect( pads[0], ioNet.chipIntNet, 'vddi' )
|
||||
CoreToChip._connect( pads[1], ioNet.chipExtNet, 'vdde' )
|
||||
|
||||
for pad in ioNet.pads: self._connectRing( pad )
|
||||
for pad in pads: self._connectRing( pad )
|
||||
self.powerPadCount += 1
|
||||
self.chipPads += ioNet.pads
|
||||
self.chipPads += pads
|
||||
return
|
||||
|
||||
def _buildClockPads ( self, ioNet ):
|
||||
ioNet.pads.append( Instance.create( self.chip
|
||||
, ioNet.padInstanceName + '_%d' % self.clockPadCount
|
||||
, self.getCell('pck_px') ) )
|
||||
ioNet.buildNets()
|
||||
pads = [ ]
|
||||
pads.append( Instance.create( self.chip
|
||||
, 'p_' + ioNet.padInstanceName + '_%d' % self.clockPadCount
|
||||
, self.getCell('pck_px') ) )
|
||||
|
||||
CoreToChip._connect( ioNet.pads[0], ioNet.chipExtNet, 'pad' )
|
||||
CoreToChip._connect( pads[0], ioNet.chipExtNet, 'pad' )
|
||||
|
||||
for pad in ioNet.pads: self._connectRing( pad )
|
||||
for pad in pads: self._connectRing( pad )
|
||||
self.clockPadCount += 1
|
||||
self.chipPads += ioNet.pads
|
||||
self.chipPads += pads
|
||||
|
||||
p = re.compile( r'pv[ds]{2}[ei]ck_px' )
|
||||
for pad in self.chipPads:
|
||||
|
|
|
|||
Loading…
Reference in New Issue