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change names to be more compact or precise

This commit is contained in:
Roselyne Chotin 2012-11-13 19:05:27 +00:00
parent 773a4b7d97
commit 708aca610e
7 changed files with 32 additions and 46 deletions
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10
stratus1/src/stratus/st_comp.py
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@ -97,8 +97,8 @@ class Comp ( Model ) :
if self.nbit > 1 : if self.nbit > 1 :
if self.egal : if self.egal :
Generate ( "st_comp.BoolToOne", "bool_to_one_%s_%dbits" % ( "nor", tempXor._arity ), param = { 'nbit' : tempXor._arity, 'func' : "Nor" } ) Generate ( "st_comp.BoolToOne", "bto1_%s_%d" % ( "nor", tempXor._arity ), param = { 'nbit' : tempXor._arity, 'func' : "Nor" } )
Inst ( "bool_to_one_%s_%dbits" % ( "nor", tempXor._arity ) Inst ( "bto1_%s_%d" % ( "nor", tempXor._arity )
, map = { 'i' : tempXor , map = { 'i' : tempXor
, 'q' : self.netOut , 'q' : self.netOut
, 'vdd' : self.vdd , 'vdd' : self.vdd
@ -106,8 +106,8 @@ class Comp ( Model ) :
} }
) )
else : else :
Generate ( "st_comp.BoolToOne", "bool_to_one_%s_%dbits" % ( "or", tempXor._arity ), param = { 'nbit' : tempXor._arity, 'func' : "Or" } ) Generate ( "st_comp.BoolToOne", "bto1_%s_%d" % ( "or", tempXor._arity ), param = { 'nbit' : tempXor._arity, 'func' : "Or" } )
Inst ( "bool_to_one_%s_%dbits" % ( "or", tempXor._arity ) Inst ( "bto1_%s_%d" % ( "or", tempXor._arity )
, map = { 'i' : tempXor , map = { 'i' : tempXor
, 'q' : self.netOut , 'q' : self.netOut
, 'vdd' : self.vdd , 'vdd' : self.vdd
@ -184,7 +184,7 @@ class BoolToOne ( Model ) :
modelName += "_" modelName += "_"
modelName += str(param['nbit']) modelName += str(param['nbit'])
modelName += "bits_to one" modelName += "bto1"
return modelName return modelName

8
stratus1/src/stratus/st_const.py
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@ -66,14 +66,14 @@ def One ( nbit ) :
if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n" if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n"
num_net = len ( cell._TAB_NETS_OUT ) num_net = len ( cell._TAB_NETS_OUT )
cell._TAB_NETS_OUT += [Signal ( "one_%d" % num_net, nbit )] cell._TAB_NETS_OUT += [Signal ( "one_s%d" % num_net, nbit )]
# "1 bit constant" => directly instanciate the virtual cell "One" cell # "1 bit constant" => directly instanciate the virtual cell "One" cell
# "> 1 bit constant" => generate a model # "> 1 bit constant" => generate a model
# if nbit == 1: # if nbit == 1:
# inst_name = "one" # inst_name = "one"
# else: # else:
inst_name = "one_%dbits" % nbit inst_name = "one_%d" % nbit
Generate ( "One", inst_name, param = { 'nbit' : nbit } ) Generate ( "One", inst_name, param = { 'nbit' : nbit } )
Inst ( inst_name Inst ( inst_name
, map = { 'q' : cell._TAB_NETS_OUT[num_net] , map = { 'q' : cell._TAB_NETS_OUT[num_net]
@ -94,14 +94,14 @@ def Zero ( nbit ) :
if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n" if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise "\n[Stratus ERROR] : there is no alim.\n"
num_net = len ( cell._TAB_NETS_OUT ) num_net = len ( cell._TAB_NETS_OUT )
cell._TAB_NETS_OUT += [Signal ( "zero_%d" % num_net, nbit )] cell._TAB_NETS_OUT += [Signal ( "zero_s%d" % num_net, nbit )]
# "1 bit constant" => directly instanciate the virtual cell "Zero" cell # "1 bit constant" => directly instanciate the virtual cell "Zero" cell
# "> 1 bit constant" => generate a model # "> 1 bit constant" => generate a model
# if nbit == 1: # if nbit == 1:
# inst_name = "zero" # inst_name = "zero"
# else: # else:
inst_name = "zero_%dbits" % nbit inst_name = "zero_%d" % nbit
Generate ( "Zero", inst_name, param = { 'nbit' : nbit } ) Generate ( "Zero", inst_name, param = { 'nbit' : nbit } )
Inst ( inst_name Inst ( inst_name
, map = { 'nq' : cell._TAB_NETS_OUT[num_net] , map = { 'nq' : cell._TAB_NETS_OUT[num_net]

2
stratus1/src/stratus/st_instance.py
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@ -121,7 +121,7 @@ class Inst :
##### Name of the instance ###### ##### Name of the instance ######
if not name : if not name :
name = "instance%d_%s" % ( cell._NB_INST, self._model ) name = "%s_i%d" % ( self._model, cell._NB_INST )
cell._NB_INST += 1 cell._NB_INST += 1
self._name = name self._name = name

10
stratus1/src/stratus/st_mux.py
View File

@ -90,8 +90,8 @@ class Smux ( Model ) :
for i in range ( nbit_cmd - 1, -1, -1 ) : for i in range ( nbit_cmd - 1, -1, -1 ) :
for j in range ( int(pow ( 2, i )) ) : for j in range ( int(pow ( 2, i )) ) :
Generate ( "Mx2", "mux_%dbits" % nbit, param = { 'nbit' : nbit } ) Generate ( "Mx2", "mux_%d" % nbit, param = { 'nbit' : nbit } )
Inst ( "mux_%dbits" % nbit Inst ( "mux_%d" % nbit
, map = { 'i0' : temp[2*j+bit_entree] , map = { 'i0' : temp[2*j+bit_entree]
, 'i1' : temp[2*j+1+bit_entree] , 'i1' : temp[2*j+1+bit_entree]
, 'cmd' : self._cmd[bit_cmd] , 'cmd' : self._cmd[bit_cmd]
@ -110,8 +110,8 @@ class Smux ( Model ) :
# If the command is a 1 bit net # If the command is a 1 bit net
############################### ###############################
else : else :
Generate ( "Mx2", "mux_%dbits" % nbit, param = { 'nbit' : nbit } ) Generate ( "Mx2", "mux_%d" % nbit, param = { 'nbit' : nbit } )
Inst ( "mux_%dbits" % nbit Inst ( "mux_%d" % nbit
, map = { 'i0' : self._in_tab[0] , map = { 'i0' : self._in_tab[0]
, 'i1' : self._in_tab[1] , 'i1' : self._in_tab[1]
, 'cmd' : self._cmd , 'cmd' : self._cmd
@ -127,11 +127,9 @@ class Smux ( Model ) :
modelName += "_" modelName += "_"
modelName += str(param['nbit']) modelName += str(param['nbit'])
modelName += "bits"
modelName += "_" modelName += "_"
modelName += str(param['nbit_cmd']) modelName += str(param['nbit_cmd'])
modelName += "cmdbits"
return modelName return modelName

33
stratus1/src/stratus/st_net.py
View File

@ -163,7 +163,7 @@ class net :
string = Constant.getString ( constParam ) string = Constant.getString ( constParam )
num_net = len ( cell._TAB_NETS_OUT ) num_net = len ( cell._TAB_NETS_OUT )
cell._TAB_NETS_OUT += [Signal ( "constant_%d" % num_net, len ( string ) )] cell._TAB_NETS_OUT += [Signal ( "cst_o%d" % num_net, len ( string ) )]
# 3 possible constant operator output name (nq,q,output) => 3 differents map # 3 possible constant operator output name (nq,q,output) => 3 differents map
if string == "0" : if string == "0" :
@ -250,7 +250,7 @@ class net :
# Creation of the output net with the right size # Creation of the output net with the right size
num_net = len ( cell._TAB_NETS_OUT ) num_net = len ( cell._TAB_NETS_OUT )
cell._TAB_NETS_OUT += [Signal ( "net_outbuf_%d" % num_net, self._arity )] cell._TAB_NETS_OUT += [Signal ( "buf_o%d" % num_net, self._arity )]
buffMap = { 'q' : cell._TAB_NETS_OUT[num_net] buffMap = { 'q' : cell._TAB_NETS_OUT[num_net]
, 'vdd' : cell._st_vdds[0] , 'vdd' : cell._st_vdds[0]
@ -267,7 +267,6 @@ class net :
inst_name = re.sub ( "\.", "_", inst_name ) inst_name = re.sub ( "\.", "_", inst_name )
inst_name += "_" inst_name += "_"
inst_name += str(self._arity) inst_name += str(self._arity)
inst_name += "bits"
Generate ( self._st_cell._buff, inst_name, param = { 'nbit' : self._arity } ) Generate ( self._st_cell._buff, inst_name, param = { 'nbit' : self._arity } )
@ -295,7 +294,7 @@ class net :
# Creation of the output net with the right size # Creation of the output net with the right size
num_net = len ( cell._TAB_NETS_OUT ) num_net = len ( cell._TAB_NETS_OUT )
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, self._arity )] cell._TAB_NETS_OUT += [Signal ( "bool_o%d" % num_net, self._arity )]
if not ( cell._st_vdds ) or not ( cell._st_vsss ) : if not ( cell._st_vdds ) or not ( cell._st_vsss ) :
err = "\n[Stratus ERROR] : there is no alim.\n" err = "\n[Stratus ERROR] : there is no alim.\n"
@ -309,7 +308,6 @@ class net :
inst_name = re.sub ( "\.", "_", inst_name ) inst_name = re.sub ( "\.", "_", inst_name )
inst_name += "_" inst_name += "_"
inst_name += str(self._arity) inst_name += str(self._arity)
inst_name += "bits"
Generate ( model, inst_name, param = { 'nbit' : self._arity } ) Generate ( model, inst_name, param = { 'nbit' : self._arity } )
@ -336,7 +334,7 @@ class net :
# Creation of the output net with the right size # Creation of the output net with the right size
num_net = len ( cell._TAB_NETS_OUT ) num_net = len ( cell._TAB_NETS_OUT )
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, self._arity )] cell._TAB_NETS_OUT += [Signal ( "inv_o%d" % num_net, self._arity )]
invMap = { 'nq' : cell._TAB_NETS_OUT[num_net] invMap = { 'nq' : cell._TAB_NETS_OUT[num_net]
, 'vdd' : cell._st_vdds[0] , 'vdd' : cell._st_vdds[0]
@ -352,7 +350,6 @@ class net :
inst_name = re.sub ( "\.", "_", inst_name ) inst_name = re.sub ( "\.", "_", inst_name )
inst_name += "_" inst_name += "_"
inst_name += str(self._arity) inst_name += str(self._arity)
inst_name += "bits"
Generate ( self._st_cell._not, inst_name, param = { 'nbit' : self._arity } ) Generate ( self._st_cell._not, inst_name, param = { 'nbit' : self._arity } )
@ -385,15 +382,15 @@ class net :
if function == self._st_cell._add : if function == self._st_cell._add :
if self._st_cell._extended : if self._st_cell._extended :
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, max ( self._arity, other_net._arity )+1 )] cell._TAB_NETS_OUT += [Signal ( "add_o%d" % num_net, max ( self._arity, other_net._arity )+1 )]
else: else:
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, max ( self._arity, other_net._arity ) )] cell._TAB_NETS_OUT += [Signal ( "add_o%d" % num_net, max ( self._arity, other_net._arity ) )]
elif function == self._st_cell._sub : elif function == self._st_cell._sub :
if self._st_cell._extended : if self._st_cell._extended :
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, max ( self._arity, other_net._arity )+1 )] cell._TAB_NETS_OUT += [Signal ( "sub_o%d" % num_net, max ( self._arity, other_net._arity )+1 )]
else: else:
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, max ( self._arity, other_net._arity ) )] cell._TAB_NETS_OUT += [Signal ( "sub_o%d" % num_net, max ( self._arity, other_net._arity ) )]
elif function == self._st_cell._mult : cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, self._arity+other_net._arity )] elif function == self._st_cell._mult : cell._TAB_NETS_OUT += [Signal ( "mul_o%d" % num_net, self._arity+other_net._arity )]
arithParam = parameter arithParam = parameter
if not self._st_cell._signed and function == self._st_cell._mult : if not self._st_cell._signed and function == self._st_cell._mult :
@ -451,7 +448,7 @@ class net :
# Creation of the output net with the right size # Creation of the output net with the right size
num_net = len ( cell._TAB_NETS_OUT ) num_net = len ( cell._TAB_NETS_OUT )
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, inputNet._arity )] cell._TAB_NETS_OUT += [Signal ( "sh_o%d" % num_net, inputNet._arity )]
# Initialisation of shiftType # Initialisation of shiftType
if direction is "left" : if direction is "left" :
@ -469,7 +466,6 @@ class net :
inst_name += type inst_name += type
inst_name += "_" inst_name += "_"
inst_name += str(inputNet._arity) inst_name += str(inputNet._arity)
inst_name += "bits"
Generate ( self._st_cell._shift, inst_name, param = { 'nbit' : inputNet._arity, 'type' : shiftType } ) Generate ( self._st_cell._shift, inst_name, param = { 'nbit' : inputNet._arity, 'type' : shiftType } )
Inst ( inst_name Inst ( inst_name
@ -496,7 +492,7 @@ class net :
# Creation of the output net with the right size # Creation of the output net with the right size
num_net = len ( cell._TAB_NETS_OUT ) num_net = len ( cell._TAB_NETS_OUT )
cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, inputNet._arity )] cell._TAB_NETS_OUT += [Signal ( "reg_o%d" % num_net, inputNet._arity )]
# if ( self._st_cell._reg == "Sff1" ) and ( inputNet._arity == 1 ) : # if ( self._st_cell._reg == "Sff1" ) and ( inputNet._arity == 1 ) :
# inst_name = "sff1" # inst_name = "sff1"
@ -505,7 +501,6 @@ class net :
# inst_name = re.sub ( "\.", "_", inst_name ) # inst_name = re.sub ( "\.", "_", inst_name )
# inst_name += "_" # inst_name += "_"
# inst_name += str(inputNet._arity) # inst_name += str(inputNet._arity)
# inst_name += "bits"
# #
# Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } ) # Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } )
@ -513,7 +508,6 @@ class net :
inst_name = re.sub ( "\.", "_", inst_name ) inst_name = re.sub ( "\.", "_", inst_name )
inst_name += "_" inst_name += "_"
inst_name += str(inputNet._arity) inst_name += str(inputNet._arity)
inst_name += "bits"
Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } ) Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } )
@ -736,10 +730,8 @@ class net :
inst_name = re.sub ( "\.", "_", inst_name ) inst_name = re.sub ( "\.", "_", inst_name )
inst_name += "_" inst_name += "_"
inst_name += str(long) inst_name += str(long)
inst_name += "bits"
inst_name += "_" inst_name += "_"
inst_name += str(self._arity) inst_name += str(self._arity)
inst_name += "cmd"
Generate ( self._st_cell._mux, inst_name, param = { 'nbit' : long, 'nbit_cmd' : self._arity } ) Generate ( self._st_cell._mux, inst_name, param = { 'nbit' : long, 'nbit_cmd' : self._arity } )
Inst ( inst_name, map = map_mux ) Inst ( inst_name, map = map_mux )
@ -768,10 +760,9 @@ class net :
inst_name = re.sub ( "\.", "_", inst_name ) inst_name = re.sub ( "\.", "_", inst_name )
inst_name += "_" inst_name += "_"
inst_name += str(self._arity) inst_name += str(self._arity)
inst_name += "bits"
inst_name += "_" inst_name += "_"
inst_name += str(nb) inst_name += str(nb)
if egal : inst_name += "egal" if egal : inst_name += "eq"
Generate ( self._st_cell._comp, inst_name, param = { 'nbit' : self._arity, 'nb' : nb, 'egal' : egal } ) Generate ( self._st_cell._comp, inst_name, param = { 'nbit' : self._arity, 'nb' : nb, 'egal' : egal } )
Inst ( inst_name Inst ( inst_name

13
stratus1/src/stratus/st_shifter.py
View File

@ -199,14 +199,13 @@ class Shifter ( Model ) :
modelName += "_" modelName += "_"
modelName += str(param['nbit']) modelName += str(param['nbit'])
modelName += "bits"
if param['type'] == 0x12 : modelName += "_logical_left" if param['type'] == 0x12 : modelName += "_ll"
elif param['type'] == 0xa : modelName += "_arith_left" elif param['type'] == 0xa : modelName += "_al"
elif param['type'] == 0x6 : modelName += "_circular_left" elif param['type'] == 0x6 : modelName += "_cl"
elif param['type'] == 0x11 : modelName += "_logical_right" elif param['type'] == 0x11 : modelName += "_lr"
elif param['type'] == 0x9 : modelName += "_arith_right" elif param['type'] == 0x9 : modelName += "_ar"
elif param['type'] == 0x5 : modelName += "_circular_right" elif param['type'] == 0x5 : modelName += "_cr"
return modelName return modelName

2
stratus1/src/stratus/st_slansky.py
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@ -204,8 +204,6 @@ class Slansky ( Model ) :
if param['nbit0'] != param['nbit1'] : name += '_%dx%d' % (param['nbit0'], param['nbit1']) if param['nbit0'] != param['nbit1'] : name += '_%dx%d' % (param['nbit0'], param['nbit1'])
else : name += '_%d' % (param['nbit0']) else : name += '_%d' % (param['nbit0'])
name += "bits"
if ('cin' in param) and (param['cin']) : name += '_cin' if ('cin' in param) and (param['cin']) : name += '_cin'
return name return name