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In OpenChams parser / driver : 

- remove callOrder member on Operator
    - add order on Instance (to order Devices and Subcircuits)
    - update python interface
    - update C++/Python parse/drive examples
This commit is contained in:
Damien Dupuis 2011-07-21 09:20:20 +00:00
parent 63f578ccdb
commit 631d636d2c
17 changed files with 59 additions and 58 deletions
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8
vlsisapd/examples/openChams/cplusplus/driveOpenChams.cpp
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@ -30,7 +30,7 @@ int main(int argc, char * argv[]) {
OpenChams::Netlist* netlist = circuit->createNetlist();
// instances
// nmos1
OpenChams::Device* inst_nmos1 = netlist->addDevice(OpenChams::Name("nmos1"), OpenChams::Name("Transistor"), OpenChams::Name("NMOS"), true);
OpenChams::Device* inst_nmos1 = netlist->addDevice(OpenChams::Name("nmos1"), OpenChams::Name("Transistor"), 1, OpenChams::Name("NMOS"), true);
inst_nmos1->addConnector(OpenChams::Name("G"));
inst_nmos1->addConnector(OpenChams::Name("S"));
inst_nmos1->addConnector(OpenChams::Name("D"));
@ -40,7 +40,7 @@ int main(int argc, char * argv[]) {
tr_nmos1->setDrain (OpenChams::Name("D"));
tr_nmos1->setBulk (OpenChams::Name("S"));
// pmos1
OpenChams::Device* inst_pmos1 = netlist->addDevice(OpenChams::Name("pmos1"), OpenChams::Name("Transistor"), OpenChams::Name("PMOS"), true);
OpenChams::Device* inst_pmos1 = netlist->addDevice(OpenChams::Name("pmos1"), OpenChams::Name("Transistor"), 2, OpenChams::Name("PMOS"), true);
inst_pmos1->addConnector(OpenChams::Name("G"));
inst_pmos1->addConnector(OpenChams::Name("S"));
inst_pmos1->addConnector(OpenChams::Name("D"));
@ -90,14 +90,14 @@ int main(int argc, char * argv[]) {
// sizing
OpenChams::Sizing* sizing = circuit->createSizing();
OpenChams::Operator* op_pmos1 = sizing->addOperator(OpenChams::Name("pmos1"), OpenChams::Name("OPVG(Veg)"), OpenChams::Name("BSIM3V3"), 0);
OpenChams::Operator* op_pmos1 = sizing->addOperator(OpenChams::Name("pmos1"), OpenChams::Name("OPVG(Veg)"), OpenChams::Name("BSIM3V3"));
op_pmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
op_pmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids") );
op_pmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L") );
op_pmos1->addConstraint(OpenChams::Name("Veg") , OpenChams::Name("design"), OpenChams::Name("Veg") );
op_pmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("design"), OpenChams::Name("Vdd") , 0.5);
op_pmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd") );
OpenChams::Operator* op_nmos1 = sizing->addOperator(OpenChams::Name("nmos1"), OpenChams::Name("OPW(Vg,Vs)"), OpenChams::Name("BSIM3V3"), 1);
OpenChams::Operator* op_nmos1 = sizing->addOperator(OpenChams::Name("nmos1"), OpenChams::Name("OPW(Vg,Vs)"), OpenChams::Name("BSIM3V3"));
op_nmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
op_nmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids" ));
op_nmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L" ));

6
vlsisapd/examples/openChams/cplusplus/parseOpenChams.cpp
View File

@ -59,9 +59,9 @@ int main(int argc, char * argv[]) {
OpenChams::Device* dev = NULL;
if (dynamic_cast<OpenChams::Device*>(inst)) {
dev = static_cast<OpenChams::Device*>(inst);
cerr << " | | + " << dev->getName().getString() << " : " << dev->getModel().getString() << " - " << dev->getMosType().getString() << " - " << (dev->isSourceBulkConnected()?"true":"false") << endl;
cerr << " | | + " << dev->getName().getString() << " : " << dev->getModel().getString() << " - " << dev->getOrder() << " - " << dev->getMosType().getString() << " - " << (dev->isSourceBulkConnected()?"true":"false") << endl;
} else {
cerr << " | | + " << inst->getName().getString() << " : " << inst->getModel().getString() << endl;
cerr << " | | + " << inst->getName().getString() << " : " << inst->getModel().getString() << " - " << inst->getOrder() << endl;
}
cerr << " | | | + connectors" << endl;
for (map<OpenChams::Name, OpenChams::Net*>::const_iterator cit = inst->getConnectors().begin() ; cit != inst->getConnectors().end() ; ++cit) {
@ -149,7 +149,7 @@ int main(int argc, char * argv[]) {
if (!sizing->hasNoOperators()) {
for (map<OpenChams::Name, OpenChams::Operator*>::const_iterator oit = sizing->getOperators().begin() ; oit != sizing->getOperators().end() ; ++oit) {
OpenChams::Operator* op = (*oit).second;
cerr << " | + instance name: " << ((*oit).first).getString() << " - operator: " << op->getName().getString() << " - simulModel: " << op->getSimulModel().getString() << " - callOrder: " << op->getCallOrder() << endl;
cerr << " | + instance name: " << ((*oit).first).getString() << " - operator: " << op->getName().getString() << " - simulModel: " << op->getSimulModel().getString() << endl;
if (!op->hasNoConstraints()) {
for (map<OpenChams::Name, OpenChams::Operator::Constraint*>::const_iterator cit = op->getConstraints().begin() ; cit != op->getConstraints().end() ; ++cit) {
OpenChams::Operator::Constraint* cstr = (*cit).second;

8
vlsisapd/examples/openChams/inverter.xml
View File

@ -11,7 +11,7 @@
</parameters>
<netlist>
<instances>
<instance name="nmos1" model="Transistor" mostype="NMOS" sourceBulkConnected="True">
<instance name="nmos1" model="Transistor" order="1" mostype="NMOS" sourceBulkConnected="True">
<connectors>
<connector name="G"/>
<connector name="D"/>
@ -23,7 +23,7 @@
</transistor>
</transistors>
</instance>
<instance name="pmos1" model="Transistor" mostype="PMOS" sourceBulkConnected="True">
<instance name="pmos1" model="Transistor" order="2" mostype="PMOS" sourceBulkConnected="True">
<connectors>
<connector name="G"/>
<connector name="D"/>
@ -95,7 +95,7 @@
</net>
</schematic>
<sizing>
<instance name="pmos1" operator="OPVG(Veg)" simulModel="BSIM3V3" callOrder="0">
<instance name="pmos1" operator="OPVG(Veg)" simulModel="BSIM3V3">
<constraint param="Temp" ref="design" refParam="temp"/>
<constraint param="Ids" ref="design" refParam="Ids"/>
<constraint param="L" ref="design" refParam="L"/>
@ -103,7 +103,7 @@
<constraint param="Vd" ref="design" refParam="Vdd" factor="0.5"/>
<constraint param="Vs" ref="design" refParam="Vdd"/>
</instance>
<instance name="nmos1" operator="OPW(Vg,Vs)" simulModel="BSIM3V3" callOrder="1">
<instance name="nmos1" operator="OPW(Vg,Vs)" simulModel="BSIM3V3">
<constraint param="Temp" ref="design" refParam="temp"/>
<constraint param="Ids" ref="design" refParam="Ids"/>
<constraint param="L" ref="design" refParam="L"/>

8
vlsisapd/examples/openChams/python/driveOpenChams.py
View File

@ -15,7 +15,7 @@ circuit.addParameter(Name("complex"), "myEq")
netlist = circuit.createNetlist()
# instances
# nmos1
inst_nmos1 = netlist.addDevice("nmos1", "Transistor", "NMOS", True)
inst_nmos1 = netlist.addDevice("nmos1", "Transistor", 1, "NMOS", True)
inst_nmos1.addConnector("G")
inst_nmos1.addConnector("S")
inst_nmos1.addConnector("D")
@ -25,7 +25,7 @@ tr_nmos1.source = "S"
tr_nmos1.drain = "D"
tr_nmos1.bulk = "S"
# pmos1
inst_pmos1 = netlist.addDevice("pmos1", "Transistor", "PMOS", True)
inst_pmos1 = netlist.addDevice("pmos1", "Transistor", 2, "PMOS", True)
inst_pmos1.addConnector("G")
inst_pmos1.addConnector("S")
inst_pmos1.addConnector("D")
@ -73,14 +73,14 @@ wireOut1.setStartPoint("nmos1", "D")
wireOut1.setEndPoint (0)
# sizing
sizing = circuit.createSizing()
op_pmos1 = sizing.addOperator("pmos1", "OPVG(Veg)" , "BSIM3V3", 0)
op_pmos1 = sizing.addOperator("pmos1", "OPVG(Veg)" , "BSIM3V3")
op_pmos1.addConstraint("Temp", "design", "temp")
op_pmos1.addConstraint("Ids" , "design", "Ids" )
op_pmos1.addConstraint("L" , "design", "L" )
op_pmos1.addConstraint("Veg" , "design", "Veg" )
op_pmos1.addConstraint("Vd" , "design", "Vdd", 0.5)
op_pmos1.addConstraint("Vs" , "design", "Vdd" )
op_nmos1 = sizing.addOperator("nmos1", "OPW(Vg,Vs)", "BSIM3V3", 1)
op_nmos1 = sizing.addOperator("nmos1", "OPW(Vg,Vs)", "BSIM3V3")
op_nmos1.addConstraint("Temp", "design", "temp")
op_nmos1.addConstraint("Ids" , "design", "Ids" )
op_nmos1.addConstraint("L" , "design", "L" )

6
vlsisapd/examples/openChams/python/parseOpenChams.py
View File

@ -16,9 +16,9 @@ def printContents(circuit):
print " | + instances"
for instance in circuit.netlist.getInstances():
if isinstance(instance, Device):
print " | | +", instance.name, ":", instance.model, instance.mosType, instance.sourceBulkConnected
print " | | +", instance.name, ":", instance.model, instance.order, instance.mosType, instance.sourceBulkConnected
else:
print " | | +", instance.name, ":", instance.model
print " | | +", instance.name, ":", instance.model, instance.order
print " | | | + connectors"
for conn in instance.getConnectors():
print " | | | |", conn.key, ":", conn.value.name
@ -67,7 +67,7 @@ def printContents(circuit):
if (circuit.sizing):
print " + sizing"
for op in circuit.sizing.getOperators():
print " | + instance name:", op.key, "- operator:", op.value.name, "- simulModel:", op.value.simulModel, "- callOrder:", op.value.callOrder
print " | + instance name:", op.key, "- operator:", op.value.name, "- simulModel:", op.value.simulModel
for constraint in op.value.getConstraints():
print " | | + param:", constraint.key, "- ref:", constraint.value.ref, "- refParam:", constraint.value.refParam, "- factor:", constraint.value.factor
print " | + equations"

31
vlsisapd/src/openChams/src/Circuit.cpp
View File

@ -319,28 +319,31 @@ void Circuit::readInstances(xmlNode* node, Netlist* netlist) {
Instance* Circuit::readInstance(xmlNode* node, Netlist* netlist) {
xmlChar* iNameC = xmlGetProp(node, (xmlChar*)"name");
xmlChar* iModelC = xmlGetProp(node, (xmlChar*)"model");
xmlChar* iOrderC = xmlGetProp(node, (xmlChar*)"order");
xmlChar* iMOSC = xmlGetProp(node, (xmlChar*)"mostype");
xmlChar* iSBCC = xmlGetProp(node, (xmlChar*)"sourceBulkConnected");
Instance* inst = NULL;
if (iNameC && iModelC && iMOSC && iSBCC) { // this is a device
if (iNameC && iModelC && iOrderC && iMOSC && iSBCC) { // this is a device
Name instanceName((const char*)iNameC);
Name modelName((const char*)iModelC);
unsigned order = ::getValue<unsigned>(iOrderC);
string mosStr((const char*)iMOSC);
string mosComp[2] = {"NMOS", "PMOS"};
vector<string> mosComps (mosComp, mosComp+2);
check_uppercase(mosStr, mosComps, "[ERROR] In 'instance', 'mostype' must be 'NMOS' or 'PMOS'.");
check_uppercase(mosStr, mosComps, "[ERROR] In 'instance', 'mostype' property must be 'NMOS' or 'PMOS'.");
string sourceBulkStr((const char*)iSBCC);
string sbcComp[4] = {"true", "false", "on", "off"};
vector<string> sbcComps(sbcComp, sbcComp+4);
check_lowercase(sourceBulkStr, sbcComps, "[ERROR] In 'instance', 'sourceBulkConnected' must 'true', 'false', 'on' or 'off'.");
check_lowercase(sourceBulkStr, sbcComps, "[ERROR] In 'instance', 'sourceBulkConnected' property must be 'true', 'false', 'on' or 'off'.");
bool sourceBulkConnected = ((sourceBulkStr == "true") || (sourceBulkStr == "on")) ? true : false;
inst = (Instance*)netlist->addDevice(instanceName, modelName, Name(mosStr), sourceBulkConnected);
} else if (iNameC && iModelC && !iMOSC && !iSBCC) { // this is a subcircuit
inst = (Instance*)netlist->addDevice(instanceName, modelName, order, Name(mosStr), sourceBulkConnected);
} else if (iNameC && iModelC && iOrderC && !iMOSC && !iSBCC) { // this is a subcircuit
Name instanceName((const char*)iNameC);
Name modelName((const char*)iModelC);
inst = netlist->addInstance(instanceName, modelName);
unsigned order = ::getValue<unsigned>(iOrderC);
inst = netlist->addInstance(instanceName, modelName, order);
} else {
throw OpenChamsException("[ERROR] 'instance' node must have ('name' and 'model') or ('name', 'model', 'mostype' and 'sourceBulkConnected') properties.");
throw OpenChamsException("[ERROR] 'instance' node must have ('name', 'model' and 'order') or ('name', 'model', 'order', 'mostype' and 'sourceBulkConnected') properties.");
//return inst;
}
@ -705,15 +708,13 @@ void Circuit::readInstanceSizing(xmlNode* node, Sizing* sizing) {
xmlChar* nameC = xmlGetProp(node, (xmlChar*)"name");
xmlChar* operatorC = xmlGetProp(node, (xmlChar*)"operator");
xmlChar* simulModC = xmlGetProp(node, (xmlChar*)"simulModel");
xmlChar* orderC = xmlGetProp(node, (xmlChar*)"callOrder");
if (nameC && operatorC && simulModC && orderC) {
if (nameC && operatorC && simulModC) {
Name iName ((const char*)nameC);
string opStr ((const char*)operatorC);
transform(opStr.begin(), opStr.end(), opStr.begin(), ::toupper);
Name opName (opStr);
Name simulMod((const char*)simulModC);
unsigned callOrder = ::getValue<unsigned>(orderC);
Operator* op = sizing->addOperator(iName, opName, simulMod, callOrder);
Operator* op = sizing->addOperator(iName, opName, simulMod);
xmlNode* child = node->children;
for (xmlNode* node = child; node; node = node->next) {
if (node->type == XML_ELEMENT_NODE) {
@ -726,7 +727,7 @@ void Circuit::readInstanceSizing(xmlNode* node, Sizing* sizing) {
}
} else {
throw OpenChamsException("[ERROR] 'instance' node in 'sizing' must have 'name', 'operator', 'simulModel' and 'callOrder' properties.");
throw OpenChamsException("[ERROR] 'instance' node in 'sizing' must have 'name', 'operator' and 'simulModel' properties.");
}
}
@ -1007,9 +1008,9 @@ bool Circuit::writeToFile(string filePath) {
}
if (dev) {
string sourceBulkStr = (dev->isSourceBulkConnected()) ? "True" : "False";
file << " <instance name=\"" << dev->getName().getString() << "\" model=\"" << dev->getModel().getString() << "\" mostype=\"" << dev->getMosType().getString() << "\" sourceBulkConnected=\"" << sourceBulkStr << "\">" << endl;
file << " <instance name=\"" << dev->getName().getString() << "\" model=\"" << dev->getModel().getString() << "\" mostype=\"" << dev->getMosType().getString() << "\" sourceBulkConnected=\"" << sourceBulkStr << "\" order=\"" << dev->getOrder() << "\">" << endl;
} else {
file << " <instance name=\"" << inst->getName().getString() << "\" model=\"" << inst->getModel().getString() << "\">" << endl;
file << " <instance name=\"" << inst->getName().getString() << "\" model=\"" << inst->getModel().getString() << "\" order=\"" << inst->getOrder() << "\">" << endl;
}
file << " <connectors>" << endl;
for (map<Name, Net*>::const_iterator it = inst->getConnectors().begin() ; it != inst->getConnectors().end() ; ++it) {
@ -1124,7 +1125,7 @@ bool Circuit::writeToFile(string filePath) {
Operator* op = (*it).second;
string opName = op->getName().getString();
transform(opName.begin(), opName.end(), opName.begin(), ::toupper);
file << " <instance name=\"" << ((*it).first).getString() << "\" operator=\"" << opName << "\" simulModel=\"" << op->getSimulModel().getString() << "\" callOrder=\"" << op->getCallOrder() << "\">" << endl;
file << " <instance name=\"" << ((*it).first).getString() << "\" operator=\"" << opName << "\" simulModel=\"" << op->getSimulModel().getString() << "\">" << endl;
if (!op->hasNoConstraints()) {
for (map<Name, Operator::Constraint*>::const_iterator cit = op->getConstraints().begin() ; cit != op->getConstraints().end() ; ++cit) {
Operator::Constraint* cn = (*cit).second;

4
vlsisapd/src/openChams/src/Device.cpp
View File

@ -16,8 +16,8 @@ using namespace std;
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Device::Device(Name name, Name model, Name mosType, bool sourceBulkConnected, Netlist* netlist)
: Instance(name, model, netlist)
Device::Device(Name name, Name model, unsigned order, Name mosType, bool sourceBulkConnected, Netlist* netlist)
: Instance(name, model, order, netlist)
, _mosType(mosType)
, _sourceBulkConnected(sourceBulkConnected)
, _trans() {}

3
vlsisapd/src/openChams/src/Instance.cpp
View File

@ -16,9 +16,10 @@ using namespace std;
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Instance::Instance(Name name, Name model, Netlist* netlist)
Instance::Instance(Name name, Name model, unsigned order, Netlist* netlist)
: _name(name)
, _model(model)
, _order(order)
, _netlist(netlist)
, _params()
, _netMap() {}

8
vlsisapd/src/openChams/src/Netlist.cpp
View File

@ -21,7 +21,7 @@ using namespace std;
namespace OpenChams {
Netlist::Netlist(Circuit* circuit) : _circuit(circuit) {}
Instance* Netlist::addInstance(Name name, Name model) {
Instance* Netlist::addInstance(Name name, Name model, unsigned order) {
for (vector<Instance*>::iterator it = _instances.begin() ; it != _instances.end() ; ++it) {
if ((*it)->getName() == name) {
string error("[ERROR] Cannot define two instances with the same name in netlist (");
@ -30,7 +30,7 @@ Instance* Netlist::addInstance(Name name, Name model) {
throw OpenChamsException(error);
}
}
Instance* inst = new Instance(name, model, this);
Instance* inst = new Instance(name, model, order, this);
if (!inst)
throw OpenChamsException("[ERROR] Cannot create instance.");
_instances.push_back(inst);
@ -38,7 +38,7 @@ Instance* Netlist::addInstance(Name name, Name model) {
return inst;
}
Device* Netlist::addDevice(Name name, Name model, Name mosType, bool sourceBulkConnected) {
Device* Netlist::addDevice(Name name, Name model, unsigned order, Name mosType, bool sourceBulkConnected) {
for (vector<Instance*>::iterator it = _instances.begin() ; it != _instances.end() ; ++it) {
if ((*it)->getName() == name) {
string error("[ERROR] Cannot define two instances with the same name in netlist (");
@ -47,7 +47,7 @@ Device* Netlist::addDevice(Name name, Name model, Name mosType, bool sourceBulkC
throw OpenChamsException(error);
}
}
Device* dev = new Device(name, model, mosType, sourceBulkConnected, this);
Device* dev = new Device(name, model, order, mosType, sourceBulkConnected, this);
if (!dev)
throw OpenChamsException("[ERROR] Cannot create device.");
_instances.push_back(dev);

5
vlsisapd/src/openChams/src/Operator.cpp
View File

@ -14,10 +14,9 @@ using namespace std;
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Operator::Operator(Name operatorName, Name simulModel, unsigned callOrder)
Operator::Operator(Name operatorName, Name simulModel)
: _name(operatorName)
, _simulModel(simulModel)
, _callOrder(callOrder) {}
, _simulModel(simulModel) {}
void Operator::addConstraint(Name paramName, Name ref, Name refParam) {
addConstraint(paramName, ref, refParam, 1.0);

8
vlsisapd/src/openChams/src/PyOpenChams.cpp
View File

@ -101,10 +101,11 @@ BOOST_PYTHON_MODULE(OPENCHAMS) {
// map wrapping and vector_indexing for OpenChams::Instance
STL_MAP_WRAPPING_PTR(Name, Net*, "ConnectorsMap")
// class OpenChams::Instance
class_<Instance, Instance*>("Instance", init<Name, Name, Netlist*>())
class_<Instance, Instance*>("Instance", init<Name, Name, unsigned, Netlist*>())
// properties
.add_property("name" , &Instance::getName )
.add_property("model" , &Instance::getModel )
.add_property("order" , &Instance::getOrder )
.add_property("parameters" , &Instance::getParameters )
.add_property("netlist" , make_function(&Instance::getNetlist ,return_value_policy<reference_existing_object>())) //make_function since we need to specify a return value policy
// accessors
@ -123,7 +124,7 @@ BOOST_PYTHON_MODULE(OPENCHAMS) {
.def(vector_indexing_suite<std::vector<Transistor*>, true>())
;
// class OpenChams::Device
class_<Device, bases<Instance> >("Device", init<Name, Name, Name, bool, Netlist*>())
class_<Device, bases<Instance> >("Device", init<Name, Name, unsigned, Name, bool, Netlist*>())
// properties
.add_property("mosType" , &Device::getMosType )
.add_property("sourceBulkConnected", &Device::isSourceBulkConnected)
@ -274,11 +275,10 @@ BOOST_PYTHON_MODULE(OPENCHAMS) {
STL_MAP_WRAPPING_PTR(Name, Operator::Constraint*, "ConstraintsMap")
{ // this scope is used to define Constraint as a subclass of Operator
// class OpenChams::Operator
scope operatorScope = class_<Operator, Operator*>("Operator", init<Name, Name, unsigned>())
scope operatorScope = class_<Operator, Operator*>("Operator", init<Name, Name>())
// properties
.add_property("name" , &Operator::getName )
.add_property("simulModel", &Operator::getSimulModel)
.add_property("callOrder" , &Operator::getCallOrder )
// accessors
.def("hasNoConstraints", &Operator::hasNoConstraints)
// modifiers

4
vlsisapd/src/openChams/src/Sizing.cpp
View File

@ -18,7 +18,7 @@ using namespace std;
namespace OpenChams {
Sizing::Sizing(Circuit* circuit): _circuit(circuit) {}
Operator* Sizing::addOperator(Name instanceName, Name operatorName, Name simulModel, unsigned callOrder) {
Operator* Sizing::addOperator(Name instanceName, Name operatorName, Name simulModel) {
map<Name, Operator*>::iterator it = _operators.find(instanceName);
if (it != _operators.end()) {
string error("[ERROR] Cannot set same instance twice in 'sizing' (");
@ -26,7 +26,7 @@ Operator* Sizing::addOperator(Name instanceName, Name operatorName, Name simulMo
error += ").";
throw OpenChamsException(error);
}
Operator* op = new Operator(operatorName, simulModel, callOrder);
Operator* op = new Operator(operatorName, simulModel);
_operators[instanceName] = op;
return op;
}

2
vlsisapd/src/openChams/src/vlsisapd/openChams/Device.h
View File

@ -22,7 +22,7 @@ class Netlist;
class Transistor;
class Device : public Instance {
public:
Device(Name name, Name model, Name mosType, bool, Netlist*);
Device(Name name, Name model, unsigned, Name mosType, bool, Netlist*);
virtual ~Device() {};

5
vlsisapd/src/openChams/src/vlsisapd/openChams/Instance.h
View File

@ -21,7 +21,7 @@ class Netlist;
class Net;
class Instance {
public:
Instance(Name name, Name model, Netlist*);
Instance(Name name, Name model, unsigned, Netlist*);
virtual ~Instance() {};
@ -32,6 +32,7 @@ class Instance {
inline void addParameter(Name, std::string);
inline Name getName() const;
inline Name getModel();
inline unsigned getOrder();
inline Netlist* getNetlist();
inline Parameters getParameters();
// pour parcourir les connecteurs
@ -41,6 +42,7 @@ class Instance {
private:
Name _name;
Name _model;
unsigned _order;
Netlist* _netlist;
Parameters _params;
std::map<Name, Net*> _netMap; //map associant nom de connecteur a un net
@ -50,6 +52,7 @@ inline void Instance::addParameter(Name name, double value) { _params.addParamet
inline void Instance::addParameter(Name name, std::string eqStr) { _params.addParameter(name, eqStr); };
inline Name Instance::getName() const { return _name; };
inline Name Instance::getModel() { return _model; };
inline unsigned Instance::getOrder() { return _order; };
inline Netlist* Instance::getNetlist() { return _netlist; };
inline Parameters Instance::getParameters() { return _params; };
inline bool Instance::hasNoConnectors() { return (_netMap.size() == 0)? true : false; };

4
vlsisapd/src/openChams/src/vlsisapd/openChams/Netlist.h
View File

@ -23,8 +23,8 @@ class Netlist {
public:
Netlist(Circuit*);
Instance* addInstance(Name name, Name model);
Device* addDevice (Name name, Name model, Name mosType, bool);
Instance* addInstance(Name name, Name model, unsigned);
Device* addDevice (Name name, Name model, unsigned, Name mosType, bool);
Net* addNet (Name name, Name type , bool);
Instance* getInstance(Name);

5
vlsisapd/src/openChams/src/vlsisapd/openChams/Operator.h
View File

@ -32,7 +32,7 @@ class Operator {
};
public:
Operator(Name operatorName, Name simulModel, unsigned callOrder);
Operator(Name operatorName, Name simulModel);
void addConstraint(Name paramName, Name ref, Name refParam );
void addConstraint(Name paramName, Name ref, Name refParam, double factor);
@ -41,20 +41,17 @@ class Operator {
inline Name getName();
inline Name getSimulModel();
inline unsigned getCallOrder();
inline bool hasNoConstraints();
inline const std::map<Name, Constraint*>& getConstraints();
private:
Name _name;
Name _simulModel;
unsigned _callOrder;
std::map<Name, Constraint*> _constraints;
};
inline Name Operator::getName() { return _name; };
inline Name Operator::getSimulModel() { return _simulModel; };
inline unsigned Operator::getCallOrder() { return _callOrder; };
inline bool Operator::hasNoConstraints() { return (_constraints.size() == 0) ? true : false; };
inline const std::map<Name, Operator::Constraint*>& Operator::getConstraints() { return _constraints; };

2
vlsisapd/src/openChams/src/vlsisapd/openChams/Sizing.h
View File

@ -21,7 +21,7 @@ class Sizing {
public:
Sizing(Circuit*);
Operator* addOperator(Name instanceName, Name operatorName, Name simulModel, unsigned callOrder);
Operator* addOperator(Name instanceName, Name operatorName, Name simulModel);
void addEquation(Name equationName, std::string equation);
inline bool hasNoOperators();