The VST driver is now allowed to preserve the case of identifiers.
* New: In CRL::NamingScheme, add a flag VstNoLowerCase, and its
management it in the Verilog to VHDL converter.
* Change: In CRL::BlifParser::Model::toVhdlModels(), disable the
lowercasing of identifiers. We shouldn't apply Alliance VHDL
subset constraits when reading blif files. So we will see
uppercase identifiers in Coriolis.
* Change: In CRL::VstParser, no longer lowercase identifiers that
are *not* VHDL keywords. Uppercases are legals in VHDL...
* New: In CRL::Catalog::State, add a new flag VstNoLowerCase to
tell if the VST driver should keep the uppercases.
* Change: In CRL::VhdlEntity, add a VstNolowerCase flag to disable
the lowercasing.
* Change: In CRL::vstDriver, lower case the file name if needed.
remove the previously opened filename if it differs from the
lowercased one.
* Change: In UnicornGui CTOR, disable VHDL enforcement for the
Blif parser.
This commit is contained in:
Jean-Paul Chaput
parent
f91fc4f927
commit
5d891b2cd8
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@ -105,6 +105,7 @@ namespace Vhdl {
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, _globals()
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, _flags (flags)
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{
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if (flags & VstNoLowerCase) _ns.setNoLowerCase( true );
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if (not _offset) {
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//_offset = offsetof(EntityProperty,_entity);
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_offset = (ptrdiff_t)this - (ptrdiff_t)property;
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@ -133,7 +134,7 @@ namespace Vhdl {
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signal->addNet( index, net );
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_signals.insert( signal );
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} else {
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ScalarSignal* signal = new ScalarSignal(net);
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ScalarSignal* signal = new ScalarSignal(stem,net);
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_signals.insert( signal );
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if (net->isGlobal())
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_globals.insert( signal );
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@ -229,7 +230,7 @@ namespace Vhdl {
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signal->addNet( index, net );
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_signals.insert( signal );
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} else {
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_signals.insert( new ScalarSignal(net) );
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_signals.insert( new ScalarSignal(stem,net) );
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}
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}
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}
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@ -324,6 +325,12 @@ namespace Vhdl {
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out << "-- Coriolis Structural VHDL Driver\n";
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out << "-- Generated on " << stamp << "\n";
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out << "-- \n";
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if (_flags & OptionMask) {
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out << "-- Genarated with options:\n";
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if (_flags & VstUseConcat) out << "-- * VstUseConcat: Use concat (&) in port map.\n";
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if (_flags & VstNoLowerCase) out << "-- * VstNoLowerCase: Identifiers are *not* put in lowercase.\n";
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out << "-- \n";
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}
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if (isIeeeMode()) {
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out << "-- VHDL IEEE compliant.\n";
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} else {
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@ -96,8 +96,8 @@ namespace Vhdl {
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// Class : "Vhdl::ScalarSignal".
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ScalarSignal::ScalarSignal ( Net* net )
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: Signal(getString(net->getName()))
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ScalarSignal::ScalarSignal ( string vhdlName, Net* net )
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: Signal(vhdlName)
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, _bit (BitExtension::create(net,this))
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{ }
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@ -15,6 +15,7 @@
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#include <cstddef>
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#include <cstdio>
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#include "hurricane/Warning.h"
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#include "hurricane/Cell.h"
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#include "hurricane/Net.h"
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@ -40,15 +41,35 @@ namespace CRL {
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{
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unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
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if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat;
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if (saveState & Catalog::State::VstNoLowerCase) entityFlags |= Vhdl::Entity::VstNoLowerCase;
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//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
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Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
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string celltest = cellPath;
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ofstream ccelltest ( celltest.c_str() );
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vhdlEntity->toEntity( ccelltest );
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ccelltest << endl;
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ccelltest.close();
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string celltest = cellPath;
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if (not (saveState & Catalog::State::VstNoLowerCase)) {
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size_t slash = cellPath.find_last_of( "/" );
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size_t dot = cellPath.find_last_of( "." );
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string path = "";
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string file = "";
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string ext = cellPath.substr( dot+1 );
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if (slash != string::npos) {
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path = cellPath.substr( 0, slash );
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file = cellPath.substr( slash+1, dot-slash-1 );
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} else {
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file = cellPath;
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}
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NamingScheme ns (NamingScheme::FromVerilog);
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file = getString( ns.convert(file) );
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celltest = path + '/' + file + '.' + ext;
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if (cellPath != celltest) remove( cellPath.c_str() );
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}
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ofstream cellStream ( celltest.c_str() );
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vhdlEntity->toEntity( cellStream );
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cellStream << endl;
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cellStream.close();
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Vhdl::EntityExtension::destroy( cell );
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}
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@ -229,7 +229,10 @@ base_specifier (B|b|O|o|X|x)
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\/ { return Slash; }
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{letter}(_?{letter_or_digit})* {
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VHDLKeywords::iterator it = vhdlKeywords.find( lower(yytext) );
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char keyword[512];
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strncpy( keyword, yytext, 511 );
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lower( keyword );
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VHDLKeywords::iterator it = vhdlKeywords.find( keyword );
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if (it != vhdlKeywords.end()) { return it->second; }
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VSTlval._text = Vst::states->addLexIdentifier( yytext );
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return Identifier;
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@ -431,7 +431,9 @@ namespace {
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{
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for ( Model* model : _blifOrder )
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CRL::NamingScheme::toVhdl( model->getCell()
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, CRL::NamingScheme::Recursive|CRL::NamingScheme::FromVerilog );
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, CRL::NamingScheme::Recursive
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| CRL::NamingScheme::FromVerilog
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| CRL::NamingScheme::NoLowerCase );
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}
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@ -87,6 +87,7 @@ namespace CRL {
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, InMemory = 1 << 7
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, Foreign = 1 << 8
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, VstUseConcat = 1 << 9
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, VstNoLowerCase = 1 << 10
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, Views = Physical|Logical
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};
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// Constructors.
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@ -65,19 +65,29 @@ namespace CRL {
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enum Flag { NoFlags = 0x0000
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, Recursive = 0x0001
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, FromVerilog = 0x0002
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, NoLowerCase = 0x0004
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};
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public:
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typedef std::function< Name(const Name&) > converter_t;
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typedef std::function< Name(const Name&,uint32_t) > converter_t;
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public:
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static Name vlogToVhdl ( const Name& vlogName );
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static void toVhdl ( Cell* topCell, unsigned int flags );
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NamingScheme ( unsigned int flags );
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static Name vlogToVhdl ( const Name& vlogName, uint32_t flags );
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static void toVhdl ( Cell* topCell, uint32_t flags );
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NamingScheme ( uint32_t flags );
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inline void setNoLowerCase ( bool state );
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Name convert ( const Name& ) const;
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private:
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uint32_t _flags;
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converter_t _converter;
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};
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inline void NamingScheme::setNoLowerCase ( bool state )
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{
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if (state) _flags |= NoLowerCase;
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else _flags &= ~NoLowerCase;
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}
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} // CRL namespace.
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#endif // CRL_TOOLBOX_H
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@ -65,8 +65,10 @@ namespace Vhdl {
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, AsPortSignal = 0x0008
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, AsInnerSignal = 0x0010
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, VstUseConcat = 0x0020
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, VstNoLowerCase = 0x0040
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, OptionMask = VstUseConcat|VstNoLowerCase
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};
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const unsigned int ModeMask = VstUseConcat;
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const unsigned int ModeMask = VstUseConcat|VstNoLowerCase;
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public:
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static std::vector<Entity*>&
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getAllEntities ();
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@ -74,7 +74,7 @@ namespace Vhdl {
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class ScalarSignal : public Signal {
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public:
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ScalarSignal ( Net* );
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ScalarSignal ( std::string vhdlName, Net* );
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virtual ~ScalarSignal ();
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virtual bool isScalar () const;
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virtual bool isVector () const;
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@ -29,17 +29,10 @@ namespace CRL {
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using Hurricane::Instance;
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Name NamingScheme::vlogToVhdl ( const Name& vlogName )
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Name NamingScheme::vlogToVhdl ( const Name& vlogName, uint32_t flags )
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{
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string vhdlName;
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// VHDL reserved keywords (scalar).
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if (vlogName == Name("in" )) return "in_v";
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if (vlogName == Name("out" )) return "out_v";
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if (vlogName == Name("inout")) return "inout_v";
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if (vlogName == Name("true" )) return "bool_true";
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if (vlogName == Name("false")) return "bool_false";
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if (vlogName == Name("undef")) return "bool_undef";
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string loweredName;
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size_t parCount = 0;
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size_t posLeftPar = 0;
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@ -49,6 +42,7 @@ namespace CRL {
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if (vlogName[i] == '[') { ++parCount; posLeftPar=i; }
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if (vlogName[i] == ')') { posRightPar=i; }
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if (vlogName[i] == ']') { posRightPar=i; }
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loweredName.push_back( tolower(vlogName[i]) );
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}
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char leftPar = (parCount > 1) ? '_' : '(';
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char rightPar = (parCount > 1) ? '_' : ')';
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@ -62,8 +56,17 @@ namespace CRL {
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}
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}
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for ( size_t i=0 ; i<vlogName.size() ; ++i ) {
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char translated = tolower( vlogName[i] );
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// VHDL reserved keywords (scalar).
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if (loweredName == "in" ) return "in_v";
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if (loweredName == "out" ) return "out_v";
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if (loweredName == "inout") return "inout_v";
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if (loweredName == "true" ) return "bool_true";
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if (loweredName == "false") return "bool_false";
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if (loweredName == "undef") return "bool_undef";
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string refName = (flags & NoLowerCase) ? getString(vlogName) : loweredName;
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for ( size_t i=0 ; i<refName.size() ; ++i ) {
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char translated = refName[i];
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if ( vhdlName.empty() and (isdigit(translated)) )
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vhdlName += 'n';
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@ -78,7 +81,7 @@ namespace CRL {
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if (translated == '_') {
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if (vhdlName.empty() ) continue;
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if (i == vlogName.size()-1) break;
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if (i == refName.size()-1) break;
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if (vhdlName.back() == '_') continue;
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}
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@ -86,18 +89,18 @@ namespace CRL {
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}
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// VHDL reserved keywords (vector).
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if (vhdlName.substr(0,3) == "in(" ) vhdlName.insert(2,"_v");
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if (vhdlName.substr(0,4) == "out(" ) vhdlName.insert(3,"_v");
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if (vhdlName.substr(0,6) == "inout(") vhdlName.insert(5,"_v");
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if (vhdlName == "true" ) vhdlName.insert(0,"value_");
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if (vhdlName == "false" ) vhdlName.insert(0,"value_");
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if (vhdlName == "undef" ) vhdlName.insert(0,"value_");
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if (loweredName.substr(0,3) == "in(" ) vhdlName.insert(2,"_v");
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if (loweredName.substr(0,4) == "out(" ) vhdlName.insert(3,"_v");
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if (loweredName.substr(0,6) == "inout(") vhdlName.insert(5,"_v");
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if (loweredName == "true" ) vhdlName.insert(0,"value_");
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if (loweredName == "false" ) vhdlName.insert(0,"value_");
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if (loweredName == "undef" ) vhdlName.insert(0,"value_");
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return Name(vhdlName);
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}
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void NamingScheme::toVhdl ( Cell* topCell, unsigned int flags )
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void NamingScheme::toVhdl ( Cell* topCell, uint32_t flags )
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{
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if (not topCell) return;
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@ -107,11 +110,11 @@ namespace CRL {
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if (converter == nullptr) return;
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topCell->setName( converter(topCell->getName()) );
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topCell->setName( converter(topCell->getName(),flags) );
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vector<Net*> nets;
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for ( Net* net : topCell->getNets() ) nets.push_back( net );
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for ( auto net : nets ) net->setName( converter( net->getName() ) );
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for ( auto net : nets ) net->setName( converter( net->getName(), flags ) );
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vector<Instance*> instances;
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set<Cell*,Entity::CompareById> models;
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@ -119,7 +122,7 @@ namespace CRL {
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instances.push_back( inst );
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models.insert( inst->getMasterCell() );
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}
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for ( auto inst : instances ) inst->setName( converter( inst->getName() ) );
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for ( auto inst : instances ) inst->setName( converter( inst->getName(), flags ) );
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if (flags & Recursive)
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for ( auto model : models ) {
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@ -128,17 +131,18 @@ namespace CRL {
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}
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NamingScheme::NamingScheme ( unsigned int flags )
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: _converter(nullptr)
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NamingScheme::NamingScheme ( uint32_t flags )
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: _flags (flags)
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, _converter(nullptr)
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{
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if (flags & FromVerilog) _converter = vlogToVhdl;
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if (_flags & FromVerilog) _converter = vlogToVhdl;
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}
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Name NamingScheme::convert ( const Name& name ) const
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{
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if (_converter == nullptr) return name;
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return _converter(name);
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return _converter(name,_flags);
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}
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@ -2,25 +2,17 @@
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// -*- C++ -*-
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//
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// This file is part of the Coriolis Software.
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// Copyright (c) UPMC/LIP6 2010-2010, All Rights Reserved
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// Copyright (c) SU/LIP6 2010-2020, All Rights Reserved
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//
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// ===================================================================
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//
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// $Id$
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//
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// x-----------------------------------------------------------------x
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// | |
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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// | Alliance / Hurricane Interface |
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// | |
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// | Author : Jean-Paul CHAPUT |
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// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
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// | E-mail : Jean-Paul.Chaput@lip6.fr |
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// | =============================================================== |
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// | C++ Module : "./PyCatalog.cpp" |
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// | *************************************************************** |
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// | U p d a t e s |
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// | |
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// x-----------------------------------------------------------------x
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// +-----------------------------------------------------------------+
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#include "hurricane/isobar/PyCell.h"
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@ -1,14 +1,14 @@
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// -*- C++ -*-
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//
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// This file is part of the Coriolis Software.
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// Copyright (c) UPMC 2010-2018, All Rights Reserved
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// Copyright (c) UPMC 2010-2020, All Rights Reserved
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//
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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// | Alliance / Hurricane Interface |
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// | |
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// | Author : Jean-Paul CHAPUT |
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// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
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// | E-mail : Jean-Paul.Chaput@lip6.fr |
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// | =============================================================== |
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// | C++ Module : "./PyCatalogState.cpp" |
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// +-----------------------------------------------------------------+
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@ -146,6 +146,7 @@ extern "C" {
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::InMemory ,"InMemory");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Foreign ,"Foreign");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUseConcat ,"VstUseConcat");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLowerCase ,"VstNoLowerCase");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views");
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}
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@ -48,7 +48,10 @@ def rsave ( cell, views=CRL.Catalog.State.Physical, depth=0 ):
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sviews += 'netlist'
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if views & CRL.Catalog.State.VstUseConcat:
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if sviews: sviews += ','
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sviews += 'VST uses &'
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sviews += ' uses &'
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if views & CRL.Catalog.State.VstNoLowerCase:
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if sviews: sviews += ', no lowercase'
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sviews += ''
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if views & CRL.Catalog.State.Physical:
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if sviews: sviews += ','
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sviews += 'layout'
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@ -98,7 +98,7 @@ namespace Unicorn {
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_importCell.setDialog( _importDialog );
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_importCell.addImporter<Cell*> ( "JSON (experimental)" , std::bind( &Cell::fromJson , placeholders::_1 ) );
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_importCell.addImporter<Cell*> ( "BLIF (Yosys/ABC)" , std::bind( &Blif::load , placeholders::_1, true ) );
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_importCell.addImporter<Cell*> ( "BLIF (Yosys/ABC)" , std::bind( &Blif::load , placeholders::_1, false ) );
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_importCell.addImporter<Cell*> ( "ACM/SIGDA (aka MCNC, .bench)", std::bind( &AcmSigda::load , placeholders::_1 ) );
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/* Disabled because this is never the one you want
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_importCell.addImporter<Cell*> ( "ISPD'04 (Bookshelf)" , std::bind( &Ispd04::load , placeholders::_1 ) );
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|
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Loading…
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