No more use of "fulladder.vst" file : parser takes into account sxlib's fulladder.

rep "lib" therefore removed.

    ! .xml environment files have to be modified to take this into account !

stratus1/etc/stratus2sxlib.xml

@@ -22,8 +22,7 @@
     <model name="mx2"       realcell="mx2_x2"       i0="i0" i1="i1"          cmd="cmd"  q="q"                      vdd="vdd" vss="vss"></model>
     <model name="nmx2"      realcell="nmx2_x1"      i0="i0" i1="i1"          cmd="cmd" nq="nq"                     vdd="vdd" vss="vss"></model>
     <model name="halfadder" realcell="halfadder_x2"  a="a"   b="b"                   sout="sout" cout="cout"       vdd="vdd" vss="vss"></model>
-    <!-- Encapsulation of fulladder_x2 in order to modify the interface more than just the names -->               
+    <model name="fulladder" realcell="fulladder_x2"  a="a1,a2,a3,a4" b="b1,b2,b3,b4" cin="cin1,cin2,cin3" sout="sout" cout="cout" vdd="vdd" vss="vss"></model>
-    <model name="fulladder" realcell="fulladder"     a="a"   b="b" cin="cin"         sout="sout" cout="cout"       vdd="vdd" vss="vss"></model>
     <model name="sff1"      realcell="sff1_x4"       i="i"          ck="ck"             q="q"                      vdd="vdd" vss="vss"></model>
     <model name="sff2"      realcell="sff2_x4"      i0="i0" i1="i1" ck="ck"  cmd="cmd"  q="q"                      vdd="vdd" vss="vss"></model>
     <model name="sff3"      realcell="sff3_x4"      i0="i0" i1="i1" i2="i2"  ck="ck" cmd0="cmd0" cmd1="cmd1" q="q" vdd="vdd" vss="vss"></model>

stratus1/src/lib/fulladder.vst

@@ -1,102 +0,0 @@
--- This file is part of the Coriolis Project.
--- Copyright (C) Laboratoire LIP6 - Departement ASIM
--- Universite Pierre et Marie Curie
---
--- Main contributors :
---        Christophe Alexandre   <Christophe.Alexandre@lip6.fr>
---        Sophie Belloeil             <Sophie.Belloeil@lip6.fr>
---        Hugo Clement                   <Hugo.Clement@lip6.fr>
---        Jean-Paul Chaput           <Jean-Paul.Chaput@lip6.fr>
---        Damien Dupuis                 <Damien.Dupuis@lip6.fr>
---        Christian Masson           <Christian.Masson@lip6.fr>
---        Marek Sroka                     <Marek.Sroka@lip6.fr>
--- 
--- The  Coriolis Project  is  free software;  you  can redistribute  it
--- and/or modify it under the  terms of the GNU General Public License
--- as published by  the Free Software Foundation; either  version 2 of
--- the License, or (at your option) any later version.
--- 
--- The  Coriolis Project is  distributed in  the hope  that it  will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied warranty
--- of MERCHANTABILITY  or FITNESS FOR  A PARTICULAR PURPOSE.   See the
--- GNU General Public License for more details.
--- 
--- You should have  received a copy of the  GNU General Public License
--- along with the Coriolis Project;  if not, write to the Free Software
--- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
--- USA
---
--- License-Tag
--- Authors-Tag
--- ===================================================================
---
--- x-----------------------------------------------------------------x 
--- |                                                                 |
--- |                   C O R I O L I S                               |
--- |        S t r a t u s   -  Netlists Description                  |
--- |                                                                 |
--- |  Author      :                    Sophie BELLOEIL               |
--- |  E-mail      :       Sophie.Belloeil@asim.lip6.fr               |
--- | =============================================================== |
--- |  Vst Module  :       "./fulladder.vst"                          |
--- | *************************************************************** |
--- |  U p d a t e s                                                  |
--- |                                                                 |
--- x-----------------------------------------------------------------x
-
-
-entity fulladder is
-   port (
-      a    :  in bit;
-      b    :  in bit;
-      cin  :  in bit;
-      sout :  out bit;
-      cout :  out bit;
-      vdd  :  in bit;
-      vss  :  in bit
-   );
-end fulladder;
-
-architecture structural of fulladder is
-component fulladder_x2
-   port (
-      a1   :  in bit;
-      a2   :  in bit;
-      a3   :  in bit;
-      a4   :  in bit;
-      b1   :  in bit;
-      b2   :  in bit;
-      b3   :  in bit;
-      b4   :  in bit;
-      cin1 :  in bit;
-      cin2 :  in bit;
-      cin3 :  in bit;
-      sout :  out bit;
-      cout :  out bit;
-      vdd  :  in bit;
-      vss  :  in bit
-   );
-end component;
-
-begin
-
-cell : fulladder_x2
-   port map ( 
-      a1   => a,
-      a2   => a,
-      a3   => a,
-      a4   => a,
-      b1   => b,
-      b2   => b,
-      b3   => b,
-      b4   => b,
-      cin1 => cin,
-      cin2 => cin,
-      cin3 => cin,
-      sout => sout,
-      cout => cout,
-      vdd  => vdd,
-      vss  => vss
-   );
-
-end structural;

stratus1/src/stratus/st_instance.py

@@ -110,6 +110,7 @@ class Inst :
     if BV == [] : InitBV()
     
     if model in BV : model, self._inout = GetRealModel ( model )
+    print "inout récupéré:", self._inout
 
     ##### Attributes of the instance #####
     self._model        = model.lower()
@@ -215,12 +216,8 @@ class Inst :
     self._hur_instance = inst
     
     ##### Connection #####
-    for pin in self._map :
+    ##### Function to be applied on each pin 
-      mapNet = self._map[pin]
+    def connectPin ( pin ) : 
-
-      ### Virtual library ###
-      if "_inout" in self.__dict__ : pin = self._inout[pin]
-      
       # Error : if there is a space in the name of the pin (usually done at the end of the pin ...)
       if re.search ( " ", pin ) :
         err = "\n[Stratus ERROR] Inst : " + self._name + " the keys of the connection map can not contain a space : \"" + pin + "\".\n"
@@ -328,12 +325,29 @@ class Inst :
         # In order to see the ring
         if str ( realNet.__class__ ) not in ALIM_NET : CRL.createPartRing ( self._st_cell._hur_cell, hurNet.getName() )
 
+    ##### Loop on each pin
+    for pin in self._map :
+      mapNet = self._map[pin]
+
+      ### Virtual library ###
+      if "_inout" in self.__dict__ :
+        import types
+        if type ( self._inout[pin] ) == types.ListType :
+          for realpin in self._inout[pin] :
+            connectPin ( realpin )
+        else :
+          realpin = self._inout[pin]
+          connectPin ( realpin )
+      ### Other ###
+      else :
+        connectPin ( pin )
+    
     # Error message if the connection is not correct (detection before vst driver)
     # Not for vdd/vss in case of utilisation of SetGlobal
     # The detection is done with vst driver in this case ...
     for plug in self._hur_instance.getUnconnectedPlugs():
       if plug.getMasterNet().getType() not in ( TypePOWER, TypeGROUND ) :
-        name = str(plus.getMasterNet().getName())
+        name = str(plug.getMasterNet().getName())
         chaine = re.search ( "(.*)\(", name )
         if chaine : name = chaine.group(1)
     

stratus1/src/stratus/st_parser.py

@@ -85,8 +85,7 @@ class Parser :
   #########################################
   def start_element ( self, name, attrs ) :
     # Print which the technology is
-#    if   name == 'technology' :
+    if   name == 'technology' : print "  - Stratus virtual technology targets:", attrs['name']
-#      print "Technology is :",   attrs['name']
 
     # Modification of attributes
     if name == 'model' :
@@ -97,7 +96,14 @@ class Parser :
       inOutTemp = {}
       for key in attrs :
         if key not in ( 'name', 'realcell' ) :
-          inOutTemp[str(key)] = str(attrs[str(key)])
+          virtualPort = str(key)
+          realPort    = str(attrs[virtualPort])
+          if ',' in realPort :
+            import re
+            tabPort = re.split ( '[,]', realPort )
+            inOutTemp[virtualPort] = tabPort
+          else :
+            inOutTemp[virtualPort] = realPort
 
       self._inOut[str(attrs['name'])] = inOutTemp
       
@@ -161,7 +167,7 @@ class InitParser :
   def Parse ( self, nameFile ) :
     self._p.ParseFile ( open ( nameFile, "r" ) )
 
-    # Givien the tab of the name of the cells, contruction of a tab giving the name of the generators (first letter uppered)
+    # Given the tab of the name of the cells, contruction of a tab giving the name of the generators (first letter uppered)
     for name in BV :
       chaine = re.search ( "([a-z])(.+)", name )
       name_g = chaine.group(1).upper() + chaine.group(2)