Correctly remove VHDL Entity and Bit properties.

* Bug: In CRL Core, in Vst driver, remove VhdlEntity (from Cell) and
    BitProperty/Bit (from Net) with the property remove and not the
    destroy() method. The BitProperty removal was completly forgotten
    leading to the use of removed Signals when doing multiple saves
    (hence core-dump).
* Change: In CRL Core, in Vst driver, never save as Signals the DeepNets
    as they are created by a virtual flatten and do not connect any
    instances at top level. Note that they will exists in the physical
    file if routing layout has been created.

crlcore/src/ccore/alliance/vst/VhdlEntity.cpp

@@ -111,16 +111,17 @@ namespace Vhdl {
 
     if (_flags == NoFlags) _flags = EntityMode;
 
-    forEach ( Net*, inet, cell->getNets() ) {
-      if (not inet->isExternal() and (flags & ComponentMode)) continue;
+    for ( Net* net : cell->getNets() ) {
+      if (net->isDeepNet()) continue;
+      if (not net->isExternal() and (flags & ComponentMode)) continue;
 
       string  stem;
       size_t  index  = 0;
-      if (parseNetName(*inet,stem,index)) {
-        if (inet->isGlobal()) {
+      if (parseNetName(net,stem,index)) {
+        if (net->isGlobal()) {
           cerr << Warning( "Vhdl::Entity::Entity(): Net is both vectorized and global, this is not allowed.\n"
                          "         On Net <%s> of Cell <%s>."
-                         , getString(inet->getName()).c_str()
+                         , getString(net->getName()).c_str()
                          , getString(cell->getName()).c_str()
                          ) << endl;
         }
@@ -128,12 +129,12 @@ namespace Vhdl {
         VectorSignal* signal = const_cast<VectorSignal*>( dynamic_cast<const VectorSignal*>( getSignal(stem) ) );
         if (not signal)
           signal = new VectorSignal ( stem );
-        signal->addNet( index, *inet );
+        signal->addNet( index, net );
         _signals.insert( signal );
       } else {
-        _signals.insert( new ScalarSignal(*inet) );
-        if (inet->isGlobal())
-          _globals.insert( new ScalarSignal(*inet) );
+        _signals.insert( new ScalarSignal(net) );
+        if (net->isGlobal())
+          _globals.insert( new ScalarSignal(net) );
       }
     }
 
@@ -144,6 +145,7 @@ namespace Vhdl {
   Entity::~Entity ()
   {
     for ( auto signal : _signals ) delete signal;
+    for ( auto global : _globals ) delete global;
     for ( auto ientity=_entities.begin() ; ientity!=_entities.end() ; ++ientity ) {
       if (*ientity == this) {
         _entities.erase( ientity );
@@ -210,19 +212,20 @@ namespace Vhdl {
   {
     if (isEntityMode()) return;
 
-    forEach ( Net*, inet, getCell()->getNets() ) {
-      if (inet->isExternal()) continue;
+    for ( Net* net : getCell()->getNets() ) {
+      if (net->isDeepNet()) continue;
+      if (net->isExternal()) continue;
 
       string  stem;
       size_t  index  = 0;
-      if (parseNetName(*inet,stem,index)) {
+      if (parseNetName(net,stem,index)) {
         VectorSignal* signal = const_cast<VectorSignal*>( dynamic_cast<const VectorSignal*>( getSignal(stem) ) );
         if (not signal)
           signal = new VectorSignal ( stem );
-        signal->addNet( index, *inet );
+        signal->addNet( index, net );
         _signals.insert( signal );
       } else {
-        _signals.insert( new ScalarSignal(*inet) );
+        _signals.insert( new ScalarSignal(net) );
       }
     }
   }
@@ -518,7 +521,7 @@ namespace Vhdl {
   void  EntityExtension::destroy ( Cell* cell )
   {
     Property* property = cell->getProperty( EntityProperty::getPropertyName() );
-    if (property) static_cast<EntityProperty*>(property)->destroy();
+    if (property) cell->remove( property );
 
     _owner = NULL;
     _cache = NULL;

crlcore/src/ccore/alliance/vst/VhdlSignal.cpp

@@ -102,7 +102,7 @@ namespace Vhdl {
   { }
 
   ScalarSignal::~ScalarSignal ()
-  { }
+  { _bit->destroy(); }
 
   bool            ScalarSignal::isScalar     () const { return true; }
   bool            ScalarSignal::isVector     () const { return false; }
@@ -150,7 +150,7 @@ namespace Vhdl {
   { }
 
   VectorSignal::~VectorSignal ()
-  { for ( auto bit : _bits ) bit->getProperty()->destroy(); }
+  { for ( auto bit : _bits ) bit->destroy(); }
 
 
   bool            VectorSignal::isScalar     () const { return false; }

crlcore/src/ccore/crlcore/VhdlBit.h

@@ -59,6 +59,7 @@ namespace Vhdl {
              const Signal* getSignal   () const;
              std::string   getName     () const;
              size_t        getIndex    () const;
+      inline void          destroy     ();
              std::string   _getString  () const;
              Record*       _getRecord  () const;
     private:
@@ -151,6 +152,7 @@ namespace Vhdl {
 
   inline BitProperty* Bit::getProperty () const { return (BitProperty*)((ptrdiff_t)(this) - _offset); }
   inline const Net*   Bit::getNet      () const { return (const Net*)getProperty()->getOwner(); }
+  inline void         Bit::destroy     () { ((Net*)getProperty()->getOwner())->remove( getProperty() ); }
 
 
 }  // Vhdl Namespace.

crlcore/src/pyCRL/PyCRL.cpp

@@ -8,7 +8,7 @@
 // |          Alliance / Hurricane  Interface                        |
 // |                                                                 |
 // |  Author      :                    Jean-Paul CHAPUT              |
-// |  E-mail      :       Jean-Paul.Chaput@asim.lip6.fr              |
+// |  E-mail      :            Jean-Paul.Chaput@lip6.fr              |
 // | =============================================================== |
 // |  C++ Module  :       "./PyCRL.cpp"                              |
 // +-----------------------------------------------------------------+