o correcting layer id (extractNumber) handling in driver

o  add sxlib2lef method we use to compare in test dir
This commit is contained in:
Jean-Manuel Caba 2010-08-02 13:07:12 +00:00
parent cdbfff194d
commit 1693eb500e
6 changed files with 9060 additions and 37 deletions

View File

@ -1,5 +1,5 @@
// -*-compile-command:"cd ../../../../.. && make"-*-
// Time-stamp: "2010-07-30 16:44:00" - OpenAccessDriver.cpp
// Time-stamp: "2010-08-02 14:58:55" - OpenAccessDriver.cpp
// x-----------------------------------------------------------------x
// | This file is part of the hurricaneAMS Software. |
// | Copyright (c) UPMC/LIP6 2008-2010, All Rights Reserved |
@ -54,15 +54,16 @@ namespace {
Cell2OADesignMap _cell2OADesign4Layout;
Instance2OAInstsMap _instance2OAInst;
Layer2OAPhysicalLayerMap _layer2OAPhysicalLayer;
set<int> _layerIDS;
int _layerID;
oaLayer* _layerDev;
oaLayer* _layerPin;
oaLayer* _layerText;
oaLayer* _layerWire;
DataBase* _db;
Technology* _technology;
int _layerID;
oaLayer* layerDev;
oaLayer* layerPin;
oaLayer* layerText;
oaLayer* layerWire;
public:
OADriver(const string& path):
OADriver(const string& path) :
_path(path),
_oaTech(NULL),
_library2OALib(),
@ -72,9 +73,14 @@ namespace {
_cell2OADesign4Layout(),
_instance2OAInst(),
_layer2OAPhysicalLayer(),
_layerIDS(),
_layerID(0),
_layerDev(NULL),
_layerPin(NULL),
_layerText(NULL),
_layerWire(NULL),
_db(NULL),
_technology(NULL),
_layerID(0) {
_technology(NULL) {
_db = DataBase::getDB();
if (!_db) {
throw Error("no database");
@ -103,9 +109,7 @@ namespace {
}
/**
Create an empty oaLib from a Library
no cells are added in this oaLib
all sub Library are also converted.
create a oaLib from a Library
*/
oaLib* getOALibForLibrary(const Library* library) {
cerr << "getOALibForLibrary" << endl;
@ -140,11 +144,39 @@ namespace {
return lib;
}
/**
handle layerID i.e: get extractNumber in Hurricane world if
possible ...
*/
int generateLayerID(BasicLayer* bLayer){
// the layer number is unique to a particular layer
cerr << "generateLayerID -> ";
int numLayer = _layerID;
if(bLayer){
numLayer = bLayer->getExtractNumber();
if(_layerIDS.find(numLayer) == _layerIDS.end()){
cerr << "getExtractNumber " << numLayer << endl;
_layerIDS.insert(numLayer);
return numLayer;
}
}
cerr << " while(...) ";
set<int>::iterator it;
while((it = _layerIDS.find(_layerID)) != _layerIDS.end()){
numLayer = ++_layerID;
}
cerr << numLayer << endl;
_layerIDS.insert(numLayer);
return numLayer;
}
/**
convert oaLayer from a Layer ...
*/
oaLayer* getOALayerFromLayer(Layer* layer,oaTech* theOATech) {
oaPhysicalLayer* getOALayerFromLayer(Layer* layer,oaTech* theOATech) {
assert(layer);
cerr << "getOALayerFromLayer " << getString(layer->getName()) << endl;
Layer2OAPhysicalLayerMap::iterator it = _layer2OAPhysicalLayer.find(layer);
if (it != _layer2OAPhysicalLayer.end()) {
return it->second;
@ -157,24 +189,25 @@ namespace {
aOALayer = oaPhysicalLayer::find(theOATech, layerName, true);
if(aOALayer){
_layer2OAPhysicalLayer[layer] = aOALayer;
_layerIDS.insert(aOALayer->getNumber());
return aOALayer;
}
BasicLayer* bLayer = dynamic_cast<BasicLayer*>(layer);
if(bLayer)
aOALayer = oaPhysicalLayer::create(theOATech, layerName, _layerID++,getOAMaterial(bLayer->getMaterial()));
else
aOALayer = oaPhysicalLayer::create(theOATech, layerName, _layerID++);
aOALayer = oaPhysicalLayer::create(theOATech, layerName, generateLayerID(bLayer),
bLayer ? getOAMaterial(bLayer->getMaterial())
: oaMaterial(oacOtherMaterial));
assert(aOALayer);
_layer2OAPhysicalLayer[layer] = aOALayer;
#if 0
//create and add layer constraint for Layer specific manufacturing rules
cerr << " o get value for constraint" << endl;
long minSize = Hurricane::DbU::getDb(layer->getMinimalSize());
long minSpace = Hurricane::DbU::getDb(layer->getMinimalSpacing());
long pitch = Hurricane::DbU::getDb(layer->getPitch());
#if 0
cerr << " o create constraint for min size : " << pitch << endl;
oaLayerConstraint* cMinSize = NULL;
try{
@ -206,9 +239,6 @@ namespace {
oaIntValue::create(theOATech->getLib(),pitch));
assert(cPitchV);
#endif
if(bLayer){
unsigned gdsIInumber = bLayer->getExtractNumber();
}
return aOALayer;
}
@ -253,22 +283,55 @@ namespace {
oaConstraintGroup *cgFoundry = theOATech->getFoundryRules();
/*
add the constraint group LEFDefaultRouteSpec for oa2lef
add the constraint group LEFDefaultRouteSpec for oa2lef
*/
//first create "utility" layers following :
layerDev = oaPhysicalLayer::create(theOATech, "device", _layerID++);
layerText = oaPhysicalLayer::create(theOATech, "text", _layerID++);
layerPin = oaPhysicalLayer::create(theOATech, "pin", _layerID++);
layerWire = oaPhysicalLayer::create(theOATech, "wire", _layerID++);
}
// get or create physical layer
//first convert basicLayers and use the getExtractNumber
for_each_basic_layer(layer, technology->getBasicLayers()) {
getOALayerFromLayer(layer,theOATech);
end_for;
}
//then convert all other layers unsing a generated ID
for_each_layer(layer, technology->getLayers()) {
getOALayerFromLayer(layer,theOATech);
end_for;
}
cerr << "test" << endl;
try{
//create or find "utility" layers following :
_layerDev = oaLayer::find(theOATech,"device");
if(!_layerDev)
_layerDev = oaPhysicalLayer::create(theOATech, "device", generateLayerID(NULL));
assert(_layerDev);
_layerIDS.insert(_layerDev->getNumber());
_layerText = oaLayer::find(theOATech,"text");
if(!_layerText)
_layerText = oaPhysicalLayer::create(theOATech, "text", generateLayerID(NULL));
assert(_layerText);
_layerIDS.insert(_layerText->getNumber());
_layerPin = oaLayer::find(theOATech,"pin");
if(!_layerPin)
_layerPin = oaPhysicalLayer::create(theOATech, "pin", generateLayerID(NULL));
assert(_layerPin);
_layerIDS.insert(_layerPin->getNumber());
_layerWire = oaLayer::find(theOATech,"wire");
if(!_layerWire)
_layerWire = oaPhysicalLayer::create(theOATech, "wire", generateLayerID(NULL));
assert(_layerWire);
_layerIDS.insert(_layerWire->getNumber());
}catch(oaException&e ){
cerr << "OA:" << e.getMsg() << endl;
exit(-2);
}catch(std::exception&e ){
cerr << "STD:" << e.what() << endl;
exit(-1);
}
printOALayers(theOATech);
return theOATech;
@ -337,9 +400,9 @@ namespace {
oaScalarName scNetName(ns, getString(net->getName()).c_str());
oaTerm* term = oaTerm::find(blockNet->getBlock(), scNetName);
assert(term);
oaPin* pin = oaPin::create(term);
return pin;
}
@ -351,11 +414,7 @@ namespace {
getOABoxForBox(box, component->getBoundingBox());
Layer* layer = (Layer*) component->getLayer();
assert(layer);
oaPhysicalLayer* physLayer = NULL;
Layer2OAPhysicalLayerMap::iterator it = _layer2OAPhysicalLayer.find(layer);
if (it != _layer2OAPhysicalLayer.end()) {
physLayer = it->second;
}
oaPhysicalLayer* physLayer = getOALayerFromLayer(layer,_oaTech);
assert(physLayer);
oaLayerNum layerNum = physLayer->getNumber();
oaRect* rect = oaRect::create(topBlock,
@ -494,7 +553,7 @@ namespace {
}
oaBlock *topBlock = designCellView->getTopBlock();
assert(topBlock);
return designCellView;
}

View File

@ -11,6 +11,9 @@ debug:
ddd:
ddd -args ./x86_64/usr/local/bin/testOAWrapper /asim/chams/etc/chams/config.freePDK45.xml /tmp/testOA
valgrind:
valgrind ./x86_64/usr/local/bin/testOAWrapper /asim/chams/etc/chams/config.freePDK45.xml /tmp/testOA
rmtmp:
rm -rf /tmp/*

View File

@ -0,0 +1,14 @@
all: sxlib.lef
lef2oa -lib sxlib -lef sxlib.lef
sxlib.lef:
grep -v "END LIBRARY" cmos.lef.bak > sxlib.lef ; for i in $$(cat cells) ; do sxlib2lef $$i ; cat $$i.lef >> sxlib.lef ; done
echo "END LIBRARY" >> sxlib.lef
cp sxlib.lef sxlib.lef.bak
mrproper: clean
rm -rf sxlib cds.lib
clean:
rm -rf *.log *.slog *~ encounter* *.lef

View File

@ -0,0 +1,95 @@
a2_x2
a2_x4
a3_x2
a3_x4
a4_x2
a4_x4
an12_x1
an12_x4
ao22_x2
ao22_x4
ao2o22_x2
ao2o22_x4
buf_x2
buf_x4
buf_x8
fulladder_x2
fulladder_x4
halfadder_x2
halfadder_x4
inv_x1
inv_x2
inv_x4
inv_x8
mx2_x2
mx2_x4
mx3_x2
mx3_x4
na2_x1
na2_x4
na3_x1
na3_x4
na4_x1
na4_x4
nao22_x1
nao22_x4
nao2o22_x1
nao2o22_x4
nmx2_x1
nmx2_x4
nmx3_x1
nmx3_x4
no2_x1
no2_x4
no3_x1
no3_x4
no4_x1
no4_x4
noa22_x1
noa22_x4
noa2a22_x1
noa2a22_x4
noa2a2a23_x1
noa2a2a23_x4
noa2a2a2a24_x1
noa2a2a2a24_x4
noa2ao222_x1
noa2ao222_x4
noa3ao322_x1
noa3ao322_x4
nts_x1
nts_x2
nxr2_x1
nxr2_x4
o2_x2
o2_x4
o3_x2
o3_x4
o4_x2
o4_x4
oa22_x2
oa22_x4
oa2a22_x2
oa2a22_x4
oa2a2a23_x2
oa2a2a23_x4
oa2a2a2a24_x2
oa2a2a2a24_x4
oa2ao222_x2
oa2ao222_x4
oa3ao322_x2
oa3ao322_x4
on12_x1
on12_x4
one_x0
powmid_x0
rowend_x0
sff1_x4
sff2_x4
sff3_x4
tie_x0
ts_x4
ts_x8
xr2_x1
xr2_x4
zero_x0

View File

@ -0,0 +1,435 @@
#
# $Id: cmos.lef,v 1.6 2005/03/01 14:59:15 jpc Exp $
#
# /------------------------------------------------------------------\
# | |
# | A l l i a n c e C A D S y s t e m |
# | S i l i c o n E n s e m b l e / A l l i a n c e |
# | |
# | Author : Jean-Paul CHAPUT |
# | E-mail : alliance-users@asim.lip6.fr |
# | ================================================================ |
# | LEF : "./cmos_12.lef" |
# | **************************************************************** |
# | U p d a t e s |
# | |
# \------------------------------------------------------------------/
#
VERSION 5.2 ;
NAMESCASESENSITIVE ON ;
BUSBITCHARS "()" ;
DIVIDERCHAR "." ;
#NOWIREEXTENSIONATPIN ON ;
#UNITS
# DATABASE MICRONS 100 ;
#END UNITS
LAYER POLY
TYPE MASTERSLICE ;
END POLY
LAYER VIAP
TYPE CUT ;
END VIAP
LAYER ALU1
TYPE ROUTING ;
WIDTH 2.00 ;
SPACING 3.00 ;
PITCH 5.00 ;
DIRECTION VERTICAL ;
CAPACITANCE CPERSQDIST 0.000032 ;
RESISTANCE RPERSQ 0.100000 ;
END ALU1
LAYER VIA1
TYPE CUT ;
END VIA1
LAYER ALU2
TYPE ROUTING ;
WIDTH 2.00 ;
SPACING 3.00 ;
PITCH 5.00 ;
DIRECTION HORIZONTAL ;
CAPACITANCE CPERSQDIST 0.000032 ;
RESISTANCE RPERSQ 0.100000 ;
END ALU2
LAYER VIA2
TYPE CUT ;
END VIA2
LAYER ALU3
TYPE ROUTING ;
WIDTH 2.00 ;
SPACING 3.00 ;
PITCH 5.00 ;
DIRECTION VERTICAL ;
CAPACITANCE CPERSQDIST 0.000032 ;
RESISTANCE RPERSQ 0.100000 ;
END ALU3
LAYER VIA3
TYPE CUT ;
END VIA3
LAYER ALU4
TYPE ROUTING ;
WIDTH 2.00 ;
SPACING 3.00 ;
PITCH 5.00 ;
DIRECTION HORIZONTAL ;
CAPACITANCE CPERSQDIST 0.000032 ;
RESISTANCE RPERSQ 0.100000 ;
END ALU4
LAYER VIA4
TYPE CUT ;
END VIA4
LAYER ALU5
TYPE ROUTING ;
WIDTH 2.00 ;
SPACING 3.00 ;
PITCH 5.00 ;
DIRECTION VERTICAL ;
CAPACITANCE CPERSQDIST 0.000032 ;
RESISTANCE RPERSQ 0.100000 ;
END ALU5
LAYER VIA5
TYPE CUT ;
END VIA5
LAYER ALU6
TYPE ROUTING ;
WIDTH 2.00 ;
SPACING 3.00 ;
PITCH 5.00 ;
DIRECTION HORIZONTAL ;
CAPACITANCE CPERSQDIST 0.000032 ;
RESISTANCE RPERSQ 0.100000 ;
END ALU6
#VIA CONT_POLY DEFAULT
# LAYER POLY ;
# RECT -1.50 -1.50 1.50 1.50 ;
# LAYER VIAP ;
# RECT -0.50 -0.50 0.50 0.50 ;
# LAYER ALU1 ;
# RECT -1.00 -1.00 1.00 1.00 ;
#END CONT_POLY
VIA CONT_VIA DEFAULT
LAYER ALU1 ;
RECT -1.00 -1.00 1.00 1.00 ;
LAYER VIA1 ;
RECT -0.50 -0.50 0.50 0.50 ;
LAYER ALU2 ;
RECT -1.00 -1.00 1.00 1.00 ;
END CONT_VIA
VIA CONT_VIA2 DEFAULT
LAYER ALU3 ;
RECT -1.00 -1.00 1.00 1.00 ;
LAYER VIA2 ;
RECT -0.50 -0.50 0.50 0.50 ;
LAYER ALU2 ;
RECT -1.00 -1.00 1.00 1.00 ;
END CONT_VIA2
VIA CONT_VIA3 DEFAULT
LAYER ALU4 ;
RECT -1.00 -1.00 1.00 1.00 ;
LAYER VIA3 ;
RECT -0.50 -0.50 0.50 0.50 ;
LAYER ALU3 ;
RECT -1.00 -1.00 1.00 1.00 ;
END CONT_VIA3
VIA CONT_VIA4 DEFAULT
LAYER ALU5 ;
RECT -1.00 -1.00 1.00 1.00 ;
LAYER VIA4 ;
RECT -0.50 -0.50 0.50 0.50 ;
LAYER ALU4 ;
RECT -1.00 -1.00 1.00 1.00 ;
END CONT_VIA4
VIA CONT_VIA5 DEFAULT
LAYER ALU6 ;
RECT -1.00 -1.00 1.00 1.00 ;
LAYER VIA5 ;
RECT -0.50 -0.50 0.50 0.50 ;
LAYER ALU5 ;
RECT -1.00 -1.00 1.00 1.00 ;
END CONT_VIA5
VIARULE TURN_ALU1 GENERATE
LAYER ALU1 ;
DIRECTION vertical ;
LAYER ALU1 ;
DIRECTION horizontal ;
END TURN_ALU1
VIARULE TURN_ALU2 GENERATE
LAYER ALU2 ;
DIRECTION vertical ;
LAYER ALU2 ;
DIRECTION horizontal ;
END TURN_ALU2
VIARULE TURN_ALU3 GENERATE
LAYER ALU3 ;
DIRECTION vertical ;
LAYER ALU3 ;
DIRECTION horizontal ;
END TURN_ALU3
VIARULE TURN_ALU4 GENERATE
LAYER ALU4 ;
DIRECTION vertical ;
LAYER ALU4 ;
DIRECTION horizontal ;
END TURN_ALU4
VIARULE TURN_ALU5 GENERATE
LAYER ALU5 ;
DIRECTION vertical ;
LAYER ALU5 ;
DIRECTION horizontal ;
END TURN_ALU5
VIARULE TURN_ALU6 GENERATE
LAYER ALU6 ;
DIRECTION vertical ;
LAYER ALU6 ;
DIRECTION horizontal ;
END TURN_ALU6
#VIARULE VIA1_HV
# LAYER ALU1 ;
# DIRECTION VERTICAL ;
# OVERHANG 0.50 ;
# METALOVERHANG 0.50 ;
#
# LAYER ALU2 ;
# DIRECTION HORIZONTAL ;
# OVERHANG 0.50 ;
# METALOVERHANG 0.50 ;
#
# VIA CONT_VIA ;
#END VIA1_HV
#
#
#VIARULE VIA2_VH
# LAYER ALU2 ;
# DIRECTION HORIZONTAL ;
# OVERHANG 0.50 ;
# METALOVERHANG 0.50 ;
#
# LAYER ALU3 ;
# DIRECTION VERTICAL ;
# OVERHANG 0.50 ;
# METALOVERHANG 0.50 ;
#
# VIA CONT_VIA2 ;
#END VIA2_VH
#
#
#VIARULE VIA3_VH
# LAYER ALU3 ;
# DIRECTION HORIZONTAL ;
# OVERHANG 0.50 ;
# METALOVERHANG 0.50 ;
#
# LAYER ALU4 ;
# DIRECTION VERTICAL ;
# OVERHANG 0.50 ;
# METALOVERHANG 0.50 ;
#
# VIA CONT_VIA3 ;
#END VIA3_VH
VIARULE genVIA1_HV GENERATE
LAYER ALU1 ;
DIRECTION VERTICAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER ALU2 ;
DIRECTION HORIZONTAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER VIA1 ;
RECT -0.50 -0.50 0.50 0.50 ;
SPACING 3.00 BY 3.00 ;
END genVIA1_HV
VIARULE genVIA1_VH GENERATE
LAYER ALU1 ;
DIRECTION HORIZONTAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER ALU2 ;
DIRECTION VERTICAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER VIA1 ;
RECT -0.50 -0.50 0.50 0.50 ;
SPACING 3.00 BY 3.00 ;
END genVIA1_VH
VIARULE genVIA2_VH GENERATE
LAYER ALU2 ;
DIRECTION HORIZONTAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER ALU3 ;
DIRECTION VERTICAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER VIA2 ;
RECT -0.50 -0.50 0.50 0.50 ;
SPACING 3.00 BY 3.00 ;
END genVIA2_VH
VIARULE genVIA2_HV GENERATE
LAYER ALU2 ;
DIRECTION VERTICAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER ALU3 ;
DIRECTION HORIZONTAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER VIA2 ;
RECT -0.50 -0.50 0.50 0.50 ;
SPACING 3.00 BY 3.00 ;
END genVIA2_HV
VIARULE genVIA3_VH GENERATE
LAYER ALU3 ;
DIRECTION HORIZONTAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER ALU4 ;
DIRECTION VERTICAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER VIA3 ;
RECT -0.50 -0.50 0.50 0.50 ;
SPACING 3.00 BY 3.00 ;
END genVIA3_VH
VIARULE genVIA3_HV GENERATE
LAYER ALU3 ;
DIRECTION VERTICAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER ALU4 ;
DIRECTION HORIZONTAL ;
OVERHANG 0.50 ;
METALOVERHANG 0.50 ;
LAYER VIA3 ;
RECT -0.50 -0.50 0.50 0.50 ;
SPACING 3.00 BY 3.00 ;
END genVIA3_HV
SPACING
SAMENET VIAP VIAP 3.00 ;
SAMENET VIA1 VIA1 3.00 ;
SAMENET VIA2 VIA2 3.00 ;
SAMENET VIAP VIA1 3.00 STACK ;
SAMENET VIA1 VIA2 3.00 STACK ;
SAMENET VIA2 VIA3 3.00 STACK ;
SAMENET VIA3 VIA4 3.00 STACK ;
SAMENET VIA4 VIA5 3.00 STACK ;
SAMENET POLY POLY 3.00 ;
SAMENET ALU1 ALU1 3.00 STACK ;
SAMENET ALU2 ALU2 3.00 STACK ;
SAMENET ALU3 ALU3 3.00 STACK ;
SAMENET ALU4 ALU4 3.00 STACK ;
SAMENET ALU5 ALU5 3.00 STACK ;
SAMENET ALU6 ALU6 3.00 ;
END SPACING
SITE core
SYMMETRY y ;
CLASS CORE ;
SIZE 5.00 BY 50.00 ;
END core
SITE pad
SYMMETRY y ;
CLASS PAD ;
SIZE 1.00 BY 500.00 ;
END pad
SITE corner
SYMMETRY y r90 ;
CLASS PAD ;
SIZE 500.00 BY 500.00 ;
END corner
END LIBRARY

File diff suppressed because it is too large Load Diff