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Make block/chip plugin use the common rsave plugin. 

* In cumulus/block.configuration, the rsave method was buggy. It did stop
    it did not save "terminal" master cells (i.e. a cell without instance)
    instead of "netlistTerminal" (explicitely flagged for standard cells).
      The result was that some "empty netlist" in the complete "ls180"
    from LibreSOC went missing. Causing cougar to complain.
This commit is contained in:
Jean-Paul Chaput 2020-12-04 12:20:57 +01:00
parent be5483a0ad
commit 1411739c0b
3 changed files with 24 additions and 18 deletions
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35
cumulus/src/plugins/alpha/block/configuration.py
View File

@ -44,6 +44,7 @@ from helpers.io import WarningMessage
from helpers.io import catch
from helpers.overlay import CfgCache
from plugins import getParameter
from plugins.rsave import rsave
from plugins.alpha.utils import getPlugByName
@ -1163,21 +1164,23 @@ class BlockConf ( GaugeConf ):
self.cloneds.append( masterCell )
return
def rsave ( self, cell ):
"""
Save the complete cell hierarchy. Saves only the physical view, except
for the ones that has been cloned (their names should end up by "_cts"),
for which logical and physical views are to be saved. They are completely
new cells.
"""
flags = CRL.Catalog.State.Physical
if cell.getName().endswith('_cts'):
flags = flags | CRL.Catalog.State.Logical
self.framework.saveCell( cell, flags )
for instance in cell.getInstances():
masterCell = instance.getMasterCell()
if not masterCell.isTerminal():
self.rsave( masterCell )
#def rsave ( self, cell, depth ):
# """
# Save the complete cell hierarchy. Saves only the physical view, except
# for the ones that has been cloned (their names should end up by "_cts"),
# for which logical and physical views are to be saved. They are completely
# new cells.
# """
# if depth == 0: print( ' o Block Recursive Save-Cell.' )
# flags = CRL.Catalog.State.Physical
# if cell.getName().endswith('_cts'): flags |= CRL.Catalog.State.Logical
# if cell.isUniquified(): flags |= CRL.Catalog.State.Logical
# self.framework.saveCell( cell, flags )
# print( ' {}+ {}.'.format(' '*(depth*2), cell.getName() ) )
# for instance in cell.getInstances():
# masterCell = instance.getMasterCell()
# if not masterCell.isTerminalNetlist():
# self.rsave( masterCell, depth+1 )
def save ( self ):
"""
@ -1190,5 +1193,5 @@ class BlockConf ( GaugeConf ):
cell.setName( cell.getName()+'_cts' )
if self.chip is None:
self.cell.setName( self.cell.getName()+'_r' )
self.rsave( self.cell )
rsave( self.cell )
return

3
cumulus/src/plugins/alpha/core2chip/core2chip.py
View File

@ -52,6 +52,7 @@ from helpers import trace, netDirectionToStr
from helpers.overlay import UpdateSession
from helpers.io import ErrorMessage, WarningMessage
import plugins.chip
from plugins.rsave import rsave
from plugins.alpha.utils import getPlugByName
from plugins.alpha.block.block import Block
from plugins.alpha.block.configuration import BlockConf, IoPadConf, ConstantsConf
@ -662,4 +663,4 @@ class CoreToChip ( object ):
ioPad.udata.createPad()
self._connectRing()
self._connectClocks()
self.conf.rsave( self.chip )
rsave( self.chip, views=Catalog.State.Logical )

4
cumulus/src/plugins/rsave.py
View File

@ -58,7 +58,9 @@ def rsave ( cell, views=CRL.Catalog.State.Physical, depth=0 ):
if sviews: sviews += ','
sviews += 'layout'
print( ' {}+ {} ({}).'.format(' '*(depth*2), cell.getName(), sviews) )
if cell.isUniquified(): views |= CRL.Catalog.State.Logical
if cell.isUniquified(): views |= CRL.Catalog.State.Logical
if cell.getName().endswith('_cts'): views |= CRL.Catalog.State.Logical
if cell.getName().endswith('_r' ): views |= CRL.Catalog.State.Logical
framework.saveCell( cell, views )
for instance in cell.getInstances():
#print( ' {}| {}.'.format(' '*(depth*2), instance) )