Capacitor & resistor integration in the Slicing Tree.
* New: In Karakaze/Oceane.py, now also read capacitor & resistors parameters.
In AnalogDesign.readParameters(), get the capacitor parameters from
Oceane into the "device spec" (dspec). Translate form OSI unit to
Coriolis units (F -> pF).
* Bug: In Bora::NodeSets::create(), Capacitor matrix parameters where never
read due to a misplaced curly brace (at the matrixRange dynamic_cast<>
test).
* Change: In Bora/PyDSlicingNode, now check that the parameter is either
a StepParameterRange or a MatrixParameterRange.
Also add a check that the Instance name exists...
* Bug: In Bora::SlicingPlotWidget::updateSelectedPoint(), as we display
only the transistor parameters in dynamic labels, do not forget to
skip resistor and capacitor. Otherwise we end up in out of bound
access in the vector of labels.
This commit is contained in:
Jean-Paul Chaput
parent
eea67a9111
commit
057501a8df
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@ -189,7 +189,10 @@ namespace Bora {
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{
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cdebug_log(535,1) << "HSlicingNode::updateGlobalsize() - " << this << endl;
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for ( SlicingNode* child : _children ) child->updateGlobalSize();
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for ( SlicingNode* child : _children ) {
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cdebug_log(535,0) << "child: " << child << endl;
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child->updateGlobalSize();
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}
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if (not getMaster()) {
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if (getNbChild() == 1) {
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@ -70,7 +70,8 @@ namespace Bora {
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TransistorFamily* device = dynamic_cast<TransistorFamily *>( cell );
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StepParameterRange* stepRange = dynamic_cast<StepParameterRange*>( nodeset->getRange() );
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if (device) {
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//cdebug_log(536,0) << "createNodeSets for an Analog Device" << endl;
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cdebug_log(535,0) << "NodeSets:create(): for a Transistor Analog Device" << endl;
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if (not stepRange) {
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throw Error( "NodeSets::create(): Device \"%s\" must be associated with a StepParameterRange argument instead of %s."
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, getString(device->getName()).c_str()
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@ -94,11 +95,14 @@ namespace Bora {
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MatrixParameterRange* matrixRange = dynamic_cast<MatrixParameterRange*>( nodeset->getRange() );
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if (mcapacitor) {
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cdebug_log(535,0) << "NodeSets::create(): for a Capacitor Analog Device" << endl;
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if (not matrixRange) {
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throw Error( "NodeSets::create(): Device \"%s\" must be associated with a MatrixParameterRange argument instead of %s."
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, getString(mcapacitor->getName()).c_str()
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, getString(stepRange).c_str()
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);
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}
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matrixRange->reset();
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do {
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@ -109,15 +113,18 @@ namespace Bora {
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layoutGenerator->setDevice( mcapacitor );
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layoutGenerator->drawLayout();
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//cerr << " Create BoxSet for Capacitor " << matrixRange->getValue() << endl;
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cerr << " Create BoxSet for Capacitor " << endl;
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nodeset->push_back( DBoxSet::create( mcapacitor, matrixRange->getIndex(), rg ) );
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matrixRange->progress();
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} while ( matrixRange->isValid() );
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}
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} else {
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ResistorFamily* device = dynamic_cast<ResistorFamily *>( cell );
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StepParameterRange* stepRange = dynamic_cast<StepParameterRange*>( nodeset->getRange() );
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if (device) {
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cdebug_log(535,0) << "NodeSets::create(): for a Resistor Analog Device" << endl;
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if (not stepRange) {
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throw Error( "NodeSets::create(): Device \"%s\" must be associated with a StepParameterRange argument instead of %s."
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, getString(device->getName()).c_str()
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@ -18,6 +18,7 @@
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#include "crlcore/PyRoutingGauge.h"
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#include "bora/PyDSlicingNode.h"
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#include "bora/PyStepParameterRange.h"
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#include "bora/PyMatrixParameterRange.h"
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namespace Bora {
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@ -73,8 +74,9 @@ extern "C" {
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PyErr_SetString( ConstructorError, "DSlicingNode.create(): Second argument *must* be of type Cell." );
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return NULL;
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}
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if (not IsPyStepParameterRange(pyParameterRange)) {
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PyErr_SetString( ConstructorError, "DSlicingNode.create(): Third argument *must* be of type StepParameterRange." );
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if ( not IsPyStepParameterRange(pyParameterRange)
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and not IsPyMatrixParameterRange(pyParameterRange)) {
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PyErr_SetString( ConstructorError, "DSlicingNode.create(): Third argument *must* be of type StepParameterRange or MatrixParameterRange." );
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return NULL;
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}
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if (pyRoutingGauge and not IsPyRoutingGauge(pyRoutingGauge)) {
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@ -84,6 +86,14 @@ extern "C" {
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Cell* cell = PYCELL_O( pyCell );
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Instance* instance = cell->getInstance( PyString_AsString(pyInstance) );
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if (not instance) {
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ostringstream message;
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message << "DSlicingNode.create(): Cell \"" << cell->getName()
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<< "\" has no instance named \"" << PyString_AsString(pyInstance) << "\".";
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PyErr_SetString( ConstructorError, message.str().c_str() );
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return NULL;
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}
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ParameterRange* range = ParameterRangeCast( pyParameterRange );
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RoutingGauge* rg = (pyRoutingGauge) ? PYROUTINGGAUGE_O(pyRoutingGauge) : NULL;
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@ -16,6 +16,7 @@
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#include "bora/PyParameterRange.h"
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#include "bora/PyStepParameterRange.h"
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#include "bora/PyMatrixParameterRange.h"
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namespace Bora {
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@ -113,6 +114,7 @@ extern "C" {
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ParameterRange* ParameterRangeCast ( PyObject* derivedObject ) {
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if (IsPyStepParameterRange (derivedObject)) return PYSTEPPARAMETERRANGE_O (derivedObject);
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if (IsPyMatrixParameterRange(derivedObject)) return PYMATRIXPARAMETERRANGE_O(derivedObject);
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return NULL;
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}
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@ -396,14 +396,18 @@ namespace Bora {
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for( Instance* iInstance : instances ) {
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Cell* model = iInstance->getMasterCell();
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Device* device = dynamic_cast<Device*>(model);
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cerr << "device:" << device << endl;
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if (device) {
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TransistorFamily* tf = dynamic_cast<TransistorFamily*>( device );
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if (tf) _gridLabel[i+5]->setDynamicText ( QString("%1" ).arg( tf->getNfing() ) );
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}
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cerr << "tf:" << tf << endl;
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if (tf) {
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_gridLabel[i+5]->setDynamicText ( QString("%1" ).arg( tf->getNfing() ) );
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i++;
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}
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}
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}
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}
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} // Bora namespace.
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@ -54,6 +54,9 @@ import Katana
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import Bora
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helpers.setTraceLevel( 110 )
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NMOS = Transistor.NMOS
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PMOS = Transistor.PMOS
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PIP = CapacitorFamily.PIP
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@ -350,8 +353,18 @@ class AnalogDesign ( object ):
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if not path: return
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self.parameters.read( path );
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for dspec in self.devicesSpecs:
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if len(dspec) > 2:
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if dspec[0] == MultiCapacitor:
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Cname = dspec[1]
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Cparameters = self.parameters.getCapacitor( Cname )
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if not Cparameters:
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raise Error( 3, [ 'AnalogDesign.readParameters(): Missing parameters for capacity \"%s\".' % Cname ] )
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continue
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print dspec[5]
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dspec[4] = Cparameters.C * 1e+12
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trace( 110, '\t- \"%s\" : C:%fpF\n' % (Cname ,dspec[4]) )
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else:
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Tname = dspec[1].split('_')[0]
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Tparameters = self.parameters.getTransistor( Tname )
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if not Tparameters:
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@ -410,6 +423,8 @@ class AnalogDesign ( object ):
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device = dspec[0].create( self.library, dspec[1], dspec[3], len(capaValues) )
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device.getParameter( 'Layout Styles' ).setValue( dspec[2] )
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print device.getParameter( 'matrix' )
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device.getParameter( 'matrix' ).setMatrix( dspec[5] )
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for i in range(len(capaValues)):
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device.getParameter( 'capacities' ).setValue( i, capaValues[i] )
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@ -7,15 +7,31 @@ class Parameters ( object ):
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class Transistor ( object ):
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def __init__ ( self, aName ):
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name = aName
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L = 0.0
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W = 0.0
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M = 0
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self.name = aName
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self.L = 0.0
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self.W = 0.0
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self.M = 0
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return
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class Capacitor ( object ):
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def __init__ ( self, aName ):
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self.name = aName
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self.C = 0.0
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return
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class Resistor ( object ):
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def __init__ ( self, aName ):
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self.name = aName
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self.R = 0.0
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return
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def __init__ ( self ):
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self.transistors = { }
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self.capacitors = { }
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self.resistors = { }
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self.indexToName = { }
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return
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@ -54,13 +70,59 @@ class Parameters ( object ):
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#def getTransistorM ( self, ref ): return self.getTransistor(ref)[2]
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def addCapacitor ( self, name, value ):
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lname = name.lower()
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if self.capacitors.has_key(lname):
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print 'Duplicated capacitor "%s" (ignored).' % lname
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else:
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print 'Add capacitor "%s"' % lname
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self.capacitors[ lname ] = Parameters.Capacitor( lname )
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self.capacitors[ lname ].C = value
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return self.capacitors[ lname ]
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def getCapacitor ( self, ref ):
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capacitor = None
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lname = ref.lower()
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if self.capacitors.has_key(lname):
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capacitor = self.capacitors[lname]
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else:
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print 'No capacitor named "%s".' % ref
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return capacitor
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def addResistor ( self, name, value ):
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lname = name.lower()
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if self.resistors.has_key(lname):
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print 'Duplicated resistor "%s" (ignored).' % lname
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else:
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self.resistors[ lname ] = Parameters.Resistor( lname )
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self.resistors[ lname ].R = value
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return self.resistors[ lname ]
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def getResistor ( self, ref ):
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resistor = None
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lname = ref.lower()
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if self.capactors.has_key(lname):
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resistor = self.capactors[lname]
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else:
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print 'No resistor named "%s".' % ref
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return resistor
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def read ( self, file ):
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reSpecCapa = re.compile( r'^(?P<name>C\w+)\s+(?P<value>.*)$' )
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reSpecResis = re.compile( r'^(?P<name>R\w+)\s+(?P<value>.*)$' )
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reSpecTran = re.compile( r'^\* SPECIFICATIONS DE M(?P<index>\d+)\s+:\s+(?P<name>\w+) \*$' )
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reSpecL = re.compile( r'L_(?P<index>\d+)\s+(?P<float>[0-9.e-]+)' )
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reSpecW = re.compile( r'W_(?P<index>\d+)\s+(?P<float>[0-9.e-]+)' )
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reSpecM = re.compile( r'M_(?P<index>\d+)\s+(?P<int>\d+)' )
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fd = open( file, 'r' )
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for line in fd.readlines():
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if line.startswith('REGIME_'): continue
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m = reSpecTran.match( line[:-1] )
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if m:
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@ -93,4 +155,12 @@ class Parameters ( object ):
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self.getTransistor(i).M = M
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self.getTransistor(i).W = M * self.getTransistor(i).W
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m = reSpecCapa.match( line[:-1] )
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if m:
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self.addCapacitor( m.group('name'), float(m.group('value')) )
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m = reSpecResis.match( line[:-1] )
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if m:
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self.addResistor( m.group('name'), float(m.group('value')) )
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fd.close()
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@ -39,6 +39,8 @@ class CapacitorStack( CapacitorUnit ):
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# \param columnNumber Number of columns in the matrix of capacitors.
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def __init__( self, device, capacitance, capacitorType, abutmentBoxPosition, nets, unitCap = 0, matrixDim = [1,1], matchingMode = False, matchingScheme = [], dummyRing = False, dummyElement = False ):
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print 'CapacitorStack.__init__()'
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print 'matrixDim:', matrixDim
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self.device = device
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self.capacitorType = capacitorType
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@ -62,6 +64,7 @@ class CapacitorStack( CapacitorUnit ):
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self.vRoutingTrack_width = 0
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if self.__areInputDataOK__(capacitance) == True :
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print 'Input data are OK'
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if self.matchingMode == False :
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self.compactCapDim = self.__computeCapDim__( capacitance[0] , capacitorType )
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@ -134,24 +137,29 @@ class CapacitorStack( CapacitorUnit ):
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def __initGivenZeroUnitCap__( self, capacitance ):
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print '__initGivenZeroUnitCap__'
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print self.matrixDim.values()
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if ( self.matrixDim.values() == [1,1] and CapacitorUnit.__isCapacitorUnitOK__(self, self.compactCapDim) ):
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print 'Case 1'
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[ self.capacitance , self.unitCapDim ] = [ capacitance , self.compactCapDim ]
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elif ( self.matrixDim.values() == [1,1] and not(CapacitorUnit.__isCapacitorUnitOK__( self, self.compactCapDim)) ):
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raise Error(1, '__init__(): Impossible to draw the capacitor, dimensions are either too large or too small, "%s".' % self.compactCapDim ) #com2 : use to physical
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elif ( self.matrixDim["columns"]>1 or self.matrixDim["rows"]>1) :
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unitCapacitance = capacitance / (self.matrixDim["columns"]*self.matrixDim["rows"])
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unitCapDim = self.__computeCapDim__( unitCapacitance, self.capacitorType )
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if CapacitorUnit.__isCapacitorUnitOK__(self, unitCapDim) == True :
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print 'This is a mutlicapacitor'
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self.unitCapDim = unitCapDim
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[ self.unitCapacitance , self.capacitance, self.doMatrix ] = [ unitCapacitance , capacitance, True ]
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else:
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print 'This is a capacitor unit'
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else : raise Error( 1, '__init__(): Impossible to draw the unit capacitor, dimensions are either too large or too small, "%s".' % self.unitCapDim ) #com2 : use to physical
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else:
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raise Error( 1, '__init__(): Impossible to draw the unit capacitor, dimensions are either too large or too small, "%s".' % self.unitCapDim ) #com2 : use to physical
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return
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@ -181,6 +189,7 @@ class CapacitorStack( CapacitorUnit ):
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def __initGivenZeroUnitCapInMatchingMode__( self, capacitance ):
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print '__initGivenZeroUnitCapInMatchingMode__'
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if self.matrixDim.values() == [1,1] or (self.matrixDim["columns"] == len(self.matchingScheme[0]) and self.matrixDim["rows"] == len(self.matchingScheme)) :
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@ -237,6 +246,10 @@ class CapacitorStack( CapacitorUnit ):
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for k in range(0, self.capacitorsNumber):
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unitCapList.append( capacitance[k]/self.capacitorIdOccurence(k) )
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print self.capacitorsNumber
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print 'capacitance', capacitance
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print 'unitCapList', unitCapList
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print '============='
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return unitCapList
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@ -344,7 +357,8 @@ class CapacitorStack( CapacitorUnit ):
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elif bbMode == False :
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drawnCapacitor = self.drawCapacitorStack( )
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output = drawnCapacitor
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else :raise Error(1, 'create(): The bonding box mode parameter, "bbMode" must be either True or False : %s.' %bbMode )
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else:
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raise Error(1, 'create(): The bonding box mode parameter, "bbMode" must be either True or False : %s.' %bbMode )
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UpdateSession.close ()
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@ -372,7 +386,7 @@ class CapacitorStack( CapacitorUnit ):
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self.drawTopPlatesRLayers ( topPlateRLayer , drawnActiveCapacitor )
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else:
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drawnCapacitor = CapacitorUnit( self.device, self.capacitance, self.capacitorType, [self.abutmentBoxPosition["XMin"], self.abutmentBoxPosition["YMin"]] )
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drawnCapacitor = CapacitorUnit( self.device, self.capacitorType, [self.abutmentBoxPosition["XMin"], self.abutmentBoxPosition["YMin"]], self.capacitance )
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drawnCapacitor.create( self.nets[0][0], self.nets[0][1] )
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return drawnCapacitor
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@ -1,20 +1,25 @@
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#!/usr/bin/python
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print "SOURCE RouteCapacitorSingle"
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import sys
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import numpy
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from Hurricane import *
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from CRL import *
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from math import sqrt, ceil
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import helpers
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from helpers import ErrorMessage as Error
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from helpers.io import ErrorMessage as Error
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from helpers import trace
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import oroshi
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from CapacitorFinal6 import CapacitorUnit
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from CapacitorMatrix20 import CapacitorStack
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from CapacitorUnit import CapacitorUnit
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from CapacitorMatrix import CapacitorStack
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## Routs a compact or a matrix of capacitors by connecting it to routing tracks. For a fixed instance, only one type of capacitor is supported at a time, either the Poly-Poly type or Metal-Metal in 350 nm AMS CMOS technology.
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# The dummy mode is also supported.
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# The dummyRing mode is not yet supported.
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def toDbU ( l ): return DbU.fromPhysical( l, DbU.UnitPowerMicro )
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def toPhY ( l ): return DbU.toPhysical ( l, DbU.UnitPowerMicro )
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def doBreak( level, message ):
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UpdateSession.close()
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@ -23,7 +28,7 @@ def doBreak( level, message ):
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helpers.staticInitialization( True )
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class RoutCapacitor( CapacitorUnit ):
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class RouteCapacitorSingle( CapacitorUnit ):
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rules = oroshi.getRules()
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@ -96,7 +101,7 @@ class RoutCapacitor( CapacitorUnit ):
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# - the capacitor type (ie., cuts2 if MIMCAP, cut1 if PIPCAP )
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# - routing tracks layers according to the designer specifications.
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def rout( self, bbMode = False ):
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def route( self, bbMode = False ):
|
||||
|
||||
UpdateSession.open ()
|
||||
|
||||
|
|
@ -117,7 +122,7 @@ class RoutCapacitor( CapacitorUnit ):
|
|||
elif self.capacitorType == 'PIPCap' :
|
||||
topbottomCutLayer = DataBase.getDB().getTechnology().getLayer("cut1")
|
||||
|
||||
else : raise Error( 1,'rout() : Unsupported capacitor type : %s.' %self.capacitorType )
|
||||
else : raise Error( 1,'route() : Unsupported capacitor type : %s.' %self.capacitorType )
|
||||
|
||||
|
||||
self.drawRoutingTracks ( routingTracksLayer )
|
||||
|
|
@ -145,19 +150,19 @@ class RoutCapacitor( CapacitorUnit ):
|
|||
def setRules ( self ):
|
||||
|
||||
CapacitorUnit.setRules ( self )
|
||||
CapacitorUnit.__setattr__ ( self, "minSpacing_routingTrackMetal" , RoutCapacitor.rules.minSpacing_metal2 )
|
||||
CapacitorUnit.__setattr__ ( self, "minSpacing_routingTrackMetal" , RouteCapacitorSingle.rules.minSpacing_metal2 )
|
||||
|
||||
if self.capacitorType == 'MIMCap' :
|
||||
|
||||
CapacitorUnit.__setattr__( self, "minHeight_routingTrackcut" , RoutCapacitor.rules.minWidth_cut2 )
|
||||
CapacitorUnit.__setattr__( self, "minSpacing_routingTrackcut" , RoutCapacitor.rules.minSpacing_cut2 )
|
||||
CapacitorUnit.__setattr__( self, "minWidth_routingTrackcut" , RoutCapacitor.rules.minWidth_cut2 )
|
||||
CapacitorUnit.__setattr__( self, "minHeight_routingTrackcut" , RouteCapacitorSingle.rules.minWidth_cut2 )
|
||||
CapacitorUnit.__setattr__( self, "minSpacing_routingTrackcut" , RouteCapacitorSingle.rules.minSpacing_cut2 )
|
||||
CapacitorUnit.__setattr__( self, "minWidth_routingTrackcut" , RouteCapacitorSingle.rules.minWidth_cut2 )
|
||||
|
||||
elif self.capacitorType == 'PIPCap' :
|
||||
|
||||
CapacitorUnit.__setattr__( self, "minHeight_routingTrackcut" , RoutCapacitor.rules.minWidth_cut1 )
|
||||
CapacitorUnit.__setattr__( self, "minSpacing_routingTrackcut" , RoutCapacitor.rules.minSpacing_cut1 )
|
||||
CapacitorUnit.__setattr__( self, "minWidth_routingTrackcut" , RoutCapacitor.rules.minWidth_cut1 )
|
||||
CapacitorUnit.__setattr__( self, "minHeight_routingTrackcut" , RouteCapacitorSingle.rules.minWidth_cut1 )
|
||||
CapacitorUnit.__setattr__( self, "minSpacing_routingTrackcut" , RouteCapacitorSingle.rules.minSpacing_cut1 )
|
||||
CapacitorUnit.__setattr__( self, "minWidth_routingTrackcut" , RouteCapacitorSingle.rules.minWidth_cut1 )
|
||||
|
||||
else : raise Error(1, 'setRules() : Unsupported capacitor type "%s".' % self.capacitorType )
|
||||
|
||||
|
|
@ -610,18 +615,31 @@ def ScriptMain( **kw ):
|
|||
UpdateSession.open()
|
||||
|
||||
nets = [[t0,b0]]
|
||||
capacitance = [400]
|
||||
|
||||
capacitorInstance = CapacitorStack( Device, capacitance, 'MIMCap', [0,0], nets,unitCap = 400)
|
||||
# capacitorInstance = CapacitorStack( Device, 400, 'MIMCap', [0,0], unitCap = 100 )
|
||||
## A matrix of unit capacitors (all are active or all are dummy capacitors)
|
||||
|
||||
# capacitance = [1600]
|
||||
# capacitorInstance = CapacitorStack( Device, capacitance, 'MIMCap', [0,0], nets,unitCap = 400)
|
||||
# capacitor = capacitorInstance.create()
|
||||
#
|
||||
# routedCap = RouteCapacitorSingle( capacitorInstance, capacitor, dummyMode = True, tracksNumbers = [1,0] )
|
||||
# routedCap = RouteCapacitorSingle( capacitorInstance, capacitor, tracksNumbers = [2,0], topPlateWSpec = [0,1] , bottomPlateWSpec = [1,0] )
|
||||
# routedCap = RouteCapacitorSingle( capacitorInstance, capacitor, dummyMode = False , tracksNumbers = [1,1], topPlateWSpec = [0,1] , bottomPlateWSpec = [1,0])
|
||||
|
||||
## Unit capacitor ( an active capacitor )
|
||||
capacitance = [600]
|
||||
capacitorInstance = CapacitorStack( Device, capacitance, 'MIMCap', [0,0], nets,unitCap = 600)
|
||||
capacitor = capacitorInstance.create()
|
||||
print(capacitor)
|
||||
# routedCap = RoutCapacitor( capacitorInstance, capacitor , tracksNumbers = [2,0], topPlateWSpec = [0,1] , bottomPlateWSpec = [1,0] )
|
||||
# routedCap = RoutCapacitor( capacitorInstance, capacitor, dummyMode = False , tracksNumbers = [1,1], topPlateWSpec = [0,1] , bottomPlateWSpec = [1,0] )
|
||||
routedCap = RoutCapacitor( capacitorInstance, capacitor, dummyMode = True, tracksNumbers = [1,0] ) #, topPlateWSpec = [0,1] , bottomPlateWSpec = [1,0] )
|
||||
# routedCap = RoutCapacitor( capacitorInstance, capacitor, dummyMode = True , tracksNumbers = [1,0]) #, topPlateWSpec = [1,0] , bottomPlateWSpec = [1,0] )
|
||||
bondingBox = routedCap.rout()
|
||||
print(bondingBox)
|
||||
routedCap = RouteCapacitorSingle( capacitorInstance, capacitor, topPlateWSpec = [0,1] , bottomPlateWSpec = [1,0] )
|
||||
|
||||
## Unit capacitor ( a dummy capacitor )
|
||||
# capacitance = [600]
|
||||
# capacitorInstance = CapacitorStack( Device, capacitance, 'MIMCap', [0,0], nets,unitCap = 600)
|
||||
# capacitor = capacitorInstance.create()
|
||||
# routedCap = RouteCapacitorSingle( capacitorInstance, capacitor, dummyMode = True, tracksNumbers = [1,0] )
|
||||
|
||||
|
||||
bondingBox = routedCap.route()
|
||||
|
||||
AllianceFramework.get().saveCell( Device, Catalog.State.Views )
|
||||
|
||||
|
|
|
|||
|
|
@ -174,10 +174,19 @@ class CapacitorUnit():
|
|||
|
||||
def __isCapacitorUnitOK__( self, capDim ):
|
||||
|
||||
print 'capDim:', DbU.getValueString(capDim['width']), DbU.getValueString(capDim['height'])
|
||||
print 'min / max:', DbU.getValueString(self.getMinimumCapWidth() ), DbU.getValueString(self.getMaximumCapWidth() )
|
||||
|
||||
state = False
|
||||
if ( self.capacitorType == 'MIMCap' and CapacitorUnit.getMinimumCapWidth( self ) < capDim["width"] < self.getMaximumCapWidth() and CapacitorUnit.getMinimumCapWidth( self ) < capDim["height"] < self.getMaximumCapWidth() ) or ( self.capacitorType == 'PIPCap' and self.getMinimumCapWidth() < capDim["width"] and self.getMinimumCapWidth() < capDim["height"] ) :
|
||||
if ( self.capacitorType == 'MIMCap' \
|
||||
and CapacitorUnit.getMinimumCapWidth(self) < capDim["width" ] < self.getMaximumCapWidth() \
|
||||
and CapacitorUnit.getMinimumCapWidth(self) < capDim["height"] < self.getMaximumCapWidth() ) \
|
||||
or ( self.capacitorType == 'PIPCap' \
|
||||
and self.getMinimumCapWidth() < capDim["width" ] \
|
||||
and self.getMinimumCapWidth() < capDim["height"] ):
|
||||
state = True
|
||||
|
||||
print '__isCapacitorUnitOK__:', state
|
||||
return state
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -77,6 +77,9 @@ class VerticalRoutingTracks( CapacitorUnit, CapacitorStack ):
|
|||
|
||||
self.setRules ()
|
||||
vRoutingTracksLayer = DataBase.getDB().getTechnology().getLayer("metal3" )
|
||||
print 'self.capacitorInstance.doMatrix:', self.capacitorInstance.doMatrix
|
||||
print 'self.capacitorsNumber:', self.capacitorsNumber
|
||||
|
||||
if self.capacitorInstance.doMatrix == True and self.capacitorsNumber > 1 :
|
||||
self.minimizeVRTs()
|
||||
self.computeVRTDimensions()
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ from CapacitorUnit import CapacitorUnit
|
|||
from CapacitorMatrix import CapacitorStack
|
||||
from CapacitorVRTracks import VerticalRoutingTracks
|
||||
from CapacitorRouted import RoutMatchedCapacitor
|
||||
from CapacitorRoutedSingle import RouteCapacitorSingle
|
||||
|
||||
|
||||
def toMatrixArgs ( matrix ):
|
||||
|
|
@ -53,6 +54,7 @@ def checkCoherency ( device, bbMode ):
|
|||
|
||||
valid = True
|
||||
if pmatrix:
|
||||
print 'MultiCapacitor.checkCoherency(): Matrix:'
|
||||
rows = pmatrix.getRows ()
|
||||
columns = pmatrix.getColumns()
|
||||
|
||||
|
|
@ -96,22 +98,40 @@ def layout ( device, bbMode ):
|
|||
if device.isMIM(): typeArg = 'MIMCap'
|
||||
if device.isMOM(): typeArg = 'MOMCap'
|
||||
|
||||
print 'matrixSizeArg', matrixSizeArg
|
||||
#capaGenerator = CapacitorStack( device
|
||||
# , capValuesArg
|
||||
# , typeArg
|
||||
# , matrixSizeArg
|
||||
# , vTrackNetsArg
|
||||
# , matrixDim =matrixSizeArg
|
||||
# , matchingMode =True
|
||||
# , matchingScheme=matchingSchemeArg
|
||||
# , dummyRing =False
|
||||
# )
|
||||
capaGenerator = CapacitorStack( device
|
||||
, capValuesArg
|
||||
, typeArg
|
||||
, matrixSizeArg
|
||||
, [0,0] # AB position.
|
||||
, vTrackNetsArg
|
||||
, matrixDim =matrixSizeArg
|
||||
, matchingMode =True
|
||||
, matchingScheme=matchingSchemeArg
|
||||
#, matrixDim =matrixSizeArg
|
||||
#, matchingMode =True
|
||||
#, matchingScheme=matchingSchemeArg
|
||||
, dummyRing =False
|
||||
)
|
||||
capaMatrix = capaGenerator.create()
|
||||
if hasattr(capaMatrix,'doMatrix') and capaMatrix.doMatrix:
|
||||
capaTracks = VerticalRoutingTracks( capaGenerator, capaMatrix, True )
|
||||
capaTracks.create()
|
||||
|
||||
capaRouted = RoutMatchedCapacitor( capaTracks )
|
||||
capaRouted.route()
|
||||
else:
|
||||
capaSingle = RouteCapacitorSingle( capaGenerator
|
||||
, capaMatrix
|
||||
, topPlateWSpec=[0,1]
|
||||
, bottomPlateWSpec=[1,0] )
|
||||
capaSingle.route()
|
||||
|
||||
paramsMatrix.setGlobalCapacitorParams( device.getAbutmentBox() )
|
||||
trace( 100, '++' )
|
||||
|
|
|
|||
Loading…
Reference in New Issue