diff --git a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
index 2d8edb26..43b6c86a 100644
--- a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
+++ b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
@@ -243,8 +243,8 @@ namespace Vhdl {
         first = false;
       }
     } else {
-      cerr << "VhdlPortMap is in bit mode for \"" << _signal->getName() << "\""
-           << " _flags:" << _flags << " mappedNames:" << _mapping.size() << endl;
+      // cerr << "VhdlPortMap is in bit mode for \"" << _signal->getName() << "\""
+      //      << " _flags:" << _flags << " mappedNames:" << _mapping.size() << endl;
 
       auto imapping  = _mapping.rbegin();
       bool first = true;
diff --git a/crlcore/src/ccore/alliance/vst/VstDriver.cpp b/crlcore/src/ccore/alliance/vst/VstDriver.cpp
index 7789d0d8..8fb670ff 100644
--- a/crlcore/src/ccore/alliance/vst/VstDriver.cpp
+++ b/crlcore/src/ccore/alliance/vst/VstDriver.cpp
@@ -39,7 +39,7 @@ namespace CRL {
   void  vstDriver ( const string cellPath, Cell *cell, unsigned int& saveState )
   {
     unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
-    /*if (saveState & Catalog::State::VstUseConcat)*/ entityFlags |= Vhdl::Entity::VstUseConcat;
+    if (saveState & Catalog::State::VstUseConcat) entityFlags |= Vhdl::Entity::VstUseConcat;
     
   //NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
     Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
diff --git a/katana/src/GlobalRoute.cpp b/katana/src/GlobalRoute.cpp
index 83264bda..e09a67d8 100644
--- a/katana/src/GlobalRoute.cpp
+++ b/katana/src/GlobalRoute.cpp
@@ -19,6 +19,7 @@
 #include "hurricane/Breakpoint.h"
 #include "hurricane/RoutingPad.h"
 #include "hurricane/Cell.h"
+#include "crlcore/Utilities.h"
 #include "anabatic/Dijkstra.h"
 #include "katana/Block.h"
 #include "katana/RoutingPlane.h"
@@ -27,6 +28,7 @@
 
 namespace {
 
+  using std::cout;
   using std::cerr;
   using std::endl;
   using std::dec;
@@ -447,19 +449,23 @@ namespace Katana {
     if (not ovEdges.empty()) {
       set< const Net*, Net::CompareByName > nets;
 
-      cerr << "  o  Global routing did not complete, overflowed edges:" << endl;
+    //cerr << "  o  Global routing did not complete, overflowed edges:" << endl;
+      cerr << "  o  Global routing did not complete." << endl;
       for ( size_t iEdge = 0 ; iEdge<ovEdges.size() ; ++iEdge ) {
-        cerr << "    " << dec << setw(4) << (iEdge+1) << "+ " << ovEdges[iEdge] << endl;
+      //cerr << "    " << dec << setw(4) << (iEdge+1) << "+ " << ovEdges[iEdge] << endl;
         for ( Segment* segment : ovEdges[iEdge]->getSegments() ) {
-          cerr << "        | " << segment << " " << DbU::getValueString(segment->getLength()) << endl;
+        //cerr << "        | " << segment << " " << DbU::getValueString(segment->getLength()) << endl;
           nets.insert( segment->getNet() );
         }
       }
 
-      cerr << "  o  Conflicting nets:" << endl;
-      size_t count = 0;
-      for ( const Net* net : nets )
-        cerr << "    " << dec << setw(4) << (++count) << "| " << net->getName() << endl;
+    //cerr << "  o  Conflicting nets:" << endl;
+    //size_t count = 0;
+    //for ( const Net* net : nets )
+    //  cerr << "    " << dec << setw(4) << (++count) << "| " << net->getName() << endl;
+
+      cout << Dots::asUInt  ("     - Overflowed edges"          ,ovEdges.size()) << endl;
+      cout << Dots::asUInt  ("     - Unsatisfied nets"          ,nets   .size()) << endl;
     }
 
     if (getBlock(0)) {