2010-03-09 09:24:55 -06:00
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// -*- C++ -*-
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//
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// This file is part of the Coriolis Software.
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2013-12-03 18:59:29 -06:00
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// Copyright (c) UPMC 2008-2013, All Rights Reserved
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2010-03-09 09:24:55 -06:00
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//
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2012-12-22 12:22:54 -06:00
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// +-----------------------------------------------------------------+
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2010-03-09 09:24:55 -06:00
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// | C O R I O L I S |
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// | K i t e - D e t a i l e d R o u t e r |
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// | |
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// | Author : Jean-Paul CHAPUT |
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// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
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// | =============================================================== |
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// | C++ Module : "./BuildPowerRails.cpp" |
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2012-12-22 12:22:54 -06:00
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// +-----------------------------------------------------------------+
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2010-03-09 09:24:55 -06:00
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2013-12-03 18:59:29 -06:00
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#include <map>
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#include <list>
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#include "hurricane/Error.h"
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#include "hurricane/Warning.h"
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#include "hurricane/DataBase.h"
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#include "hurricane/Technology.h"
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#include "hurricane/BasicLayer.h"
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#include "hurricane/RegularLayer.h"
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#include "hurricane/Horizontal.h"
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#include "hurricane/Vertical.h"
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#include "hurricane/NetExternalComponents.h"
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#include "hurricane/Instance.h"
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#include "hurricane/Plug.h"
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#include "hurricane/Path.h"
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#include "hurricane/Query.h"
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#include "crlcore/AllianceFramework.h"
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#include "kite/RoutingPlane.h"
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#include "kite/TrackFixedSegment.h"
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#include "kite/Track.h"
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#include "kite/KiteEngine.h"
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2010-03-09 09:24:55 -06:00
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namespace {
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using namespace std;
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using Hurricane::tab;
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using Hurricane::inltrace;
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2013-12-03 18:59:29 -06:00
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using Hurricane::ltracein;
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using Hurricane::ltraceout;
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2010-03-09 09:24:55 -06:00
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using Hurricane::ForEachIterator;
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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using Hurricane::Warning;
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using Hurricane::Error;
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2010-03-09 09:24:55 -06:00
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using Hurricane::DbU;
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using Hurricane::Box;
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using Hurricane::Interval;
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using Hurricane::Horizontal;
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using Hurricane::Vertical;
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using Hurricane::NetExternalComponents;
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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using Hurricane::Instance;
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using Hurricane::Plug;
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using Hurricane::Path;
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2010-03-09 09:24:55 -06:00
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using Hurricane::Query;
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using Hurricane::Go;
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using Hurricane::Rubber;
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using Hurricane::Layer;
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using Hurricane::BasicLayer;
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using Hurricane::RegularLayer;
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using Hurricane::Transformation;
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using Hurricane::Technology;
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using Hurricane::DataBase;
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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using CRL::AllianceFramework;
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* ./Kite:
- New: In BuildPowerRails, special processing for the power ring segments.
The "diagonal" of vias at each corner is causing a misbehavior of the
routing algorithm (due to fully saturated GCells in one direction).
As a temporary fix, extend the segments so they form a "square corner".
(problem arise on "d_in_i(22)").
- New: In RoutingEvent::_processNegociate, disable the "isForcedToHint()"
feature. No noticeable loss of quality or speed.
- New: In TrackElement/TrackSegment, wraps the AutoSegment parent's mechanism.
Allows to gets the DataNegociate of either the segment or it's parent.
- New: State::solveFullBlockages(), dedicated method to solves the case when
all the allowed tracks of a segment are blocked, tries to moves up
local segments and to break-up global ones.
- New: RoutingEventLoop, a more sophisticated way to detect looping.
Maintain a dynamic histogram of the last N (default 10) segments routeds,
with the count of how many times they have occurred. If that count
exeed 40, we *may* be facing a loop.
- Change: In State::conflictSolve1, implement new policy. The global segments
no more can be broken by local ones. The idea behind is that breaking
a global on the request of a local will only produce more cluttering
in the GCell. Globals must be keep straigth pass through, especially
inside near-saturated GCells. Globals breaking however can occurs at
another global's request.
- Change: In TrackCost, implement the new policy about locals segments that
cannot break globals segments. The sorting class now accept flags to
modulate the sorting function. Two options avalaibles: IgnoreAxisWeigth
(to uses for strap segments) and DiscardGlobals (to uses with locals).
- Change: In TrackCost, the "distance to fixed" have now an upper bound of
50 lambdas (no need to be greater because it means it's outside the
begin & en GCells). Take account not only of fixed segment, but also
of placed segments which makes bound.
- Bug: In Track::_check(), while calling each individual TrackSegment check,
uses it as the *first* argument of the "or", otherwise it may not be
called.
- Bug: In ProtectRoutingPad, loop over segment Collections while modificating
it was producing non-deterministic results. The fact that a collection
must be not modificated while beeing iterated is becoming a more and more
painful problem.
2010-12-30 12:42:17 -06:00
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using Katabatic::ChipTools;
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2010-03-09 09:24:55 -06:00
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using namespace Kite;
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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// -------------------------------------------------------------------
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// Class : "::GlobalNetTable".
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class GlobalNetTable {
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public:
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* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
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GlobalNetTable ( Cell* );
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Net* getRootNet ( const Net*, Path ) const;
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inline Net* getVdde () const;
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inline Net* getVddi () const;
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inline Net* getVsse () const;
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inline Net* getVssi () const;
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inline Net* getCk () const;
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inline Net* getCki () const;
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inline Net* getCkc () const;
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inline Net* getBlockage () const;
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inline void setBlockage ( Net* );
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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private:
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Name _vddeName;
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Name _vddiName;
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Name _vsseName;
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Name _vssiName;
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Name _ckName;
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Name _ckiName;
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Name _ckcName;
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Net* _vdde;
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Net* _vddi;
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Net* _vsse;
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Net* _vssi;
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Net* _ck; // Clock net on the (external) pad.
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Net* _cki; // Clock net in the pad ring.
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Net* _ckc; // Clock net of the core (design).
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* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
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Net* _blockage;
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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};
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* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
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inline Net* GlobalNetTable::getVdde () const { return _vdde; }
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inline Net* GlobalNetTable::getVddi () const { return _vddi; }
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inline Net* GlobalNetTable::getVsse () const { return _vsse; }
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inline Net* GlobalNetTable::getVssi () const { return _vssi; }
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inline Net* GlobalNetTable::getCk () const { return _ck; }
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inline Net* GlobalNetTable::getCki () const { return _cki; }
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inline Net* GlobalNetTable::getCkc () const { return _ckc; }
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inline Net* GlobalNetTable::getBlockage () const { return _blockage; }
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inline void GlobalNetTable::setBlockage ( Net* net ) { _blockage=net; }
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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GlobalNetTable::GlobalNetTable ( Cell* topCell )
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: _vddeName("vdde")
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, _vddiName("vddi")
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, _vsseName("vsse")
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, _vssiName("vssi")
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, _ckName ("ck")
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, _ckiName ("cki")
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, _ckcName ("ckc")
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, _vdde (NULL)
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, _vddi (NULL)
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, _vsse (NULL)
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, _vssi (NULL)
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, _ck (NULL)
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, _cki (NULL)
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, _ckc (NULL)
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* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
, _blockage(NULL)
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
{
|
|
|
|
if ( topCell == NULL ) return;
|
|
|
|
|
|
|
|
AllianceFramework* af = AllianceFramework::get ();
|
|
|
|
|
|
|
|
bool hasPad = false;
|
|
|
|
forEach ( Instance*, iinstance, topCell->getInstances() ) {
|
|
|
|
if ( af->isPad(iinstance->getMasterCell()) ) {
|
|
|
|
cmess1 << " o Design has pads, assuming complete chip top structure." << endl;
|
|
|
|
hasPad = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
forEach ( Net*, inet, topCell->getNets() ) {
|
|
|
|
Net::Type netType = inet->getType();
|
|
|
|
if ( (netType != Net::Type::POWER )
|
|
|
|
and (netType != Net::Type::GROUND)
|
|
|
|
and (netType != Net::Type::CLOCK ) ) continue;
|
|
|
|
if ( not inet->isGlobal() ) {
|
|
|
|
cerr << Warning("Non global supply/clock net <%s>.",getString(inet->getName()).c_str()) << endl;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( hasPad and (inet->getName() == _vddeName) ) { _vdde = *inet; continue; }
|
|
|
|
else if ( hasPad and (inet->getName() == _vsseName) ) { _vsse = *inet; continue; }
|
|
|
|
else if ( hasPad and (inet->getName() == _ckName ) ) { _ck = *inet; continue; }
|
|
|
|
else if ( hasPad and (inet->getName() == _ckiName ) ) { _cki = *inet; continue; }
|
|
|
|
|
|
|
|
if ( inet->isPower() ) {
|
|
|
|
if ( _vddi == NULL ) {
|
|
|
|
cmess1 << " - Using <" << inet->getName() << "> as core power net." << endl;
|
|
|
|
_vddi = *inet;
|
|
|
|
} else {
|
|
|
|
cerr << Error("More than one power net in designs is not supported yet.\n"
|
|
|
|
" (<%s> and <%s>)"
|
|
|
|
,getString(_vddi->getName()).c_str()
|
|
|
|
,getString(inet->getName()).c_str()
|
|
|
|
) << endl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( inet->isGround() ) {
|
|
|
|
if ( _vssi == NULL ) {
|
|
|
|
cmess1 << " - Using <" << inet->getName() << "> as core ground net." << endl;
|
|
|
|
_vssi = *inet;
|
|
|
|
} else {
|
|
|
|
cerr << Error("More than one ground net in designs is not supported yet.\n"
|
|
|
|
" (<%s> and <%s>)"
|
|
|
|
,getString(_vssi->getName()).c_str()
|
|
|
|
,getString(inet->getName()).c_str()
|
|
|
|
) << endl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( inet->isClock() ) {
|
|
|
|
if ( _ckc == NULL ) {
|
|
|
|
cmess1 << " - Using <" << inet->getName() << "> as core clock net." << endl;
|
|
|
|
_ckc = *inet;
|
|
|
|
} else {
|
|
|
|
cerr << Error("More than one clock net in designs is not supported yet.\n"
|
|
|
|
" (<%s> and <%s>)"
|
|
|
|
,getString(_ckc->getName()).c_str()
|
|
|
|
,getString(inet->getName()).c_str()
|
|
|
|
) << endl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( hasPad ) {
|
|
|
|
if ( _vdde == NULL ) cerr << Error("Missing (pad) <vdde> net at chip level." ) << endl;
|
|
|
|
if ( _vsse == NULL ) cerr << Error("Missing (pad) <vsse> net at chip level." ) << endl;
|
|
|
|
if ( _ck == NULL ) cerr << Warning("No (pad) <ck> net at chip level." ) << endl;
|
|
|
|
if ( _cki == NULL ) cerr << Warning("No (pad) <cki> net at chip level." ) << endl;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( _vddi == NULL ) cerr << Error("Missing <vddi>/<vdd> net at top level." ) << endl;
|
|
|
|
if ( _vssi == NULL ) cerr << Error("Missing <vssi>/<vss> net at top level." ) << endl;
|
2013-12-03 18:59:29 -06:00
|
|
|
if ( _ckc == NULL ) cparanoid << Warning("No <ck> net at top level." ) << endl;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
Net* GlobalNetTable::getRootNet ( const Net* net, Path path ) const
|
|
|
|
{
|
|
|
|
//ltrace(300) << "getRootNet:" << path << ":" << net << endl;
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
if ( net == _blockage ) return _blockage;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
|
|
|
if ( net->getName() == _vddeName ) return _vdde;
|
|
|
|
if ( net->getName() == _vsseName ) return _vsse;
|
|
|
|
|
|
|
|
if ( net->getType() == Net::Type::POWER ) return _vddi;
|
|
|
|
if ( net->getType() == Net::Type::GROUND ) return _vssi;
|
|
|
|
if ( net->getType() != Net::Type::CLOCK ) return NULL;
|
|
|
|
|
|
|
|
const Net* upNet = net;
|
|
|
|
|
|
|
|
if ( not path.isEmpty() ) {
|
|
|
|
Path upPath = path;
|
|
|
|
Instance* instance = NULL;
|
|
|
|
Plug* plug = NULL;
|
|
|
|
|
|
|
|
while ( true ) {
|
|
|
|
//cerr << path << "+" << upNet << endl;
|
|
|
|
|
|
|
|
if ( (upNet == NULL) or not upNet->isExternal() ) return NULL;
|
|
|
|
if ( path.isEmpty() ) break;
|
|
|
|
|
|
|
|
instance = path.getTailInstance();
|
|
|
|
plug = instance->getPlug(net);
|
|
|
|
if ( plug == NULL ) return NULL;
|
|
|
|
|
|
|
|
upNet = plug->getNet();
|
|
|
|
path = path.getHeadPath();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( upNet->getName() == _ckName ) return _ck;
|
|
|
|
if ( upNet->getName() == _ckiName ) return _cki;
|
|
|
|
if ( upNet->getName() == _ckcName ) return _ckc;
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
// -------------------------------------------------------------------
|
|
|
|
// Class : "::PowerRailsPlanes".
|
|
|
|
|
|
|
|
class PowerRailsPlanes {
|
2013-12-03 18:59:29 -06:00
|
|
|
public:
|
2010-03-09 09:24:55 -06:00
|
|
|
class Rails;
|
|
|
|
class Plane;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
class Rail {
|
|
|
|
public:
|
2013-12-03 18:59:29 -06:00
|
|
|
Rail ( Rails*, DbU::Unit axis, DbU::Unit width );
|
|
|
|
inline DbU::Unit getAxis () const;
|
|
|
|
inline DbU::Unit getWidth () const;
|
|
|
|
inline Rails* getRails () const;
|
|
|
|
inline RoutingPlane* getRoutingPlane () const;
|
|
|
|
inline unsigned int getDirection () const;
|
|
|
|
inline Net* getNet () const;
|
|
|
|
void merge ( DbU::Unit source, DbU::Unit target );
|
|
|
|
void doLayout ( const Layer* );
|
|
|
|
string _getString () const;
|
2010-03-09 09:24:55 -06:00
|
|
|
private:
|
|
|
|
Rails* _rails;
|
|
|
|
DbU::Unit _axis;
|
|
|
|
DbU::Unit _width;
|
|
|
|
list<Interval> _chunks;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
Net* _net;
|
2010-03-09 09:24:55 -06:00
|
|
|
};
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
private:
|
|
|
|
class RailCompare {
|
|
|
|
public:
|
|
|
|
bool operator() ( const Rail* lhs, const Rail* rhs );
|
|
|
|
};
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
class RailMatch : public unary_function<Rail*,bool> {
|
|
|
|
public:
|
|
|
|
inline RailMatch ( DbU::Unit axis, DbU::Unit width );
|
|
|
|
inline bool operator() ( const Rail* );
|
|
|
|
private:
|
|
|
|
DbU::Unit _axis;
|
|
|
|
DbU::Unit _width;
|
|
|
|
};
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
public:
|
2010-03-09 09:24:55 -06:00
|
|
|
class Rails {
|
|
|
|
public:
|
2013-12-03 18:59:29 -06:00
|
|
|
Rails ( Plane*, unsigned int direction, Net* );
|
|
|
|
~Rails ();
|
|
|
|
inline Plane* getPlane ();
|
|
|
|
inline RoutingPlane* getRoutingPlane ();
|
|
|
|
inline unsigned int getDirection () const;
|
|
|
|
inline Net* getNet () const;
|
|
|
|
void merge ( const Box& );
|
|
|
|
void doLayout ( const Layer* );
|
2010-03-09 09:24:55 -06:00
|
|
|
private:
|
2013-12-03 18:59:29 -06:00
|
|
|
Plane* _plane;
|
|
|
|
unsigned int _direction;
|
|
|
|
Net* _net;
|
|
|
|
vector<Rail*> _rails;
|
2010-03-09 09:24:55 -06:00
|
|
|
};
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
public:
|
2010-03-09 09:24:55 -06:00
|
|
|
class Plane {
|
|
|
|
public:
|
2013-12-03 18:59:29 -06:00
|
|
|
typedef map<Net*,Rails*,Net::CompareById> RailsMap;
|
|
|
|
public:
|
|
|
|
Plane ( const Layer*, RoutingPlane* );
|
|
|
|
~Plane ();
|
|
|
|
inline const Layer* getLayer () const;
|
|
|
|
inline RoutingPlane* getRoutingPlane ();
|
|
|
|
inline unsigned int getDirection () const;
|
|
|
|
inline unsigned int getPowerDirection () const;
|
|
|
|
void merge ( const Box&, Net* );
|
|
|
|
void doLayout ();
|
2010-03-09 09:24:55 -06:00
|
|
|
private:
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
const Layer* _layer;
|
|
|
|
RoutingPlane* _routingPlane;
|
2013-12-03 18:59:29 -06:00
|
|
|
RailsMap _horizontalRails;
|
|
|
|
RailsMap _verticalRails;
|
|
|
|
unsigned int _powerDirection;
|
2010-03-09 09:24:55 -06:00
|
|
|
};
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
public:
|
|
|
|
typedef map<const BasicLayer*,Plane*,BasicLayer::CompareByMask> PlanesMap;
|
2010-03-09 09:24:55 -06:00
|
|
|
public:
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
PowerRailsPlanes ( KiteEngine* );
|
|
|
|
~PowerRailsPlanes ();
|
|
|
|
inline Net* getRootNet ( Net*, Path );
|
|
|
|
bool hasPlane ( const BasicLayer* );
|
|
|
|
bool setActivePlane ( const BasicLayer* );
|
|
|
|
inline Plane* getActivePlane () const;
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
void merge ( const Box&, Net* );
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
void doLayout ();
|
2010-03-09 09:24:55 -06:00
|
|
|
private:
|
2013-12-03 18:59:29 -06:00
|
|
|
KiteEngine* _kite;
|
|
|
|
GlobalNetTable _globalNets;
|
|
|
|
PlanesMap _planes;
|
|
|
|
Plane* _activePlane;
|
2010-03-09 09:24:55 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
} // Anonymous namespace.
|
|
|
|
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
PowerRailsPlanes::Rail::Rail ( Rails* rails, DbU::Unit axis, DbU::Unit width )
|
|
|
|
: _rails (rails)
|
|
|
|
, _axis (axis)
|
|
|
|
, _width (width)
|
|
|
|
, _chunks()
|
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
ltrace(300) << " new Rail "
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
<< " @" << DbU::getValueString(axis)
|
|
|
|
<< " " << getRoutingPlane()->getLayer()->getName()
|
|
|
|
<< " " << getRails()->getNet()
|
2013-12-03 18:59:29 -06:00
|
|
|
<< " " << ((getDirection()==KbHorizontal) ? "Horizontal" : "Vertical")<< endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
inline DbU::Unit PowerRailsPlanes::Rail::getAxis () const { return _axis; }
|
|
|
|
inline DbU::Unit PowerRailsPlanes::Rail::getWidth () const { return _width; }
|
|
|
|
inline PowerRailsPlanes::Rails* PowerRailsPlanes::Rail::getRails () const { return _rails; }
|
|
|
|
inline RoutingPlane* PowerRailsPlanes::Rail::getRoutingPlane () const { return _rails->getRoutingPlane(); }
|
|
|
|
inline unsigned int PowerRailsPlanes::Rail::getDirection () const { return _rails->getDirection(); }
|
|
|
|
inline Net* PowerRailsPlanes::Rail::getNet () const { return _rails->getNet(); }
|
2010-03-09 09:24:55 -06:00
|
|
|
|
|
|
|
|
|
|
|
void PowerRailsPlanes::Rail::merge ( DbU::Unit source, DbU::Unit target )
|
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
Interval chunkToMerge ( source, target );
|
|
|
|
ltrace(300) << " Rail::merge() "
|
|
|
|
<< ((getDirection()==KbHorizontal) ? "Horizontal" : "Vertical")
|
|
|
|
<< " " << chunkToMerge << endl;
|
|
|
|
ltrace(300) << " | " << _getString() << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
|
|
|
|
list<Interval>::iterator imerge = _chunks.end();
|
|
|
|
list<Interval>::iterator ichunk = _chunks.begin();
|
|
|
|
|
|
|
|
while ( ichunk != _chunks.end() ) {
|
2013-12-03 18:59:29 -06:00
|
|
|
if (imerge == _chunks.end()) {
|
|
|
|
if (chunkToMerge.getVMax() < (*ichunk).getVMin()) {
|
|
|
|
ltrace(300) << " | Insert before " << *ichunk << endl;
|
|
|
|
imerge = _chunks.insert( ichunk, chunkToMerge );
|
|
|
|
break;
|
|
|
|
}
|
2010-03-09 09:24:55 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
if (chunkToMerge.intersect(*ichunk)) {
|
|
|
|
ltrace(300) << " | Merge with " << *ichunk << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
imerge = ichunk;
|
2013-12-03 18:59:29 -06:00
|
|
|
(*imerge).merge( chunkToMerge );
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
2013-12-03 18:59:29 -06:00
|
|
|
} else {
|
|
|
|
if (chunkToMerge.getVMax() >= (*ichunk).getVMin()) {
|
|
|
|
(*imerge).merge( *ichunk );
|
|
|
|
ltrace(300) << " | Absorb (erase) " << *ichunk << endl;
|
|
|
|
ichunk = _chunks.erase( ichunk );
|
|
|
|
continue;
|
|
|
|
} else
|
|
|
|
break;
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
2013-12-03 18:59:29 -06:00
|
|
|
|
|
|
|
// if (chunkToMerge.intersect(*ichunk)) {
|
|
|
|
// if (imerge == _chunks.end()) {
|
|
|
|
// ltrace(300) << " | Merge with " << *ichunk << endl;
|
|
|
|
// imerge = ichunk;
|
|
|
|
// (*imerge).merge( chunkToMerge );
|
|
|
|
// } else {
|
|
|
|
// (*imerge).merge( *ichunk );
|
|
|
|
// ltrace(300) << " | Absorb (erase) " << *ichunk << endl;
|
|
|
|
// ichunk = _chunks.erase( ichunk );
|
|
|
|
// continue;
|
|
|
|
// }
|
|
|
|
// }
|
|
|
|
++ichunk;
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
if (imerge == _chunks.end()) {
|
|
|
|
_chunks.insert( ichunk, chunkToMerge );
|
|
|
|
ltrace(300) << " | Insert at end " << DbU::getValueString(_axis) << " " << chunkToMerge << endl;
|
|
|
|
ltrace(300) << " | " << _getString() << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
void PowerRailsPlanes::Rail::doLayout ( const Layer* layer )
|
2010-03-09 09:24:55 -06:00
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
ltrace(300) << "Doing layout of rail: "
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
<< " " << layer->getName()
|
2013-12-03 18:59:29 -06:00
|
|
|
<< " " << ((getDirection()==KbHorizontal) ? "Horizontal" : "Vertical")
|
|
|
|
<< " @" << DbU::getValueString(_axis) << endl;
|
|
|
|
ltrace(300) << _getString() << endl;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
|
|
|
Net* net = getNet();
|
|
|
|
RoutingPlane* plane = getRoutingPlane();
|
|
|
|
Segment* segment = NULL;
|
|
|
|
DbU::Unit delta = plane->getLayerGauge()->getPitch()
|
|
|
|
- plane->getLayerGauge()->getHalfWireWidth()
|
|
|
|
- DbU::lambda(0.1);
|
|
|
|
DbU::Unit extension = layer->getExtentionCap();
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
//DbU::Unit extension = Session::getExtentionCap();
|
2013-12-03 18:59:29 -06:00
|
|
|
//unsigned int type = plane->getLayerGauge()->getType();
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
DbU::Unit axisMin = 0;
|
|
|
|
DbU::Unit axisMax = 0;
|
2010-03-09 09:24:55 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
// if ( type == Constant::PinOnly ) {
|
|
|
|
// ltrace(300) << " Layer is PinOnly." << endl;
|
|
|
|
// return;
|
|
|
|
// }
|
|
|
|
|
|
|
|
if ( getDirection() == KbHorizontal ) {
|
|
|
|
list<Interval>::iterator ichunk = _chunks.begin();
|
|
|
|
list<Interval>::iterator ichunknext = ichunk;
|
|
|
|
++ichunknext;
|
|
|
|
|
|
|
|
for ( ; ichunk != _chunks.end() ; ++ichunk, ++ichunknext ) {
|
|
|
|
|
|
|
|
if (ichunknext != _chunks.end()) {
|
|
|
|
if ((*ichunk).intersect(*ichunknext))
|
|
|
|
cerr << Error( "Overlaping consecutive chunks in %s %s Rail @%s:\n"
|
|
|
|
" %s"
|
|
|
|
, getString(layer->getName()).c_str()
|
|
|
|
, ((getDirection()==KbHorizontal) ? "Horizontal" : "Vertical")
|
|
|
|
, DbU::getValueString(_axis).c_str()
|
|
|
|
, _getString().c_str()
|
|
|
|
) << endl;
|
|
|
|
}
|
|
|
|
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
ltrace(300) << " chunk: [" << DbU::getValueString((*ichunk).getVMin())
|
|
|
|
<< ":" << DbU::getValueString((*ichunk).getVMax()) << "]" << endl;
|
|
|
|
|
|
|
|
segment = Horizontal::create ( net
|
|
|
|
, layer
|
|
|
|
, _axis
|
|
|
|
, _width
|
|
|
|
, (*ichunk).getVMin()+extension
|
|
|
|
, (*ichunk).getVMax()-extension
|
|
|
|
);
|
|
|
|
if ( segment and net->isExternal() )
|
|
|
|
NetExternalComponents::setExternal ( segment );
|
2010-03-09 09:24:55 -06:00
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
axisMin = _axis - _width/2 - delta;
|
|
|
|
axisMax = _axis + _width/2 + delta;
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
Track* track = plane->getTrackByPosition ( axisMin, Constant::Superior );
|
2013-12-03 18:59:29 -06:00
|
|
|
for ( ; track and (track->getAxis() <= axisMax) ; track = track->getNextTrack() ) {
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
TrackElement* element = TrackFixedSegment::create ( track, segment );
|
|
|
|
ltrace(300) << " Insert in " << track << "+" << element << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
list<Interval>::iterator ichunk = _chunks.begin();
|
|
|
|
for ( ; ichunk != _chunks.end() ; ichunk++ ) {
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
ltrace(300) << " chunk: [" << DbU::getValueString((*ichunk).getVMin())
|
|
|
|
<< ":" << DbU::getValueString((*ichunk).getVMax()) << "]" << endl;
|
|
|
|
|
|
|
|
segment = Vertical::create ( net
|
|
|
|
, layer
|
|
|
|
, _axis
|
|
|
|
, _width
|
|
|
|
, (*ichunk).getVMin()+extension
|
|
|
|
, (*ichunk).getVMax()-extension
|
|
|
|
);
|
|
|
|
if ( segment and net->isExternal() )
|
|
|
|
NetExternalComponents::setExternal ( segment );
|
2010-03-09 09:24:55 -06:00
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
axisMin = _axis - _width/2 - delta;
|
|
|
|
axisMax = _axis + _width/2 + delta;
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
Track* track = plane->getTrackByPosition ( axisMin, Constant::Superior );
|
2013-12-03 18:59:29 -06:00
|
|
|
for ( ; track and (track->getAxis() <= axisMax) ; track = track->getNextTrack() ) {
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
TrackElement* element = TrackFixedSegment::create ( track, segment );
|
2013-12-03 18:59:29 -06:00
|
|
|
ltrace(300) << " Insert in " << track << "+" << element << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
string PowerRailsPlanes::Rail::_getString () const
|
|
|
|
{
|
|
|
|
ostringstream os;
|
|
|
|
|
|
|
|
os << "<Rail " << ((getDirection()==KbHorizontal) ? "Horizontal" : "Vertical")
|
|
|
|
<< " @" << DbU::getValueString(_axis) << " ";
|
|
|
|
list<Interval>::const_iterator ichunk = _chunks.begin();
|
|
|
|
for ( ; ichunk != _chunks.end() ; ++ichunk ) {
|
|
|
|
if (ichunk != _chunks.begin()) os << " ";
|
|
|
|
os << "[" << DbU::getValueString((*ichunk).getVMin())
|
|
|
|
<< " " << DbU::getValueString((*ichunk).getVMax()) << "]";
|
|
|
|
}
|
|
|
|
os << ">";
|
|
|
|
return os.str();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
inline bool PowerRailsPlanes::RailCompare::operator() ( const Rail* lhs, const Rail* rhs )
|
|
|
|
{
|
|
|
|
if ( lhs->getAxis () < rhs->getAxis () ) return true;
|
|
|
|
if ( lhs->getWidth() < rhs->getWidth() ) return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
inline PowerRailsPlanes::RailMatch::RailMatch ( DbU::Unit axis, DbU::Unit width )
|
|
|
|
: _axis(axis)
|
|
|
|
, _width(width)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
|
|
|
|
inline bool PowerRailsPlanes::RailMatch::operator() ( const Rail* rail )
|
|
|
|
{ return (rail->getAxis() == _axis) and (rail->getWidth() == _width); }
|
|
|
|
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
PowerRailsPlanes::Rails::Rails ( PowerRailsPlanes::Plane* plane , unsigned int direction , Net* net )
|
|
|
|
: _plane (plane)
|
|
|
|
, _direction (direction)
|
|
|
|
, _net (net)
|
|
|
|
, _rails ()
|
2010-03-09 09:24:55 -06:00
|
|
|
{
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
ltrace(300) << " new Rails @"
|
|
|
|
<< " " << getRoutingPlane()->getLayer()->getName()
|
|
|
|
<< " " << net
|
2013-12-03 18:59:29 -06:00
|
|
|
<< " " << ((getDirection()==KbHorizontal) ? "Horizontal": "Vertical") << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
PowerRailsPlanes::Rails::~Rails ()
|
|
|
|
{
|
|
|
|
while ( not _rails.empty() ) {
|
|
|
|
delete (*_rails.begin());
|
|
|
|
_rails.erase ( _rails.begin() );
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
inline PowerRailsPlanes::Plane* PowerRailsPlanes::Rails::getPlane () { return _plane; }
|
|
|
|
inline RoutingPlane* PowerRailsPlanes::Rails::getRoutingPlane () { return getPlane()->getRoutingPlane(); }
|
|
|
|
inline unsigned int PowerRailsPlanes::Rails::getDirection () const { return _direction; }
|
|
|
|
inline Net* PowerRailsPlanes::Rails::getNet () const { return _net; }
|
2010-03-09 09:24:55 -06:00
|
|
|
|
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
void PowerRailsPlanes::Rails::merge ( const Box& bb )
|
2010-03-09 09:24:55 -06:00
|
|
|
{
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
DbU::Unit axis;
|
|
|
|
DbU::Unit width;
|
|
|
|
DbU::Unit sourceU;
|
|
|
|
DbU::Unit targetU;
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
if (getDirection() == KbHorizontal) {
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
axis = bb.getYCenter();
|
|
|
|
width = bb.getHeight();
|
|
|
|
sourceU = bb.getXMin();
|
|
|
|
targetU = bb.getXMax();
|
|
|
|
} else {
|
|
|
|
axis = bb.getXCenter();
|
|
|
|
width = bb.getWidth();
|
|
|
|
sourceU = bb.getYMin();
|
|
|
|
targetU = bb.getYMax();
|
|
|
|
}
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
vector<Rail*>::iterator irail = find_if ( _rails.begin(), _rails.end(), RailMatch(axis,width) );
|
|
|
|
|
|
|
|
Rail* rail = NULL;
|
|
|
|
if ( irail == _rails.end() ) {
|
|
|
|
rail = new Rail(this,axis,width);
|
|
|
|
_rails.push_back ( rail );
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
stable_sort ( _rails.begin(), _rails.end(), RailCompare() );
|
2010-03-09 09:24:55 -06:00
|
|
|
} else {
|
|
|
|
rail = *irail;
|
|
|
|
}
|
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
rail->merge ( sourceU, targetU );
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
void PowerRailsPlanes::Rails::doLayout ( const Layer* layer )
|
2010-03-09 09:24:55 -06:00
|
|
|
{
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
ltrace(300) << "Doing layout of rails: " << layer->getName()
|
2013-12-03 18:59:29 -06:00
|
|
|
<< " " << ((_direction==KbHorizontal) ? "Horizontal" : "Vertical")
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
<< " " << _net->getName() << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
|
|
|
|
for ( size_t irail=0 ; irail<_rails.size() ; irail++ )
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
_rails[irail]->doLayout ( layer );
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
PowerRailsPlanes::Plane::Plane ( const Layer* layer, RoutingPlane* routingPlane )
|
2010-03-09 09:24:55 -06:00
|
|
|
: _layer (layer)
|
|
|
|
, _routingPlane (routingPlane)
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
, _horizontalRails ()
|
|
|
|
, _verticalRails ()
|
2013-12-03 18:59:29 -06:00
|
|
|
, _powerDirection (routingPlane->getDirection())
|
2010-03-09 09:24:55 -06:00
|
|
|
{
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
ltrace(300) << "New Plane " << _layer->getName() << " " << _routingPlane << endl;
|
2013-12-03 18:59:29 -06:00
|
|
|
|
|
|
|
// Hard-coded SxLib gauge.
|
|
|
|
if (_routingPlane->getDepth() == 0) _powerDirection = KbHorizontal;
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
PowerRailsPlanes::Plane::~Plane ()
|
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
RailsMap::iterator irail = _horizontalRails.begin();
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
for ( ; irail != _horizontalRails.end() ; ++irail ) {
|
|
|
|
delete (*irail).second;
|
|
|
|
}
|
|
|
|
irail = _verticalRails.begin();
|
|
|
|
for ( ; irail != _verticalRails.end() ; ++irail ) {
|
|
|
|
delete (*irail).second;
|
|
|
|
}
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
inline const Layer* PowerRailsPlanes::Plane::getLayer () const { return _layer; }
|
|
|
|
inline RoutingPlane* PowerRailsPlanes::Plane::getRoutingPlane () { return _routingPlane; }
|
|
|
|
inline unsigned int PowerRailsPlanes::Plane::getDirection () const { return _routingPlane->getDirection(); }
|
|
|
|
inline unsigned int PowerRailsPlanes::Plane::getPowerDirection () const { return _powerDirection; }
|
2010-03-09 09:24:55 -06:00
|
|
|
|
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
void PowerRailsPlanes::Plane::merge ( const Box& bb, Net* net )
|
2010-03-09 09:24:55 -06:00
|
|
|
{
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
Rails* rails = NULL;
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
ltrace(300) << " Plane::merge() " << net->getName() << " " << bb << endl;
|
|
|
|
|
|
|
|
unsigned int direction = getDirection();
|
|
|
|
if ( (net->getType() == Net::Type::POWER) or (net->getType() == Net::Type::GROUND) )
|
|
|
|
direction = getPowerDirection();
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
if (direction == KbHorizontal) {
|
|
|
|
RailsMap::iterator irails = _horizontalRails.find(net);
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
if ( irails == _horizontalRails.end() ) {
|
2013-12-03 18:59:29 -06:00
|
|
|
rails = new Rails(this,KbHorizontal,net);
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
_horizontalRails.insert ( make_pair(net,rails) );
|
|
|
|
} else
|
|
|
|
rails = (*irails).second;
|
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
rails->merge ( bb );
|
2010-03-09 09:24:55 -06:00
|
|
|
} else {
|
2013-12-03 18:59:29 -06:00
|
|
|
RailsMap::iterator irails = _verticalRails.find(net);
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
if ( irails == _verticalRails.end() ) {
|
2013-12-03 18:59:29 -06:00
|
|
|
rails = new Rails(this,KbVertical,net);
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
_verticalRails.insert ( make_pair(net,rails) );
|
|
|
|
} else
|
|
|
|
rails = (*irails).second;
|
|
|
|
|
2012-01-03 11:04:00 -06:00
|
|
|
ltrace(300) << " Vertical Merging" << endl;
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
rails->merge ( bb );
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
void PowerRailsPlanes::Plane::doLayout ()
|
2010-03-09 09:24:55 -06:00
|
|
|
{
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
ltrace(300) << "Doing layout of plane: " << _layer->getName() << endl;
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
RailsMap::iterator irails = _horizontalRails.begin();
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
for ( ; irails != _horizontalRails.end() ; ++irails ) {
|
|
|
|
(*irails).second->doLayout(_layer);
|
|
|
|
}
|
|
|
|
irails = _verticalRails.begin();
|
|
|
|
for ( ; irails != _verticalRails.end() ; ++irails ) {
|
|
|
|
(*irails).second->doLayout(_layer);
|
|
|
|
}
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
PowerRailsPlanes::PowerRailsPlanes ( KiteEngine* kite )
|
|
|
|
: _kite (kite)
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
, _globalNets (kite->getCell())
|
2010-03-09 09:24:55 -06:00
|
|
|
, _planes ()
|
|
|
|
, _activePlane(NULL)
|
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
_globalNets.setBlockage( kite->getBlockageNet() );
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
Technology* technology = DataBase::getDB()->getTechnology();
|
|
|
|
RoutingGauge* rg = _kite->getConfiguration()->getRoutingGauge();
|
|
|
|
|
|
|
|
forEach ( Layer*, iLayer, technology->getLayers() ) {
|
|
|
|
RegularLayer* regular = dynamic_cast<RegularLayer*>(*iLayer);
|
|
|
|
if ( not regular
|
|
|
|
or (regular->getBasicLayer()->getMaterial() != BasicLayer::Material::metal) ) continue;
|
|
|
|
|
|
|
|
RoutingLayerGauge* lg = rg->getLayerGauge(regular);
|
|
|
|
if ( not lg ) continue;
|
|
|
|
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
ltrace(300) << "Gauge: [" << lg->getDepth() << "] " << lg << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
|
|
|
|
RoutingPlane* rp = _kite->getRoutingPlaneByIndex(lg->getDepth());
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
ltrace(300) << "Plane:" << rp << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
_planes.insert( make_pair(regular->getBasicLayer(),new Plane(regular,rp)) );
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
|
|
|
|
const BasicLayer* blockageLayer = regular->getBasicLayer()->getBlockageLayer();
|
2013-12-03 18:59:29 -06:00
|
|
|
if (not blockageLayer) continue;
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
_planes.insert( make_pair(blockageLayer,new Plane(blockageLayer,rp)) );
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
PowerRailsPlanes::~PowerRailsPlanes ()
|
|
|
|
{
|
|
|
|
while ( not _planes.empty() ) {
|
|
|
|
delete _planes.begin()->second;
|
|
|
|
_planes.erase ( _planes.begin() );
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
|
|
|
inline Net* PowerRailsPlanes::getRootNet ( Net* net, Path path )
|
|
|
|
{ return _globalNets.getRootNet(net,path); }
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
|
|
|
|
bool PowerRailsPlanes::hasPlane ( const BasicLayer* layer )
|
|
|
|
{ return (_planes.find(layer) != _planes.end()); }
|
|
|
|
|
|
|
|
|
|
|
|
bool PowerRailsPlanes::setActivePlane ( const BasicLayer* layer )
|
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
PlanesMap::iterator iplane = _planes.find(layer);
|
2010-03-09 09:24:55 -06:00
|
|
|
if ( iplane == _planes.end() ) return false;
|
|
|
|
|
|
|
|
_activePlane = iplane->second;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
inline PowerRailsPlanes::Plane* PowerRailsPlanes::getActivePlane () const
|
|
|
|
{ return _activePlane; }
|
|
|
|
|
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
void PowerRailsPlanes::merge ( const Box& bb, Net* net )
|
2010-03-09 09:24:55 -06:00
|
|
|
{
|
|
|
|
if ( not _activePlane ) return;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
|
|
|
Net* topGlobalNet = _globalNets.getRootNet ( net, Path() );
|
2012-01-03 11:04:00 -06:00
|
|
|
if ( topGlobalNet == NULL ) {
|
|
|
|
ltrace(300) << "Not a global net: " << net << endl;
|
|
|
|
return;
|
|
|
|
}
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
_activePlane->merge ( bb, topGlobalNet );
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void PowerRailsPlanes::doLayout ()
|
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
PlanesMap::iterator iplane = _planes.begin();
|
2010-03-09 09:24:55 -06:00
|
|
|
for ( ; iplane != _planes.end() ; iplane++ )
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
iplane->second->doLayout ();
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// -------------------------------------------------------------------
|
|
|
|
// Class : "::QueryPowerRails".
|
|
|
|
|
|
|
|
class QueryPowerRails : public Query {
|
|
|
|
public:
|
2010-08-18 15:25:02 -05:00
|
|
|
QueryPowerRails ( KiteEngine* );
|
2010-03-09 09:24:55 -06:00
|
|
|
virtual bool hasGoCallback () const;
|
|
|
|
virtual void setBasicLayer ( const BasicLayer* );
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
virtual bool hasBasicLayer ( const BasicLayer* );
|
2010-03-09 09:24:55 -06:00
|
|
|
virtual void goCallback ( Go* );
|
|
|
|
virtual void rubberCallback ( Rubber* );
|
|
|
|
virtual void extensionGoCallback ( Go* );
|
|
|
|
virtual void masterCellCallback ();
|
|
|
|
void addToPowerRail ( const Go* go
|
|
|
|
, const BasicLayer* basicLayer
|
|
|
|
, const Box& area
|
|
|
|
, const Transformation& transformation
|
|
|
|
);
|
* ./Kite:
- New: In BuildPowerRails, special processing for the power ring segments.
The "diagonal" of vias at each corner is causing a misbehavior of the
routing algorithm (due to fully saturated GCells in one direction).
As a temporary fix, extend the segments so they form a "square corner".
(problem arise on "d_in_i(22)").
- New: In RoutingEvent::_processNegociate, disable the "isForcedToHint()"
feature. No noticeable loss of quality or speed.
- New: In TrackElement/TrackSegment, wraps the AutoSegment parent's mechanism.
Allows to gets the DataNegociate of either the segment or it's parent.
- New: State::solveFullBlockages(), dedicated method to solves the case when
all the allowed tracks of a segment are blocked, tries to moves up
local segments and to break-up global ones.
- New: RoutingEventLoop, a more sophisticated way to detect looping.
Maintain a dynamic histogram of the last N (default 10) segments routeds,
with the count of how many times they have occurred. If that count
exeed 40, we *may* be facing a loop.
- Change: In State::conflictSolve1, implement new policy. The global segments
no more can be broken by local ones. The idea behind is that breaking
a global on the request of a local will only produce more cluttering
in the GCell. Globals must be keep straigth pass through, especially
inside near-saturated GCells. Globals breaking however can occurs at
another global's request.
- Change: In TrackCost, implement the new policy about locals segments that
cannot break globals segments. The sorting class now accept flags to
modulate the sorting function. Two options avalaibles: IgnoreAxisWeigth
(to uses for strap segments) and DiscardGlobals (to uses with locals).
- Change: In TrackCost, the "distance to fixed" have now an upper bound of
50 lambdas (no need to be greater because it means it's outside the
begin & en GCells). Take account not only of fixed segment, but also
of placed segments which makes bound.
- Bug: In Track::_check(), while calling each individual TrackSegment check,
uses it as the *first* argument of the "or", otherwise it may not be
called.
- Bug: In ProtectRoutingPad, loop over segment Collections while modificating
it was producing non-deterministic results. The fact that a collection
must be not modificated while beeing iterated is becoming a more and more
painful problem.
2010-12-30 12:42:17 -06:00
|
|
|
void ringAddToPowerRails ();
|
2010-03-09 09:24:55 -06:00
|
|
|
virtual void doQuery ();
|
|
|
|
inline void doLayout ();
|
|
|
|
inline unsigned int getGoMatchCount () const;
|
|
|
|
private:
|
* ./Kite:
- New: In BuildPowerRails, special processing for the power ring segments.
The "diagonal" of vias at each corner is causing a misbehavior of the
routing algorithm (due to fully saturated GCells in one direction).
As a temporary fix, extend the segments so they form a "square corner".
(problem arise on "d_in_i(22)").
- New: In RoutingEvent::_processNegociate, disable the "isForcedToHint()"
feature. No noticeable loss of quality or speed.
- New: In TrackElement/TrackSegment, wraps the AutoSegment parent's mechanism.
Allows to gets the DataNegociate of either the segment or it's parent.
- New: State::solveFullBlockages(), dedicated method to solves the case when
all the allowed tracks of a segment are blocked, tries to moves up
local segments and to break-up global ones.
- New: RoutingEventLoop, a more sophisticated way to detect looping.
Maintain a dynamic histogram of the last N (default 10) segments routeds,
with the count of how many times they have occurred. If that count
exeed 40, we *may* be facing a loop.
- Change: In State::conflictSolve1, implement new policy. The global segments
no more can be broken by local ones. The idea behind is that breaking
a global on the request of a local will only produce more cluttering
in the GCell. Globals must be keep straigth pass through, especially
inside near-saturated GCells. Globals breaking however can occurs at
another global's request.
- Change: In TrackCost, implement the new policy about locals segments that
cannot break globals segments. The sorting class now accept flags to
modulate the sorting function. Two options avalaibles: IgnoreAxisWeigth
(to uses for strap segments) and DiscardGlobals (to uses with locals).
- Change: In TrackCost, the "distance to fixed" have now an upper bound of
50 lambdas (no need to be greater because it means it's outside the
begin & en GCells). Take account not only of fixed segment, but also
of placed segments which makes bound.
- Bug: In Track::_check(), while calling each individual TrackSegment check,
uses it as the *first* argument of the "or", otherwise it may not be
called.
- Bug: In ProtectRoutingPad, loop over segment Collections while modificating
it was producing non-deterministic results. The fact that a collection
must be not modificated while beeing iterated is becoming a more and more
painful problem.
2010-12-30 12:42:17 -06:00
|
|
|
AllianceFramework* _framework;
|
|
|
|
KiteEngine* _kite;
|
|
|
|
RoutingGauge* _routingGauge;
|
|
|
|
const ChipTools& _chipTools;
|
|
|
|
PowerRailsPlanes _powerRailsPlanes;
|
|
|
|
bool _isBlockagePlane;
|
|
|
|
vector<const Segment*> _hRingSegments;
|
|
|
|
vector<const Segment*> _vRingSegments;
|
|
|
|
unsigned int _goMatchCount;
|
2010-03-09 09:24:55 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
QueryPowerRails::QueryPowerRails ( KiteEngine* kite )
|
|
|
|
: Query ()
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
, _framework (AllianceFramework::get())
|
2010-03-09 09:24:55 -06:00
|
|
|
, _kite (kite)
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
, _routingGauge (kite->getConfiguration()->getRoutingGauge())
|
* ./Kite:
- New: In BuildPowerRails, special processing for the power ring segments.
The "diagonal" of vias at each corner is causing a misbehavior of the
routing algorithm (due to fully saturated GCells in one direction).
As a temporary fix, extend the segments so they form a "square corner".
(problem arise on "d_in_i(22)").
- New: In RoutingEvent::_processNegociate, disable the "isForcedToHint()"
feature. No noticeable loss of quality or speed.
- New: In TrackElement/TrackSegment, wraps the AutoSegment parent's mechanism.
Allows to gets the DataNegociate of either the segment or it's parent.
- New: State::solveFullBlockages(), dedicated method to solves the case when
all the allowed tracks of a segment are blocked, tries to moves up
local segments and to break-up global ones.
- New: RoutingEventLoop, a more sophisticated way to detect looping.
Maintain a dynamic histogram of the last N (default 10) segments routeds,
with the count of how many times they have occurred. If that count
exeed 40, we *may* be facing a loop.
- Change: In State::conflictSolve1, implement new policy. The global segments
no more can be broken by local ones. The idea behind is that breaking
a global on the request of a local will only produce more cluttering
in the GCell. Globals must be keep straigth pass through, especially
inside near-saturated GCells. Globals breaking however can occurs at
another global's request.
- Change: In TrackCost, implement the new policy about locals segments that
cannot break globals segments. The sorting class now accept flags to
modulate the sorting function. Two options avalaibles: IgnoreAxisWeigth
(to uses for strap segments) and DiscardGlobals (to uses with locals).
- Change: In TrackCost, the "distance to fixed" have now an upper bound of
50 lambdas (no need to be greater because it means it's outside the
begin & en GCells). Take account not only of fixed segment, but also
of placed segments which makes bound.
- Bug: In Track::_check(), while calling each individual TrackSegment check,
uses it as the *first* argument of the "or", otherwise it may not be
called.
- Bug: In ProtectRoutingPad, loop over segment Collections while modificating
it was producing non-deterministic results. The fact that a collection
must be not modificated while beeing iterated is becoming a more and more
painful problem.
2010-12-30 12:42:17 -06:00
|
|
|
, _chipTools (kite->getChipTools())
|
2010-03-09 09:24:55 -06:00
|
|
|
, _powerRailsPlanes(kite)
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
, _isBlockagePlane (false)
|
* ./Kite:
- New: In BuildPowerRails, special processing for the power ring segments.
The "diagonal" of vias at each corner is causing a misbehavior of the
routing algorithm (due to fully saturated GCells in one direction).
As a temporary fix, extend the segments so they form a "square corner".
(problem arise on "d_in_i(22)").
- New: In RoutingEvent::_processNegociate, disable the "isForcedToHint()"
feature. No noticeable loss of quality or speed.
- New: In TrackElement/TrackSegment, wraps the AutoSegment parent's mechanism.
Allows to gets the DataNegociate of either the segment or it's parent.
- New: State::solveFullBlockages(), dedicated method to solves the case when
all the allowed tracks of a segment are blocked, tries to moves up
local segments and to break-up global ones.
- New: RoutingEventLoop, a more sophisticated way to detect looping.
Maintain a dynamic histogram of the last N (default 10) segments routeds,
with the count of how many times they have occurred. If that count
exeed 40, we *may* be facing a loop.
- Change: In State::conflictSolve1, implement new policy. The global segments
no more can be broken by local ones. The idea behind is that breaking
a global on the request of a local will only produce more cluttering
in the GCell. Globals must be keep straigth pass through, especially
inside near-saturated GCells. Globals breaking however can occurs at
another global's request.
- Change: In TrackCost, implement the new policy about locals segments that
cannot break globals segments. The sorting class now accept flags to
modulate the sorting function. Two options avalaibles: IgnoreAxisWeigth
(to uses for strap segments) and DiscardGlobals (to uses with locals).
- Change: In TrackCost, the "distance to fixed" have now an upper bound of
50 lambdas (no need to be greater because it means it's outside the
begin & en GCells). Take account not only of fixed segment, but also
of placed segments which makes bound.
- Bug: In Track::_check(), while calling each individual TrackSegment check,
uses it as the *first* argument of the "or", otherwise it may not be
called.
- Bug: In ProtectRoutingPad, loop over segment Collections while modificating
it was producing non-deterministic results. The fact that a collection
must be not modificated while beeing iterated is becoming a more and more
painful problem.
2010-12-30 12:42:17 -06:00
|
|
|
, _hRingSegments ()
|
|
|
|
, _vRingSegments ()
|
2010-03-09 09:24:55 -06:00
|
|
|
, _goMatchCount (0)
|
|
|
|
{
|
|
|
|
setCell ( kite->getCell() );
|
|
|
|
setArea ( kite->getCell()->getBoundingBox() );
|
|
|
|
setBasicLayer ( NULL );
|
|
|
|
setFilter ( Query::DoTerminalCells|Query::DoComponents );
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
inline unsigned int QueryPowerRails::getGoMatchCount () const
|
|
|
|
{ return _goMatchCount; }
|
|
|
|
|
|
|
|
|
|
|
|
inline void QueryPowerRails::doLayout ()
|
|
|
|
{ return _powerRailsPlanes.doLayout(); }
|
|
|
|
|
|
|
|
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
bool QueryPowerRails::hasBasicLayer ( const BasicLayer* basicLayer )
|
|
|
|
{ return _powerRailsPlanes.hasPlane ( basicLayer ); }
|
|
|
|
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
void QueryPowerRails::setBasicLayer ( const BasicLayer* basicLayer )
|
|
|
|
{
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
_isBlockagePlane = (basicLayer) and (basicLayer->getMaterial() == BasicLayer::Material::blockage);
|
2010-03-09 09:24:55 -06:00
|
|
|
_powerRailsPlanes.setActivePlane ( basicLayer );
|
|
|
|
Query::setBasicLayer ( basicLayer );
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void QueryPowerRails::doQuery ()
|
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
PowerRailsPlanes::Plane* activePlane = _powerRailsPlanes.getActivePlane();
|
|
|
|
|
|
|
|
if (not activePlane) return;
|
|
|
|
// if (activePlane->getRoutingPlane()->getLayerGauge()->getType() == Constant::PinOnly) {
|
|
|
|
// cmess1 << " - PowerRails in " << activePlane->getLayer()->getName() << " - Skipped (PinOnly layer)." << endl;
|
|
|
|
// return;
|
|
|
|
// }
|
|
|
|
|
|
|
|
cmess1 << " - PowerRails in " << activePlane->getLayer()->getName() << " ..." << endl;
|
|
|
|
Query::doQuery();
|
* ./Kite:
- New: In BuildPowerRails, special processing for the power ring segments.
The "diagonal" of vias at each corner is causing a misbehavior of the
routing algorithm (due to fully saturated GCells in one direction).
As a temporary fix, extend the segments so they form a "square corner".
(problem arise on "d_in_i(22)").
- New: In RoutingEvent::_processNegociate, disable the "isForcedToHint()"
feature. No noticeable loss of quality or speed.
- New: In TrackElement/TrackSegment, wraps the AutoSegment parent's mechanism.
Allows to gets the DataNegociate of either the segment or it's parent.
- New: State::solveFullBlockages(), dedicated method to solves the case when
all the allowed tracks of a segment are blocked, tries to moves up
local segments and to break-up global ones.
- New: RoutingEventLoop, a more sophisticated way to detect looping.
Maintain a dynamic histogram of the last N (default 10) segments routeds,
with the count of how many times they have occurred. If that count
exeed 40, we *may* be facing a loop.
- Change: In State::conflictSolve1, implement new policy. The global segments
no more can be broken by local ones. The idea behind is that breaking
a global on the request of a local will only produce more cluttering
in the GCell. Globals must be keep straigth pass through, especially
inside near-saturated GCells. Globals breaking however can occurs at
another global's request.
- Change: In TrackCost, implement the new policy about locals segments that
cannot break globals segments. The sorting class now accept flags to
modulate the sorting function. Two options avalaibles: IgnoreAxisWeigth
(to uses for strap segments) and DiscardGlobals (to uses with locals).
- Change: In TrackCost, the "distance to fixed" have now an upper bound of
50 lambdas (no need to be greater because it means it's outside the
begin & en GCells). Take account not only of fixed segment, but also
of placed segments which makes bound.
- Bug: In Track::_check(), while calling each individual TrackSegment check,
uses it as the *first* argument of the "or", otherwise it may not be
called.
- Bug: In ProtectRoutingPad, loop over segment Collections while modificating
it was producing non-deterministic results. The fact that a collection
must be not modificated while beeing iterated is becoming a more and more
painful problem.
2010-12-30 12:42:17 -06:00
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void QueryPowerRails::masterCellCallback ()
|
|
|
|
{ }
|
|
|
|
|
|
|
|
|
|
|
|
bool QueryPowerRails::hasGoCallback () const
|
|
|
|
{ return true; }
|
|
|
|
|
|
|
|
|
|
|
|
void QueryPowerRails::goCallback ( Go* go )
|
|
|
|
{
|
2013-12-03 18:59:29 -06:00
|
|
|
//ltrace(80) << "QueryPowerRails::goCallback() " << go->getId() << ":" << go
|
|
|
|
// << " " << getPath().getName() << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
addToPowerRail ( go, getBasicLayer(), getArea(), getTransformation() );
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void QueryPowerRails::addToPowerRail ( const Go* go
|
|
|
|
, const BasicLayer* basicLayer
|
|
|
|
, const Box& area
|
|
|
|
, const Transformation& transformation
|
|
|
|
)
|
|
|
|
{
|
|
|
|
const Component* component = dynamic_cast<const Component*>(go);
|
|
|
|
if ( component ) {
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
if ( _framework->isPad(getMasterCell())
|
|
|
|
and (_routingGauge->getLayerDepth(component->getLayer()) < 2) )
|
|
|
|
return;
|
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
Net* rootNet = NULL;
|
|
|
|
if ( not _isBlockagePlane )
|
|
|
|
rootNet = _powerRailsPlanes.getRootNet(component->getNet(),getPath());
|
|
|
|
else
|
|
|
|
rootNet = _kite->getBlockageNet();
|
|
|
|
if ( rootNet == NULL ) return;
|
2010-03-09 09:24:55 -06:00
|
|
|
|
|
|
|
const Segment* segment = dynamic_cast<const Segment*>(component);
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
if ( segment != NULL ) {
|
|
|
|
_goMatchCount++;
|
|
|
|
ltrace(300) << " Merging PowerRail element: " << segment << endl;
|
2010-03-09 09:24:55 -06:00
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
Box bb = segment->getBoundingBox ( basicLayer );
|
* ./Kite:
- New: In BuildPowerRails, special processing for the power ring segments.
The "diagonal" of vias at each corner is causing a misbehavior of the
routing algorithm (due to fully saturated GCells in one direction).
As a temporary fix, extend the segments so they form a "square corner".
(problem arise on "d_in_i(22)").
- New: In RoutingEvent::_processNegociate, disable the "isForcedToHint()"
feature. No noticeable loss of quality or speed.
- New: In TrackElement/TrackSegment, wraps the AutoSegment parent's mechanism.
Allows to gets the DataNegociate of either the segment or it's parent.
- New: State::solveFullBlockages(), dedicated method to solves the case when
all the allowed tracks of a segment are blocked, tries to moves up
local segments and to break-up global ones.
- New: RoutingEventLoop, a more sophisticated way to detect looping.
Maintain a dynamic histogram of the last N (default 10) segments routeds,
with the count of how many times they have occurred. If that count
exeed 40, we *may* be facing a loop.
- Change: In State::conflictSolve1, implement new policy. The global segments
no more can be broken by local ones. The idea behind is that breaking
a global on the request of a local will only produce more cluttering
in the GCell. Globals must be keep straigth pass through, especially
inside near-saturated GCells. Globals breaking however can occurs at
another global's request.
- Change: In TrackCost, implement the new policy about locals segments that
cannot break globals segments. The sorting class now accept flags to
modulate the sorting function. Two options avalaibles: IgnoreAxisWeigth
(to uses for strap segments) and DiscardGlobals (to uses with locals).
- Change: In TrackCost, the "distance to fixed" have now an upper bound of
50 lambdas (no need to be greater because it means it's outside the
begin & en GCells). Take account not only of fixed segment, but also
of placed segments which makes bound.
- Bug: In Track::_check(), while calling each individual TrackSegment check,
uses it as the *first* argument of the "or", otherwise it may not be
called.
- Bug: In ProtectRoutingPad, loop over segment Collections while modificating
it was producing non-deterministic results. The fact that a collection
must be not modificated while beeing iterated is becoming a more and more
painful problem.
2010-12-30 12:42:17 -06:00
|
|
|
|
|
|
|
unsigned int depth = _routingGauge->getLayerDepth ( segment->getLayer() );
|
|
|
|
|
|
|
|
if ( _chipTools.isChip()
|
|
|
|
and ((depth == 2) or (depth == 3))
|
|
|
|
and (segment->getWidth () == DbU::lambda( 12.0))
|
|
|
|
and (segment->getLength() > DbU::lambda(200.0))
|
|
|
|
and (_kite->getChipTools().getCorona().contains(bb)) ) {
|
|
|
|
switch ( depth ) {
|
|
|
|
case 2: _vRingSegments.push_back ( segment ); break; // M3 V.
|
|
|
|
case 3: _hRingSegments.push_back ( segment ); break; // M4 H.
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
transformation.applyOn ( bb );
|
2010-03-09 09:24:55 -06:00
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
_powerRailsPlanes.merge ( bb, rootNet );
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
} else {
|
|
|
|
const Contact* contact = dynamic_cast<const Contact*>(component);
|
|
|
|
if ( contact != NULL ) {
|
|
|
|
_goMatchCount++;
|
|
|
|
|
|
|
|
Box bb = contact->getBoundingBox ( basicLayer );
|
|
|
|
transformation.applyOn ( bb );
|
|
|
|
|
2012-01-03 11:04:00 -06:00
|
|
|
ltrace(300) << " Merging PowerRail element: " << contact << " bb:" << bb
|
|
|
|
<< " " << basicLayer << endl;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
_powerRailsPlanes.merge ( bb, rootNet );
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
}
|
|
|
|
}
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
* ./Kite:
- New: In BuildPowerRails, special processing for the power ring segments.
The "diagonal" of vias at each corner is causing a misbehavior of the
routing algorithm (due to fully saturated GCells in one direction).
As a temporary fix, extend the segments so they form a "square corner".
(problem arise on "d_in_i(22)").
- New: In RoutingEvent::_processNegociate, disable the "isForcedToHint()"
feature. No noticeable loss of quality or speed.
- New: In TrackElement/TrackSegment, wraps the AutoSegment parent's mechanism.
Allows to gets the DataNegociate of either the segment or it's parent.
- New: State::solveFullBlockages(), dedicated method to solves the case when
all the allowed tracks of a segment are blocked, tries to moves up
local segments and to break-up global ones.
- New: RoutingEventLoop, a more sophisticated way to detect looping.
Maintain a dynamic histogram of the last N (default 10) segments routeds,
with the count of how many times they have occurred. If that count
exeed 40, we *may* be facing a loop.
- Change: In State::conflictSolve1, implement new policy. The global segments
no more can be broken by local ones. The idea behind is that breaking
a global on the request of a local will only produce more cluttering
in the GCell. Globals must be keep straigth pass through, especially
inside near-saturated GCells. Globals breaking however can occurs at
another global's request.
- Change: In TrackCost, implement the new policy about locals segments that
cannot break globals segments. The sorting class now accept flags to
modulate the sorting function. Two options avalaibles: IgnoreAxisWeigth
(to uses for strap segments) and DiscardGlobals (to uses with locals).
- Change: In TrackCost, the "distance to fixed" have now an upper bound of
50 lambdas (no need to be greater because it means it's outside the
begin & en GCells). Take account not only of fixed segment, but also
of placed segments which makes bound.
- Bug: In Track::_check(), while calling each individual TrackSegment check,
uses it as the *first* argument of the "or", otherwise it may not be
called.
- Bug: In ProtectRoutingPad, loop over segment Collections while modificating
it was producing non-deterministic results. The fact that a collection
must be not modificated while beeing iterated is becoming a more and more
painful problem.
2010-12-30 12:42:17 -06:00
|
|
|
void QueryPowerRails::ringAddToPowerRails ()
|
|
|
|
{
|
|
|
|
|
|
|
|
if ( not _hRingSegments.empty() ) {
|
|
|
|
const RegularLayer* layer = dynamic_cast<const RegularLayer*>(_routingGauge->getRoutingLayer(3));
|
|
|
|
setBasicLayer ( layer->getBasicLayer() );
|
|
|
|
|
|
|
|
DbU::Unit xmin = DbU::Max;
|
|
|
|
DbU::Unit xmax = DbU::Min;
|
|
|
|
vector<Box> boxes;
|
|
|
|
|
|
|
|
for ( size_t i=0 ; i<_hRingSegments.size() ; ++i ) {
|
|
|
|
boxes.push_back ( _hRingSegments[i]->getBoundingBox() );
|
|
|
|
xmin = std::min ( xmin, boxes.back().getXMin() );
|
|
|
|
xmax = std::max ( xmax, boxes.back().getXMax() );
|
|
|
|
}
|
|
|
|
|
|
|
|
for ( size_t i=0 ; i<_hRingSegments.size() ; ++i ) {
|
|
|
|
_powerRailsPlanes.merge ( Box(xmin,boxes[i].getYMin(),xmax,boxes[i].getYMax())
|
|
|
|
, _powerRailsPlanes.getRootNet(_hRingSegments[i]->getNet(),Path()) );
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( not _vRingSegments.empty() ) {
|
|
|
|
const RegularLayer* layer = dynamic_cast<const RegularLayer*>(_routingGauge->getRoutingLayer(2));
|
|
|
|
setBasicLayer ( layer->getBasicLayer() );
|
|
|
|
|
|
|
|
DbU::Unit ymin = DbU::Max;
|
|
|
|
DbU::Unit ymax = DbU::Min;
|
|
|
|
vector<Box> boxes;
|
|
|
|
|
|
|
|
for ( size_t i=0 ; i<_vRingSegments.size() ; ++i ) {
|
|
|
|
boxes.push_back ( _vRingSegments[i]->getBoundingBox() );
|
|
|
|
ymin = std::min ( ymin, boxes.back().getYMin() );
|
|
|
|
ymax = std::max ( ymax, boxes.back().getYMax() );
|
|
|
|
}
|
|
|
|
|
|
|
|
for ( size_t i=0 ; i<_vRingSegments.size() ; ++i ) {
|
|
|
|
_powerRailsPlanes.merge ( Box(boxes[i].getXMin(),ymin,boxes[i].getXMax(),ymax)
|
|
|
|
, _powerRailsPlanes.getRootNet(_vRingSegments[i]->getNet(),Path()) );
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
void QueryPowerRails::rubberCallback ( Rubber* )
|
|
|
|
{ }
|
|
|
|
|
|
|
|
|
|
|
|
void QueryPowerRails::extensionGoCallback ( Go* )
|
|
|
|
{ }
|
|
|
|
|
|
|
|
|
|
|
|
} // End of anonymous namespace.
|
|
|
|
|
|
|
|
|
|
|
|
namespace Kite {
|
|
|
|
|
|
|
|
|
|
|
|
using Hurricane::DataBase;
|
|
|
|
using Hurricane::Technology;
|
|
|
|
using Hurricane::BasicLayer;
|
|
|
|
using Hurricane::ForEachIterator;
|
|
|
|
|
|
|
|
|
|
|
|
void KiteEngine::buildPowerRails ()
|
|
|
|
{
|
|
|
|
cmess1 << " o Building power rails." << endl;
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
if (not _blockageNet) {
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
_blockageNet = getCell()->getNet("blockagenet");
|
2013-12-03 18:59:29 -06:00
|
|
|
if (not _blockageNet)
|
|
|
|
_blockageNet = Net::create( getCell(), "blockagenet" );
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
}
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
QueryPowerRails query ( this );
|
|
|
|
Technology* technology = DataBase::getDB()->getTechnology();
|
|
|
|
|
|
|
|
forEach ( BasicLayer*, iLayer, technology->getBasicLayers() ) {
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
if ( (iLayer->getMaterial() != BasicLayer::Material::metal)
|
|
|
|
and (iLayer->getMaterial() != BasicLayer::Material::blockage) )
|
|
|
|
continue;
|
2013-12-03 18:59:29 -06:00
|
|
|
if (_configuration->isGMetal(*iLayer)) continue;
|
|
|
|
if (not query.hasBasicLayer(*iLayer)) continue;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
query.setBasicLayer( *iLayer );
|
|
|
|
query.doQuery ();
|
2010-03-09 09:24:55 -06:00
|
|
|
}
|
2013-12-03 18:59:29 -06:00
|
|
|
query.ringAddToPowerRails();
|
|
|
|
query.doLayout();
|
2010-03-09 09:24:55 -06:00
|
|
|
cmess1 << " - " << query.getGoMatchCount() << " power rails elements found." << endl;
|
|
|
|
|
|
|
|
Session::revalidate ();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-12-03 18:59:29 -06:00
|
|
|
} // Kite namespace.
|