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coriolis/chamsin/etc/technology.hcmos9.dtr.xml

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Technology in progress beginning layout of transistor
2008-05-26 11:37:14 -05:00
<technology name="hcmos9">
<physical_rules>
getDataBase -> DataBase::getDB() Transistor layout ... in progress XML DTR technology parsing
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<rule name="minWidth" layer="cut0" value="0.16" ref="19-1"/>
new Technology management : symetric and asymetric rules new DTR file Transistor Layout in progress
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<arule name="minExtension" layer1="poly" layer2="cut0" value="0.07" ref="19-3"/>
getDataBase -> DataBase::getDB() Transistor layout ... in progress XML DTR technology parsing
2008-06-13 11:02:05 -05:00
new Technology management : symetric and asymetric rules new DTR file Transistor Layout in progress
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<arule name="minExtension" layer1="nImplant" layer2="poly" value="0.2" ref="16-17"/>
<arule name="minExtension" layer1="nImplant" layer2="active" value="0.18" ref="16-8"/>
getDataBase -> DataBase::getDB() Transistor layout ... in progress XML DTR technology parsing
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new Technology management : symetric and asymetric rules new DTR file Transistor Layout in progress
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<arule name="minGateEnclosure" layer1="pImplant" layer2="poly" value="0.4" ref="17-6"/>
<arule name="minEnclosure" layer1="pImplant" layer2="poly" value="0.2" ref="17-17"/>
<arule name="minExtension" layer1="pImplant" layer2="active" value="0.18" ref="17-8"/>
getDataBase -> DataBase::getDB() Transistor layout ... in progress XML DTR technology parsing
2008-06-13 11:02:05 -05:00
new Technology management : symetric and asymetric rules new DTR file Transistor Layout in progress
2008-06-16 13:04:27 -05:00
<arule name="minExtension" layer1="active" layer2="cut0" value="0.07" ref="19-4.a"/>
<arule name="minExtension" layer1="pImplant" layer2="cut0" value="0.09" ref="19-4.b"/>
<arule name="minExtension" layer1="nImplant" layer2="cut0" value="0.09" ref="19-4.c"/>
getDataBase -> DataBase::getDB() Transistor layout ... in progress XML DTR technology parsing
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<rule name="minSpacing" layer1="active" layer2="cut0" value="0.14" ref="19-5"/>
<rule name="minSpacing" layer1="active" layer2="poly" value="0.07" ref="13-5"/>
new Technology management : symetric and asymetric rules new DTR file Transistor Layout in progress
2008-06-16 13:04:27 -05:00
<arule name="minExtension" layer1="poly" layer2="active" value="0.18" ref="13-7"/>
getDataBase -> DataBase::getDB() Transistor layout ... in progress XML DTR technology parsing
2008-06-13 11:02:05 -05:00
Technology in progress beginning layout of transistor
2008-05-26 11:37:14 -05:00
</physical_rules>
</technology>